A radiation tolerant 5 Gb/s Laser Driver in 130 nm CMOS technology

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1 Journal of Instrumentation OPEN ACCESS A radiation tolerant 5 Gb/s Laser Driver in 130 nm CMOS technology To cite this article: G Mazza et al View the article online for updates and enhancements. Related content - The GBLD: a radiation tolerant laser driver for high energy physics applications G Mazza, F Tavernier, P Moreira et al. - Radiation-hard/high-speed parallel optical engine K K Gan, P Buchholz, H P Kagan et al. - The Versatile Link common project: feasibility report F Vasey, D Hall, T Huffman et al. Recent citations - A large Scintillating Fibre Tracker for LHCb R. Greim - The Versatile Transceiver: towards production readiness C Soós et al - The GBLD: a radiation tolerant laser driver for high energy physics applications G Mazza et al This content was downloaded from IP address on 02/09/2018 at 23:40

2 PUBLISHED BY IOP PUBLISHING FOR SISSA TOPICAL WORKSHOP ON ELECTRONICS FOR PARTICLE PHYSICS 2011, SEPTEMBER 2011, VIENNA, AUSTRIA RECEIVED: October 31, 2011 ACCEPTED: December 19, 2011 PUBLISHED: January 11, 2012 A radiation tolerant 5 Gb/s Laser Driver in 130 nm CMOS technology G. Mazza, a A. Rivetti, a P. Moreira, b K. Wyllie, b C. Soos, b J. Troska b and P. Gui c a INFN sezione di Torino, Via P. Giuria 1, Torino, Italy b CERN, Geneva, Switzerland c Southern Methodist University Dallas, Texas, U.S.A. mazza@to.infn.it ABSTRACT: The GigaBit Transceiver (GBT) project aims at the design of a radiation tolerant chip set for high speed optical data transmission. The chipset includes the GigaBit Laser Driver (GBLD), a radiation tolerant ASIC designed in a standard CMOS 130 nm technology. The GBLD is a laser driver designed to work to up to 5 Gb/s and capable to drive both Vertical Cavity Surface Emitting Lasers (VCSELs) and Edge Emitting Lasers (EELs). The GBLD can provide a modulation current up to 24 ma and a bias current up to 43 ma with the pre-emphasis function to compensate for external capacitive load. KEYWORDS: VLSI circuits; Radiation-hard electronics; Data acquisition circuits c 2012 IOP Publishing Ltd and SISSA doi: / /7/01/c01052

3 Contents 1 The GBT project 1 2 The GBt Laser Driver (GBLD) 2 3 Modulator architecture Output and emphasis stages Radiation tolerance 5 4 The GBLD ASIC 6 5 Test results 7 6 Conclusions 8 1 The GBT project The upgrade of the LHC experiments will lead to an increase of luminosity and detector granularity. Therefore a significant increase in the amount of data to be transmitted to the data acquisition system is expected. The same requirements will characterize high energy physics experiments in the new accelerator facilities under construction around the world. Optical transmission is the obvious choice where high data rate is required while keeping the number of cables and therefore the amount of material at minimum. While on the outer detectors it is possible to use commercial transceivers, in the inner detectors the levels of radiation requires the development of a custom, radiation tolerant solution. The GigaBit Transceiver (GBT) project is devoted to the design of a radiation tolerant transceiver for the transmission of data, clock, trigger and slow control commands from and to the detector front-end electronics [1]. The GBT will consists of an ASIC-based chipset to be installed close to the detector, and an FPGA-based board with commercial components for the counting room side. Figure 1 shows a simplified view of the GBT architecture. The GBT chipset is based on four ASICs: the GBTx chip, which contains the serializer, deserializer, clock and data recovery and the protocol implementation; the GBTIA and GBLD chips, which are the receiver from the photodiode and the driver for the laser diode, respectively, and the GBTSCA chip which implements the slow control interface. This paper describes the GBLD laser driver. 1

4 Max bit rate Modulation current Bias current Emphasis current Pre-de emphasis Power supply Random jitter Deterministic jitter 2 The GBt Laser Driver (GBLD) Figure 1. GBT schematic. Table 1. GBLD specifications. 5 Gb/s 2 24 ma in 1.6 ma steps 2 48 ma in 1.6 ma steps 0 12 ma in 0.8 ma steps independently programmable single, 2.5 V < 1 ps (rms) < 25 ps (pk-pk) The GBLD is a laser driver targeted at driving both VCSELs and EELs [2] at a maximum data rate of 5 Gb/s. In order to be able to address both laser types, a large modulation and bias current range (up to 24 ma and 48 ma, respectively) is required. Pre- and de-emphasis functions are also required in order to compensate for high external capacitive loads and asymmetrical laser diode response. The chip has to be powered from a single 2.5 V power supply in order to allow enough voltage headroom to the laser diode. Table 1 summarize the GBLD specifications. The modulation, bias and emphasis current, as well as the selection between pre- and deemphasis are externally programmable via an I 2 C slave interface [3] controlled by the GBTx. In order to achieve the required performances without a BiCMOS technology, a deep submicron process (130 nm or less) is required. However, such technologies operates at low power supply (1.5 V or less) and therefore cannot stand the 2.5 V. Special transistors with thicker oxide are usually available for 2.5 V and 3.3 V compatibility, but their speed performances cannot match their thin oxide counterparts. To address this problem, all internal circuits in the GBLD, with the exception of the output stages, uses thin oxide transistor powered at 1.5 V. A simple voltage shifter has been integrated to reduce the supply voltage from 2.5 to 1.5 V for these circuits [4]. 2

5 Figure 2. Modulator schematic. A set of control DACs based on the current steering architecture have been implemented to control the various currents. An integrated bandgap reference is used as a reference voltage for the current generation. 3 Modulator architecture The main component of the GBLD is the high frequency modulator, which is composed by a chain of high speed stages for signal amplification and high current driving capability. To address both EELs and VCSEL, the output stage has been split in two identical drivers with a 12 ma driving capability and 50 Ω output impedance [5]. A single output driver is generally sufficient for VCSEL applications, while for the edge emitting lasers the two drivers have to be connected in parallel. In this second configuration the output impedance is halved, thus allowing a better impedance matching with the EELs, which have a dynamic impedance of the order of 10 Ω or less. The modulator schematic is shown in 2. An input stage with integrated termination resistance is followed by a buffer and delay stage which in turn feeds the predriver stage and the four differential AND gates for the emphasis pulse generation. The predriver drives the two output stages while the AND gates drive the emphasis drivers for the two outputs. Since the emphasis pulse on the rising and on the falling edge of the signal has to be independently programmable, two independent drivers are required for the two signal edges. All stages are designed as differential amplifier with resistive load. The transistor width has been chosen to have a current density between 0.25 and 0.3 ma/µm. It has been shown [6] that such current density leads to the maximum transistor cutoff frequency independently from the 3

6 Figure 3. GBLD output stage. technology node. Passive inductive peaking has been used for the pre-driver to compensate for its large capacitive load from the two output stages. 3.1 Output and emphasis stages The output stage, shown in figure 3, is a cascode differential pair with 50 Ω load resistor. The cascode transistors have been implemented with thick oxide I/O transistors in order to guarantee the compliance with the 2.5 V power supply. Due to the large current variation required for the output stage, a feedback mechanism has been implemented for the tail current generation in order to compensate for the channel length modulation effect. The voltage at the drain of transistor M 3 is compared with that of transistor M 4, and the difference is used to drive the gate of the two transistors. The modulation current set by a control DAC is applied to M 4, and the feedback loop force the same current (after multiplication by the transistor width ratio) on M 3, thus compensating at the first order for the V DS variation. The emphasis pulses are generated by combining in a differential AND gate the signal and its delayed version. Two pulses, one for each signal transition, are generated and fed to separate output drivers to obtain the desired function [7]. The delay width can be digitally controlled by changing the bias current of the delay line. The emphasis output stage is a scaled version of the output stage shown in figure 3. The main difference is that two cascode transistor are present for each differential branch in order to be able to invert the connection to the output lines. In this way it is possible to choose between the preand de-emphasis functions simply by setting the gate voltage of the cascode transistors. 4

7 3.2 Radiation tolerance Figure 4. SEU protection scheme. Deep submicron technology like the 130 nm used for the GBLD shows an intrinsic radiation tolerance exceeding 1 MGy [8]. In principle the thick oxide transistors used in the output stage can be a problem owing to their more pronounced increase of leakage current with irradiation. However, in the output stage, these transistors are in series with thin oxide transistors acting as switches, thus cutting any DC path for leakage current. For correct laser driver operation, it is important that the contents of the configuration registers will not be upset by SEUs. To avoid malfunction, the I 2 C interface should thus use Triple Modular Redundancy (TMR). However, since the I 2 C interface operates with a gated clock (i.e., the clock is only active during the data transfers) TMR alone can not prevent corruption of the registers. In other words, the absence of clock transitions prevents the corrupted registers from loading the correct data provided by the majority voting circuit. During the clock inactivity periods, errors will accumulate on the registers with time resulting in some probability of having two out of the three 5

8 Figure 5. GBLD layout. voted signals in error thus leading to a wrong output of the majority voter. To avoid this problem, the scheme shown in figure 4 is proposed. Its operation is as follows: when no error is present, or during a load cycle, the register behaves as a common triple voted register. However, when a corrupted bit is detected by the error detection circuit, a clock rising edge is generated loading the registers with the output of the majority voters. Once the register content is corrected the clock signal is cleared. The circuit is thus self-timed. The effectiveness of this approach and the overall robustness of the GBLD with respect to the SEU has been reported in [9] 4 The GBLD ASIC The GBLD ASIC has been implemented in a commercial 130 nm CMOS technology featuring 8 metal layers. The chip die is 2 2 mm 2 and can be mounted on a 4 4 mm 2 QFN24 package. Figure 5 shows the chip layout. Single layer planar spiral inductors have been used for the predrivers stage. This type of inductor have the lowest parasitic capacitance but relatively high series resistance due to the turn resistance. However in the predriver circuit topology the inductor is in series with a resistor and therefore its series resistance is not important. The two uppermost metal layers have been fully dedicated to the VDD and GND lines in order to guarantee optimal power distribution. The modulator has been designed using nmos transistors only in order to maximize speed. In the selected process the nmos transistors are realized in the p-substrate while the pmos are 6

9 Figure 6. Eye diagram at 5 Gb/s with I MOD = 2 ma and no pre-emphasis (left) and with I MOD = 12 ma and 26% pre-emphasis (right). realized in dedicated n-well, thus allowing better insulation from substrate noise. However, the technology also allows nmos transistors in dedicated p-well inside the n-well. This option has been used for the modulator switching transistors in order to improve substrate insulation. Moreover, by having source and bulk of those transistors at the same potential, it is possible to reduce their threshold voltage and therefore their size. At high frequencies the bonding wire inductances severely limits the effectiveness of the external decoupling capacitors. Therefore the amount of on chip power supply decoupling capacitance have been maximized. A combination of gate capacitors, metal to metal vertical capacitor and metal-insulator-metal capacitors has been used to filter both the external 2.5 V and the internal 1.5 V power supplies. The total amount of decoupling capacitance is 400 pf for the 2.5 V power supply and 1.06 nf for the 1.5 V supply. In order to reduce the bonding wire inductance, the power supply and high frequency signals bonding pads have been duplicated. Unfortunately, due to an oversight, also the input protection diodes have been duplicated, thus leading to a degradation of the performances due to the increased input capacitance. The problem has been solved with a Focused Ion Beam (FIB) operation to disconnect the extra protection diodes. A simple passive input compensation network has also been proven as effective as the FIB to correct the problem at the expense of a 6 db input signal attenuation. 5 Test results Electrical test have been performed on the GBLD prototype (after the FIB correction) using an high speed PRBS generator and an high bandwidth oscilloscope. Figure 6 (left) shows the eye diagram with a modulation current of 2 ma and no pre-emphasis on a single output driver. A random jitter of 0.68 ps and a deterministic jitter of about 23 ps has been measured in these conditions. At 12 ma the random jitter is almost constant while the deterministic component is about 25 ps. 7

10 Better jitter performances have been obtained when the pre-emphasis function is applied. Figure 6 (right) shows the eye diagram for a modulation current of 12 ma and a pre-emphasis of 3.2 ma (i.e. about 26%). In this case the random and the deterministic jitter decreases to 0.61 ps and 16 ps, respectively. Measurements performed on various modulation and emphasis conditions have shown a random jitter below 1.2 ps and a deterministic jitter below 30 ps in most of the cases. A degradation of the jitter performances (between 15 and 20 ps in the total jitter) has been observed when the chip is encapsulated in the QFN24 package. Simulations have confirmed that this degradation is due to higher temperature of the encapsulated GBLD with respect to the bare die one. 6 Conclusions A radiation tolerant 5 Gb/s laser driver for high energy physics applications has been designed, produced and tested. The driver can be used both for VCSEL and EEL and includes the laser bias current source and pre- and de-emphasis functions. Electrical measurements show that the chip is fully functional and can achieve a random jitter of less than 1.2 ps and a deterministic jitter of less than 30 ps in most of the operating conditions. The chip is powered by a single 2.5 V power supply; the internal core operate at 1.5 V supply provided by an integrated voltage scaler. References [1] P. Moreira et al., The GBT Project, Proceedings of the TWEPP-09 Conference, CERN , pg [2] J. Troska et al., The Versatile Transceiver Proof of Concept, Proceedings of the TWEPP-09 Conference, CERN , pg [3] I 2 C-bus Specification, Version 3.0 (Rev June 2007), available online manual.um10204.pdf. [4] L. Amaral et al., A 5 Gb/s Radiation Tolerant Laser Driver in CMOS 0.13 µm Technology, in Proceedings of the Topical Workshop on Electronics for Particle Physics, Sep 2009, Paris France, CERN [5] S. Galal and B. Razavi, 10-Gb/s Limiting Amplifier and Laser/Modulator Driver in 0.18-µm CMOS Technology, IEEE J. Solid-State Circ. 38 (2003) [6] T.O. Dickson et al., The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks, IEEE J. Solid-State Circ. 41 (2006) [7] P. Westergaard, T.O. Dickson and S.P. Voinigescu, A 1.5V 20/30 Gb/s CMOS Backplane Driver with Digital Pre-emphasis, Proc. IEEE CICC, Orlando, FL, Oct 2004, pp [8] F. Faccio and G. Cervelli, Radiation-Induced Edge Effects in Deep Submicron CMOS Transistors, IEEE Trans. Nucl. Sci. 52 (2005) [9] J. Troska et al., Single-Event Upset testing of the Versatile Transceiver, 2011 JINST 6 C