A 56Gb/s PAM-4 VCSEL driver circuit

Transcription

1 ISSC 2012, NUI Maynooth, June Gb/s PM-4 VCSEL driver circuit N. Quadir*, P. Ossieur* and P. D. Townsend* *Photonic Systems Group, Tyndall National Institute, University College Cork, Ireland bstract We present a driver circuit that can modulate a VCSEL with a 56Gb/s (28Gbaud/s) 4-level pulse-amplitude-modulated (PM-4) signal. High power efficiency is achieved using a common-source driver topology that only draws the modulation current corresponding to the PM-4 symbol being transmitted. Gray encoder based on MOS Current-Mode Logic (MCML) gates is included on chip, as well as programmable PM-4 bias and modulation levels. Keywords VCSEL driver, pulse amplitude modulation, MCML gate. I INTRODUCTION Within the next five years, short-reach optical links (with a distance ranging from a few meters to hundreds of meters) will need to be able to support 100Gb/s/fibre on a single wavelength. pplications include datacenters and supercomputers (Infiniband, Fibre Channel), Local rea Networks (100G Ethernet and beyond) and new consumer links such as Thunderbolt. On top of the high-speed requirements, these links must also comply with stringent power consumption, cost and size limitations, for example allowing integration of highly parallel optical interconnects to further increase capacity. Short-reach optical links for these applications are typically based on a directly modulated, short-wavelength (e.g. 850nm) vertical cavity surface emitting laser (VCSEL) and multimode fibres. Pushing the bitrate on such links beyond today s commercially available 10Gb/s/fibre will require new generations of VCSEL driver and receiver electronics, as well as the use of advanced modulation formats. relatively simple multilevel modulation format beyond the conventional nonreturn to zero (NRZ) is 4-level pulse amplitude modulation (PM-4), providing 2 transmitted bits per symbol. Several PM-4driver circuits have been reported in [1-4]. In [1] the basic cell design consists of a differential pair which steers an always-on tail current to either the positive or negative output rail. This circuit was primarily intended for electrical backplane interconnect, and not very power efficient since the tail currents corresponding to the different PM symbols are always on, irrespective of the currently transmitted PM-symbol. In [2], a highspeed multilevel driver circuit implemented in a deepsubmicron CMOS technology, again primarily intended for electrical backplane interconnects is reported. It saves power by only activating the bias currents for the outer PM-4 symbols at the moment when they are transmitted. However this is not done for the inner PM-4 symbols. The used method to switch on/off the current sources corresponding to the outer PM-4 symbols (extinguishing the current by shorting the source and drain of the current source transistors) is also relatively slow, rendering this circuit impractical for the higher speeds which are needed for future applications. In [3], a differential pair topology is used, which again has the drawbacks in terms of power consumption as explained before. In [4] the driver circuit uses Current-Mode Logic (CML) style differential outputs (it was again intended primarily for electrical backplane interconnect), which means that the modulation currents for the different PM-4 symbols are continuously on and hence no power is saved. In this paper we present a VCSEL driver circuit design using PM-4 format implemented in 65nm CMOS technology which switches on only when the modulation current corresponding to a particular PM-4 symbol is being transmitted thus dramatically increasing power efficiency. II PM-4 MODULTION y transmitting multiple bits using a single symbol, the required bandwidth of the channel for a given bit rate decreases and system spectral efficiency increases. relatively simple multi-level modulation scheme is M-level pulse amplitude modulation, where each pulse conveys log 2 (M) bits of

2 1.2V Gnd 28Gb/s data 28Gb/s data Clock Data information. For a given data rate the effective symbol rate is reduced by log 2 (M) by using PM Fig. 1 PM-4 modulation and Gray encoding of binary input bits. X, Y and Z according to the truth table as shown in Table 1. Each of these bit streams X, Y and Z controls a slice of the driver circuit which can steer a current I to the VCSEL if its logical input is high, and a zero current if its logical input is low. In this way, the driver draws only modulation current for the PM symbol being actually transmitted. The generation of the bias current is spread across all three driver slices, thus ensuring that each driver slice is loaded with the same output impedance. oth the bias current and modulation current I are programmable through on-chip digital registers via the bias and modulation level controllers. n on-chip filtering capacitor is foreseen to provide the anode bias voltage to the VCSEL. The high-speed IO cells were specifically designed for very low capacitance (less than 100fF). P VCSEL PM-4 VCSEL diode VCSEL bias PM-3 PM-2 differential efficiency Driver 1 Driver 2 Driver 3 Level control PM-1 I I I I TH I IS I VCSEL Fig. 2 VCSEL Power vs. current relationship. ias driver (1) ias driver (2) X Y Z inary to Gray& Thermometer encoder ias driver (3) Level control SPI interface modulation compared to conventional binary modulation. Fig. 1 gives a schematic representation of PM-4 modulation. its are assigned to the PM symbols using so-called Gray coding, whereby adjacent PM symbols do not differ in more than a single bit, thus minimizing the bit-error rate at the receiver. Fig. 2 shows the optical output power of a VCSEL versus its bias current: note how a VCSEL only emits optical power when biased above its socalled threshold current. Hence, when modulating a VCSEL with a PM-4 signal, the PM-1 symbol (lowest order symbol) is generated by biasing the VCSEL with a current I IS. This bias current needs to be sufficiently large compared to the VCSEL threshold current (thus minimizing jitter due to turnon delay as well as decreasing the overshoot on the rising typical for laser diodes), but small enough to ensure sufficient modulation contrast. The other PM symbols are generated by driving the VCSEL with an additional current I per PM level. Fig. 3 shows a block diagram of the PM-4 VCSEL driver. The driver accepts two 28Gb/s bit streams and. To generate the corresponding PM-4 symbols, these two bit streams are converted into three Gray and thermometer encoded bitstreams Fig. 3 PM-4 VCSEL driver diagram (SPI = serial peripheral interface). Table 1 inary to Gray/thermometer encoding. PM X Y Z symbol III INRY TO THERMOMETER/GRY ENCODING s conventional CMOS logic does not switch fast enough to accommodate the required 28Gb/s, an MCML (Multi Current Mode Logic) style is used to implement the binary to thermometer/gray encoder. Contrary to static CMOS logic, mostly static power is consumed with little dynamic power. In

3 combination with a smaller voltage swing and its far superior switching speed, this makes MCML an excellent candidate for integration in circuits that require high-speed and are sensitive to power supply disturbances. s shown on Fig. 4, MCML gates are composed of a pull up (passive) network, differential NMOS pairs and a tail transistor that serves as a current source [5]. They are based on current steering wherein the bias current is steered to one of the output branches depending upon the inputs to the NMOS transistors. The branch with no current flowing through it generates a logic high output as the voltage drop across the load resistor is (ideally) zero. The voltage swing is decided by the resistance offered by the load device and the bias current provided through the tail transistor. Fig. 5 MCML inverter/buffer gate Passive pullup network Differential output NOR OR Differential inputs NMOS differential pairs Fig. 4 MCML gates. In order to generate 4-level signals, the binary data (,) has to be converted to thermometer Code (X,Y,Z) as shown in Table 1. From Table 1, we can see that bits X, Y and Z can be implemented as: X= OR, Y=, Z= ND (NOT ) as shown in Fig. 4. To increase the bandwidth, inductive peaking was used in all three logic gates. Fig. 6 MCML OR/NOR gate IV VCSEL DRIVER The VCSEL driver circuit is separated into three different slices (see Fig. 3) in order to reduce the load on each of the driving MCML gates. OR X To VCSEL x1 ND Fig. 5 inary to Thermometer Encoder Y Z X P 1 M 5 M 3 M 4 V DRV M 2 M 1 M Fig. 5 and 6 show an MCML inverter/buffer and OR/NOR gate respectively. The ND/NND gate (Z = ND (NOT ) ) required for the binary to thermometer encoder can be created using the same topology as the OR/NOR gate but with the inputs wired differently. Modulation ( I) control ias (I IS ) control Fig. 7 VCSEL driver slice.

4 Fig. 7 shows the detailed schematic of the VCSEL driver slice. Conventional VCSEL drivers are differential in nature with one output connected to a dummy load (chosen to be equivalent to the VCSEL impedance) and the other output to the VCSEL, however such drivers consume a lot of power as the tail current is always on and merely switched either to the (on-chip) dummy load or to the VCSEL. Here in order to save power we have used a common source stage (transistor M 1 ) with a cascode transistor M 2 driven by source follower M 3. Hence the modulation current is determined by the amount of swing (voltage V DRV ) seen at the input of the common source stage. This voltage swing can be controlled by setting the gate voltage of current source transistor M 4. The source follower is driven by a CMOS inverter stage (M 3 and P 1 ) which converts the output of the MCML gates to a full swing. The split bias currents are added at the drain of the CS transistors using transistor M, thus minimizing the capacitive load at the output. Then all currents (modulation and bias) from the three VCSEL driver slices are summed together and provided to VCSEL diode. The chip layout is shown in Fig. 12: the chip measures 0.98 by 0.76 mm 2. It is currently being fabricated. Devices will be integrated into a suitable module, first experimental results are expected during Q Fig. 9 Time trace the of VCSEL current at 56Gb/s (28Gbaud/s). Fig. 10 Postlayout eye diagram at 56Gb/s (28Gbaud/s). Fig. 8 Eye diagram of the VCSEL current at 56Gb/s (28Gbaud/s). V RESULTS The driver circuit was implemented in a 65nm dual oxide CMOS technology with a 7-layer metal back-end; a 1.2V supply voltage was used for the simulations. Fig. 8 shows the simulated eye diagram at a total throughput of 56Gb/s (28Gbaud/s). The bias current was 10m and the modulation current I was 2m. The VCSEL exhibited 61 differential resistance and an 85fF capacitance (bondpad + junction). Clear open eye opening can be observed with a horizontal eye opening of 27.5ps. Fig. 9 shows a time trace of the PM-4 signal, the different PM levels can be clearly observed. Fig. 10 shows the eye diagram under the same conditions as before with the extracted parasitic elements: some eye closure can be observed due to the layout parasitic. This will be solved in a next version using transmitter-side equalisation having a delayed tap approach to open the eye horizonally and vertically. Fig. 11 shows eye diagram for different amounts of modulation current (4.5m, 6m and 7.5m). Note how the eyes remain clearly open over this range of currents. I = 4.5m 3 I = 6.0m 3 I = 7.5m Fig.11 Eye diagram of VCSEL 56Gb/s for different modulation levels. Table I provides a table comparing our work with previously published M-PM driver circuits. part from the speed, note favourable performance in terms of required energy per transmitted bit (pjoule/bit). Fig. 12 Mask Layout of PM4-VCSEL driver

5 VI CONCLUSION novel topology for a PM-4 VCSEL driver has been presented. The driver circuit only switches the current corresponding to the PM symbol being transmitted thus saving significant power compared to conventional designs. For a bias current of 10m and a peak modulation current of 7.5m, the chip consumes only 32mW. t a throughput of 56Gb/s, this results in 0.56pJ/bit. VII CKNOWLEDGMENT Funding from Science Foundation Ireland (grant 06/IN/I969) and the Microelectronics Competence Centre Ireland (MCCI grant MCCI ) is gratefully acknowledged. VIII REFERENCES [1] H. Cheng and.c. Carusone, 32/16Gb/s 4/2- PM transmitter with PWM pre-emphasis and 1.2Vpp per side output swing in 0.13 m CMOS, Proceedings IEEE Custom Integrated Circuits Conference (CICC 2008), pp , Sept [2] K. Farzan and D.. Johns, CMOS 10-Gb/s power-efficient 4-PM transmitter, IEEE Journal of Solid-State Circuits, vol. 39, March [3] C.H. Lin, 4/2 PM serial link transmitter with tunable pre-emphasis, Proc. International Symp. Circuits and Systems (ISCS 2004), pp , May [4] C. Menolfi, T. Toifl, R. Reutemann, M. Ruegg, P.3 uchmann, M. Kossel, T. Morf and M. Schmatz, 25Gb/s PM4 transmitter in 90nm CMOS SOI, Dig. of Technical Papers ISSCC 2005, pp , Feb [5] M.Mizuno, M. Yamashina, K. Furuta, H. Igura, H. biko, K Okabe,. one H.Yamada, GHz MOS adapative pipeline technique using MOS current-mode logic, IEEE J. Solid-State Circuits, vol. 31, pp , June 1996