Investigation and Modelling of the Floating Body Effects and Surface Recombination on SOS MOSFETs

Transcription

1 Investigation and Modelling of the Floating Body Effects and Surface Recombination on SOS MOSFETs Student: Tom (Chien-Ju) Chu Department of Electrical and Computer Engineering, University of Queensland. Supervisor: Dr. Y. T. Yeow Submitted for the degree of Bachelor of Engineering (Honours) in the division of Electrical Engineering October 2003

2 Tom (Chien-Ju) Chu ADDRESS LINE 1 ADDRESS LINE 2 Tel. (07) xxxx xxxx 19 th October, 2003 The Dean School of Engineering The University of Queensland St Lucia QLD 4072 Dear Professor Simmons, According to the requirements of the degree of Bachelor of Engineering in the division of Electrical Engineering, I hereby submit my thesis entitled Investigation and Modeling Study of the Floating Body Potential in Ultra Thin film of Silicon-on Sapphire MOSFETs. This research work was performed under the supervision of Dr Y. T. Yeow. I declare the thesis submitted is my own work, and those of others work are correctly acknowledged in the bibliography and footnote; and also this thesis has not been submitted previously at the University of Queensland and other institutions. Yours Sincerely, Tom (Chien-Ju) Chu

3 ACKNOWLEDGEMENTS Tom (Chien-Ju) Chu This thesis would not have been possible without the assistance and support of many people. I wish to express my gratefulness to my supervisor, Dr. Y. T. Yeow, for his supervision, guidance and beneficial advices towards this thesis. To research assistant John Khor for his assistance in developing the software programs. Also I would like to thank my friends who gave me the encouragement and motivation to finish this work. I am especially grateful for the love, patience and support of my parents. Department of Electrical Engineering 3

4 ABSTRACT As today s technology advances semiconductor technologies continue to challenge the area of device dimensions and designs. Silicon-on-sapphire (SOS)/ Silicon-on-Insulator (SOI) technologies are developed to provide better performance and scalability for the today s digital applications. It is also designed to operate in environment with high-energy radiation and to reduce the parasitic capacitance comparing to the traditional bulk MOSFETs. This thesis presents the investigation of leakage current caused by surface recombination, and the floating body effects of the SOI/SOS. Investigation of leakage current is by experimental device characterization and analysis of the SOI/SOS devices. The experimental work is based on the gated diode measurements (GDM). Measurements are made on P-channel N-substrate gated diodes devices with a channel length of 50, 0.6, 0.5, 0.4 µm. Experiments involved measurements of I d -V d, I d -V g, C gs -V gs, C gd -V gs characteristics, reverse biased GDM and forward biased GDM. Results gathered demonstrated that at the interfaces of silicon and sapphire is unstable. This unstableness maybe caused by the ionic charges on the surface of the semiconductor, which induces other charges within the semiconductor and therefore causes the formation of the surface channel. Once the surface channel forms, it changes the junction of the depletion region and increases the surface leakage current. It was suggested that by annealing could decrease this leakage problem. Department of Electrical Engineering 4

5 Table of Contents ACKNOWLEDGEMENTS... 3 ABSTRACT... 4 Table of Contents... 5 List of Symbols... 7 List of Figures... 9 Chapter 1 INTRODUCTION Introduction Aim of Thesis Overview of the thesis...11 Chapter 2: INTRODUCTION of BULK & SOS DEVICES Conventional Bulk MOSFET Silicon-on Insulator (SOI)/ Silicon-on-Sapphire (SOS) MOSFET SOI Structures SOI/SOS Fabrication processes SIMOX Technology ZMR technology BESOI Technology Smart-Cut Technology Advantages of SOI/SOS Chapter 3: SOI CHARACTERISTICS Floating-Body Effects Kink Effects Transconductance Bipolar transistor action Operation Modes of SOI devices Accumulation Mode Depletion Mode Inversion Mode Chapter 4: INTRODUCTION TO EXPERIMENT SETUP Hardware Software Chapter 5: RECOMBINATION CURRENT & PROCESS Recombination and Generation processes Surface Recombination Generation-Recombination currents in Gated-Diode Measurement Department of Electrical Engineering 5

6 Chapter 6: Results and Discussions Part I results Results Part I Analysis Part II Results Parts II Results Analysis Chapter 7 Conclusions and future work Conclusions Future works Bibliography Appendix Department of Electrical Engineering 6

7 List of Symbols β bipolar transistor µ 1 pure mobility µ fe1 field-effect mobility C gd C gs c n C ox1 c p C-V d D E i e n e p E t f t g m I B I ch I d I diode I dsat I-V k L L n n b n b* n i N st N t p b p b* r a r b gate to drain capacitance gate to source capacitance capture probability of electrons gate oxide capacitance capture probability of holes capacitance-voltage thickness of a semiconductor slab drain intrinsic Fermi level emission probability of electrons emission probability of holes energy level of recombination centres probability of occupancy of a centre at E t bay an electron transconductance body current channel current drain current diode current drain saturation current current-voltage Boltzman s constant channel length diffusion length electron concentration in the bulk non-equilibrium electron concentration in the bulk intrinsic carrier concentration concentration of recombination centres per unit area at the surface concentration of recombination centres per unit volume in the bulk hole concentration in the bulk non-equilibrium hole concentration in the bulk rate of electron capture rate of electron emission Department of Electrical Engineering 7

8 r c r d S s n s p T τ n τ p U U s V d V ds V dsat V Flatband V g V gs V T V th /V T W rate of hole capture rate of hole emission source surface recombination velocity f electrons in a p-type semiconductor surface recombination velocities of holes in an n-type semiconductor temperature life time of electron in an p-type semiconductor life time of holes in an n-type semiconductor recombination rate in the bulk per unit volume surface recombination rate per unit area drain voltage drain to source voltage drain saturation voltage flatband voltage gate voltage gate to source voltage thermal volatge threshold voltage width of device Department of Electrical Engineering 8

9 List of Figures Figure Basic structure of an N-channel MOSFET Figure Linear Region operation of N-channel MOSFET Figure Saturation Region operation of N-channel MOSFET Figure Beyond Saturation Region operation of N-channel MOSFET Figure Output I-V characteristics of different region operation Figure 2.2 cross section of bulk CMOS and SOI CMOS Figure Structure of SOI NMOSFET Figure SOI devices: partially depleted versus fully depleted Figure Process steps of implant, anneal and epitaxial silicon deposition in SIMOX wafer fabrication Figure cross section of a ZMR process Figure Stacked SOI device structure using seeding lateral epitaxy process Figure Fabrication procedures of BESOI process Figure Formation of voids during the contaminated fabrication Figure Processes of Smart-Cut Technology process Figure Bulk versus SOI devices for illumination of α-particles Figure Capacitances of Bulk and SOI devices Figure I d -V d characteristics of an SOI NMOS device Figure 3.1 VDID characteristics showing breakdown at different gate voltage Figure 3.2 N-channel transistor Figure Microlabs Four-point probe Station Figure HP 4145A Parameter Analyzer Figure HP 4284A precision LCR meter Figure 4.2 HP VEE program Figure 5.1 Generation and recombination through recombination centres Figure 5.3 Gated-Diode structure Figure V g -I diode for device in50* Figure V g -I diode for different device dimensions Figure V g -I diode for different device dimensions Figure Cgd versus Vgs for various level of Vd Figure Cgs versus Vgs for various levels of Vds Department of Electrical Engineering 9

10 Chapter 1 INTRODUCTION Tom (Chien-Ju) Chu Introduction For the past decades fabrication technologies of semiconductor have advanced from Very Large Scale Integrated circuits (VLSI) to Ultra Large Scale Integration circuits (ULSI). In 1970s the semiconductor wafers had 1000 transistors per die with minimum gate dimension of 6µm compared to 10 million transistors per die in today s microprocessors with gate dimension of 0.12µm. The main reason of this fast advancing technology is continuously scaling of devices to sub-micron ranges. However, when the semiconductor devices decrease in sizes, it poses many problems especially it challenges toady s fabrication technologies. Silicon-on-Insulator (SOI) technology was originally proposed in 1963 by Simpson and Manasevit by the epitaxial growth of a silicon film on a single crystal insulator/sapphire. [Simpson & Manasevit 1964]. SOI technology has been regarded as another major technology for VLSI in addition to the bulk silicon technology. Compare to the traditional silicon technology, SOI technology offers more superior devices with higher speed, higher density and reduced parasitic phenomena for sub-micron low-voltage, low-power VLSI circuit applications. However, the disadvantage of the SOI/SOS technology is the floating body effect (FBE). Kink effect, hysteresis, single transistor latch, and bipolar transistor action are some of the problems caused by the FBE. As continuous miniaturization of SOI/SOS devices leakage currents are one of the serious problems influencing the performance of the devices. Leakage currents occur between the silicon and sapphire/insulator interfaces. It is an inevitable problem as it is caused by the heating and cooling during the fabrication processes. The heating and cooling processes creates imperfect match of crystal lattice results in high density of generation and recombination centers. This high density of generation and recombination centers induces increase in surface recombination currents and leakage currents. Department of Electrical Engineering 10

11 1.2 Aim of Thesis Tom (Chien-Ju) Chu The purpose of this thesis is to study the effects of floating body potential on the electrical characteristics of the ultra thin film SOS transistors and to investigate the effects of surface recombination physics and the causes of leakage currents. Investigation is via experimental device characterization of the wafers provided by Peregrine semiconductor. 1.3 Overview of the thesis This thesis is to provide study of the SOI device physics and assess the surface recombination currents. It is also to addresses the characteristics of leakage currents in SOS MOSFETs via gated diode measurement. The following is the brief description of each chapter in this thesis report. Chapter 1: Introduction This chapter introduces the topic of the thesis Investigation of Floating Body Effects and Surface Recombination on SOS MOSFETs. It also presents the aim and overview of the thesis. Chapter 2: Introduction to Bulk and SOS devices This chapter introduces and compares the traditional bulk and SOS MOSFET. The fabrications processes of the SOS devices are also presented, including of SOI structure and its advantages. Chapter 3: SOI characteristics This chapter discusses the details of SOI characteristics: floating body effects, and the cause of these effects. Chapter 4: Introduction to Experimental Setup This chapter gives a brief insight to the hardware and software used for device testing. Department of Electrical Engineering 11

12 Chapter 5: Tom (Chien-Ju) Chu Recombination Currents processes This chapter mainly presents the surface recombination process in gated diode and Gated Diode Measurements theory. As GDM can be used to monitor the generation and recombination currents. Chapter 6: Results and Analysis This chapter presents the results gathered and analysis of the results. The results gathered are the electrical characteristics including I-V, C-V characteristics. Chapter 7: Discussion and Conclusion This chapter presents conclusion of the thesis and suggestions of possible future researches. Department of Electrical Engineering 12

13 Chapter 2: INTRODUCTION of BULK & SOS DEVICES 2.1 Conventional Bulk MOSFET Conventional bulk MOSFET is a two dimensional device consists of a Gate, a Drain and a Source where horizontally from the Source to the Drain and vertically from Gate to Substrate. For a P-type substrate device the Source and Drain are two N-type semiconductors isolated by a P-type substrate. All of the MOSFETs also consist of a heavily doped polysilicon (silicides or polysilicon can be used) gate covering the region between the Source and Drain. A cross sectional view if the N-type MOSFET is shown below. Figure Basic structure of an N-channel MOSFET The basic parameters for a MOSFET is channel length (distance been covered by the gate or distance between the source and the drain), channel width, gate oxide thickness, junction depth and substrate doping. When gate has no voltage the structure of the source to the drain is the same as connecting two p-n junctions. The only currents that will flow through between the source and drain are the reverse leakage currents. When a small gate voltage (V g ) is applied (where gate voltage is greater than threshold voltage (V th ), it will induce an inversion layer between the source and the drain, it is located below the gate oxide. Different drain voltage (V d ) applied will results in different region of operations. There are three main types of regions that MOSFET can operates in, those are Linear, Saturation, and beyond saturation region. Department of Electrical Engineering 13

14 Linear Region Tom (Chien-Ju) Chu Linear region is when V d applied is small, the current flows through the Source to the drain via the conducting channel. Hence, the conducting channel is acting like a resistor. Channel resistance depends on the potential difference of the gate to the inversion layer, where this inversion layer formed by the currents flowing through the source to the drain. Figure Linear Region operation of N-channel MOSFET Saturation Region and Beyond Occurs when the drain voltage increased until it reaches a point where the channel depth reduced to zero. This V d is called saturation voltage (V d sat ). The potential difference between the gate and inversion layer will also decrease until where the inversion layer reaches to zero. As resulted in channel resistance decrease. Figure Saturation Region operation of N-channel MOSFET Department of Electrical Engineering 14

15 Theoretically operation beyond the saturation region the V d will not exceed the V d sat and stayed constant. Results in width of the inversion layer will also be shortened. Figure Beyond Saturation Region operation of N-channel MOSFET Figure Output I-V characteristics of different region operation 2.2 Silicon-on Insulator (SOI)/ Silicon-on-Sapphire (SOS) MOSFET SOI was proposed in 1963 to reduce the parasitic effect in bulk MOSFETs by consisting of an insulator isolating the device from the substrate. Structurally SOI MOSFET is similar to conventional bulk MOSFET, SOI also have the drain, source and gate terminals. For SOI CMOS devices, buried oxide has been used for isolation. For conventional bulk CMOS devices, between the devices and between the device and substrate, depletion regions of reversed biased pn junction have been used for isolation. Therefore device density of the bulk CMOS technology cannot be high. Department of Electrical Engineering 15

16 Below is the comparison of bulk CMOS and SOI CMOS structure. Figure 2.2 cross section of bulk CMOS and SOI CMOS From the figure above, device isolation is much simpler for SOI technology. Consequently SOI technology has a higher device density and easier device isolations. The rapid improvements in VLSI technology, SOI devices have been continuously miniaturized and the circuits have been expanding. In addition, meeting the needs in the portable systems, low-power consumption has become essential. SOI have more advantages compared to the conventional bulk devices, those are reduced channel effects, higher transconductance, increased latch-up immunity (due to the isolation), reduced capacitance between the source and drain, and the scalability of the devices. Resulted from those superior properties SOI technology delivers a better performance, higher speed, higher destiny and reduced parasitic effects phenomena for sub-micron low-voltage, low-power VLSI circuit applications SOI Structures SOI structure is somewhat similar to the conventional bulk MOSFET. It consists of an insulating substrate, oxide layer and the three terminals. There are varieties of insulators which can be used, silicon dioxide is the most common ones, but silicon nitride or sapphire was used in the early years. On top of the insulating layer, a layer of thin film is used to build the active devices. Below is a figure of SOI NMOSFET: Department of Electrical Engineering 16

17 Figure Structure of SOI NMOSFET The buried oxide layer is used to isolate the active region from the substrate. As shown in the figure above, on the bulk silicon, a layer of silicon dioxide is formed. And on top of this buried oxide is where the active MOS devices are located. Owing to the buried oxide layer, the parasitic effect of SOI MOS devices are smaller than the bulk one. This is mainly due to the buried oxide layer is much thicker than the depletion regions. Partially depletion and full depletion SOI devices can be divided into thin-film and thick-film. Below is a cross-section view of a partially depleted versus fully depleted. Figure SOI devices: partially depleted versus fully depleted If the silicon thin-film is thick and only the top parts of the silicon thin film is depleted and the bottom part is neutral. This type is partially depleted SOI Department of Electrical Engineering 17

18 devices. If the silicon thin-film is fully depleted and has no neutral region than this type of the SOI devices is called fully depleted SOI devices. 2.3 SOI/SOS Fabrication processes Initially SOI technology was based on SOS technology. In early 1980s SOS technology was replaced by Separation by Implantation of Oxygen (SIMOX) and Zone Melting and Recrystallization (ZMR) SOI technology. [Lam 1983,Partridge 1986, Colinge 1989, Auberton-Herve 1990] Due to the fast improvement in Bond-and-Etch back SOI (BESOI), SIMOX and ZMR was replaced. As a result, SIMOX and BESOI have become the mainstream technologies for SOI. SIMOX technology is suitable for realizing ultra-thin SOI devices. However the quality of the thin-film was inferior. In contrast, the quality of the thin-film in BESOI technology is better but uniformity control of the thin-film is inferior. Therefore, SIMOX and BESOI technologies have their own strength. [Kawamure 1993]. Recently, smart-cut technology has emerged. In the following sections, each of the major SOI technologies is described in details SIMOX Technology Figure Process steps of implant, anneal and epitaxial silicon deposition in SIMOX wafer fabrication. As shown in the figure, firstly is the oxygen been implanted into certain depth Department of Electrical Engineering 18

19 within the silicon substrate. Where the profile of the implanted oxygen dopants is a Gaussian-shape with the peak some distance below the surface. And then with high temperature anneal, the oxygen dopants reacted with the silicon to form a buried oxide layer around the peak of the oxygen profile. During the annealing process the oxygen dopants moved to gather at the peak region, thus react with the silicon to form silicon dioxide. As a result, a single-crystal silicon thin-film can be formed above the buried oxide layer. If necessary, the thickness of the single-crystal silicon thin-film can be increased by epitaxy. The thickness of the single-crystal silicon thin-film is dependant on the energy of oxygen implant. A higher energy implant will results in a deeper distribution of the oxygen implanted. Therefore, the buried oxide layer is formed at a deeper location from the surface and the thickness of the silicon thin-film becomes greater. In addition, the dose of the oxygen implants also influence the thickness and quality of the buried oxide. If the dose is too low the buried oxide layer will have discontinued precipitation. On the other hand, if the dose is too high will results in silicon islands been formed within the buried oxide layer and in both cases the thin-film on top of the buried oxide layer will generate threading dislocation. However, if a relatively low dose is used than the buried oxide layer is thinner, which improves the self-heating of the device and short-channel effects ZMR technology Figure cross section of a ZMR process The above diagram shows a typical ZMR starting wafer and the process showing Department of Electrical Engineering 19

20 a wafer being scanned across by a wired heater, which sits on a heated lower platen. [Zavracky 1991] A thermal oxide layer is grown on top of the wafer as a buried oxide layer. The thermal oxide at the edge of the wafer is etched off such that silicon is exposed as the seed during crystallization. A layer of the polysilicon is deposited by Low Pressure Chemical Vaporization Deposition (LPCVD). Then another layer of oxide, which is deposited by LPCVD, is used as the capping oxide to isolate the wafer from contamination. In addition, this capping oxide layer can be used to reduce the thickness variation of the single-crystal silicon thin-film after ZMR. At an appropriate distance on top of the wafer graphite stripe heater is used to scan the wafer back and forth. The polysilicon layer under the graphite stripe heater is melted and than is let to cooled down to be crystallized to become single-crystal silicon thin-film. Since the scan of the graphite heater is started from the edge of the wafer, the exposed silicon substrate functions as the seed during the Recrystallization process. In addition to the graphite strip heater, arc lamp and laser and electron beam techniques are also effective heat sources for ZMR process. ZMR is especially suitable for 3D fabrication. Below is a stacked SOI device structure using seeding lateral epitaxy. Figure Stacked SOI device structure using seeding lateral epitaxy process. When the device at the surface is formed, an oxide layer is added, to be used for Department of Electrical Engineering 20

21 planarization. An opening in the oxide layer is used as the seeding area. A polysilicon layer followed by a Si 3 N 4 layer and a tungsten layer is deposited. The purpose of the tungsten layer is used to limit the temperature variations in the wafer such that a stable Recrystallization process is obtained BESOI Technology Figure Fabrication procedures of BESOI process Firstly, a special epitaxial layer is grown on the top of the device wafer, which is used as the etch-stop layer. Another epitaxial layer is grown for the device thin-film region. Then a thermal oxide layer is grown on both the device wafer and the handle wafer. The oxide layer on the handle wafer is used as the buried oxide. The device wafer and the handle wafer are bonded together with the device wafer upside down at a raised temperature. The front surface of the device wafer is now in the center portion of the bonded wafer. The back surface of the device is then grounded, followed by a high selective etch to remove the remaining silicon on the top of the etch-stop layer. Another high selective etch is used to remove the etch-top layer such that only the device thin-film layer is left at the device wafer side. The thickness of the device thin-film layer can be further reduced by thermal oxidation or etch. A hydrogen anneals or Chemical Mechanical Polishing (CMP) is used to improve the surface roughness of the wafer. Department of Electrical Engineering 21

22 However, in the BESOI process, if the fabrication environment is not sufficiently clean during bonding or if the surface of the oxide layer is not even, dust or gas bubbles may exist between the bonded oxide layers. As a result, the bonded wafers cannot sustain the following high-temperature processes and the thickness of the device thin-film region will not be uniform. Below is a figure showing the contamination during the fabrication process: Figure Formation of voids during the contaminated fabrication Smart-Cut Technology Smart-Cut technology is derived from the BESOI technology. Below is a figure showing the process of Smart-Cut technology. Figure Processes of Smart-Cut Technology process The device wafer is grown with a thick thermal oxide layer to be used as the buried oxide in the final SOI structure. [Bruel 1995] A hydrogen ion implantation is carried out. After cleaning the device wafer and the handle Department of Electrical Engineering 22

23 wafer are bonded together at a temperature slightly higher than room temperature. The implanted hydrogen ions at a depth under the oxide layer gather to form blistering. If the amount of the implanted hydrogen atoms is sufficient, this blistering will cause flaking of the whole silicon layer. As a result, a thin-film silicon layer identical to the depth of the hydrogen implant is left at the top of the buried oxide. Due to blistering the wafer surface maybe rough, often CMP is used to smooth the surface. 2.4 Advantages of SOI/SOS There are many reasons for adopting SOI/SOS technologies. Those reasons are mainly based on the different and simpler structure of the device, comparing to conventional bulk devices. As discussed in other chapters SOI/SOS structure is simpler for fabrication, it has reduced parasitic capacitance, better device isolation, and negligible back gate bias effect. SOI/SOS uses thin-film silicon for active devices, this thin-film provided ease of fabrication of isolation trenches and junction formations comparing to fabrication of conventional bulk devices. As a result SOI device is immune to the latch-up and allows simpler control on other effects like short-channel effects. Another advantage provided by the structure of SOI device is the excellent isolation provided by the buried oxide layer as it immunes the SOI devices against high-energy particle illumination. When the device is illuminated by a ray of α-particles, it will generates electron-hole pairs, resulting in excessive amount of current been produced. And because of the active thin-film is totally isolated from the substrate by the buried oxide layer, the induced currents does not influence the performance of the device. This can be seen as below: Department of Electrical Engineering 23

24 Figure Bulk versus SOI devices for illumination of α-particles In addition, provided by the buried oxide layer, SOI devices are immune to the back-gate bias effect. Back gate bias effect occurs in bulk device is when a non-zero source is applied to the body potential, where SOI MOSFET operated in strong inversion. Consequently, there is an increase in threshold voltage and decrease in drive currents. Due to the buried oxide between the silicon thin-film and the substrate, the back gate bias effect in SOI MOS devices is smaller than the bulk one. For partially-depleted SOI devices the back gate bias effect is much smaller than the fully-depleted SOI devices. SOI devices is almost free of back gate bias effect is mainly because SOI device has a floating body and its threshold voltage is almost independent of the back gate bias. The influence of the back gate bias is at minimum; in another word the influence of the back gate bias is shielded. SOI technologies are free of latch-up effect in CMOS devices. In conventional bulk device latch-up effects are caused by the interaction between the npn of the NMOS device and the pnp of PMOS device due to a common substrate. However, in SOI technologies, it can completely isolates the NMOS and PMOS devices and the minority carrier cannot interact with any other neighbouring device. Finally, another important advantage of the SOI technology is the reduction of parasitic capacitance. Below is a cross section view of conventional bulk and SOI device Department of Electrical Engineering 24

25 Figure Capacitances of Bulk and SOI devices From the above figure, conventional bulk device has junction capacitance to the substrate, and another capacitance is to the field implant on the sides of the junction, which is a perimeter capacitance. These capacitances are a significant factor to the conventional bulk devices. On the other figure is the SOI device structure, SOI device only has a junction capacitance. And also because of the dielectric permittivity of silicon dioxide substrate (in bulk devices) is three times more than the dielectric permittivity of the silicon substrate in SOI devices, these contributing factors allow the reduction of capacitance in SOI technology. Department of Electrical Engineering 25

26 Chapter 3: SOI CHARACTERISTICS Tom (Chien-Ju) Chu Floating-Body Effects SOI/SOS devices have many advantages over conventional bulk devices but these technologies have a major parasitic effect, namely the Floating-Body Effects (FBE). It is initiated by the impact ionization within the device. This impact ionization process generates film charges which can not be removed quickly enough as the device has a floating-body or in other words, the substrate is weakly connected to the terminals (not grounded properly). As a result, the FBE generates more problems affecting the device s performance. FBE affected more seriously on the performance of the partially depleted SOI device compared to the fully depleted SOI device because partially depleted SOI device has a neutral region in the bottom portion of the silicon thin-film. The problems generated by the FBE are: Kink effect Negative conductance and transconductance Hysteresis and Latch-up Bipolar transistor action Premature breakdown Kink Effects Kink effect is due to the generation of holes by the impact ionization process in the depletion region near the drain terminal, this generation of holes turns on the parasitic bipolar device, resulting in excess of hole current. However, due to full depletion of the silicon thin film the source-bulk potential barrier is always small in a fully deplete SOI device. [Colinge 1988] Therefore, accumulation of holes can not take place in the body, such that the influence on the device behaviour is small. In partially depleted SOI NMOS devices Department of Electrical Engineering 26

27 (operating in strong inversion), owing to the existence of the neutral region in the bulk, the source-bulk potential barrier is large. Therefore, the generated holes due to impact ionization are easily trapped in the bulk. Consequently, the potential barrier between the source and the bulk decreases. The hole current generated by impact ionization flow from bulk to source and because of the increase in the bulk potential, the threshold voltage depending on the drain bias. [Schlotterer 1975, Suh 1995, Kato 1985] Below is a figure showing I d -V d characteristics. Figure I d -V d characteristics of an SOI NMOS device From the above figure when the gate voltage is small, the Kink effect occurs at a lower drain voltage. Nevertheless, Kink effects also depend on the channel length. This is mainly due to the fact that when channel length becomes smaller, the electric field becomes larger and resulting in impact ionization becomes more serious. In addition, a smaller channel length also allows parasitic BJT perform better. Therefore, the kink effect occurs at a smaller drain voltage. Finally the kink effect is also related to the back gate bias. When the back gate bias becomes more negative, the kink effect is more visible since more holes can be generated at the bottom of the silicon thin-film Transconductance As discussed in previous chapter, back gate bias effect does not have great influence in fully depleted SOI device. But due to the influence of the back Department of Electrical Engineering 27

28 gate bias effect negative transconductance are generated. This negative transconductance have the control over the front-channel threshold voltage and also allows the activation of a back channel inversion. The transconductance can be monitored as: g m C = ox1 WVdµ L fe1 C = ox1 WV L d [ 1 + θ 1(V Where µ 1 is pure mobility and C ox1 is the gate oxide capacitance. Hence, transconductance is directly proportional to the mobility; film thickness will not influence the transconductance. G 1 µ 1 -V T 1 (V G 2 ))] Bipolar transistor action Due to the floating body structure and the parasitic bipolar transistor action effect (BJT), the impact ionization effect of SOI NMOS devices is much more important than that of bulk NMOS devices. [Chen 1997, Burns 1988, Chen 1995] This is due to when SOI device operates in inversion region where high drain voltage is accumulated, caused by the electron-hole pair generation during impact ionization near the junction of the drain terminal. Since SOI device has a floating body, the generated holes will build up the potential charge in the body; as a result the source-to-body junction will be turned on, or in other words when source-to-body junction is turned on there is additional minority carrier been injected from the source(emitter) into the body(base). The gain of a long lateral bipolar transistor can be monitored as: β = 2 Ln 2 L 1 Where L n is diffusion length and L is channel length The collector currents that contributing to the drain current is I b = ( I + β I )( M + 1) ch b ( M + 1) I ch = 1 β ( M 1 ) Department of Electrical Engineering 28

29 Therefore, the total drain current is I d = M ( I ch + β I b I ch M ) = 1 β ( M 1 ) The above equation implies that impact ionization and bipolar action amplifies the drain current and breakdown occurs when 1 β ( M 1 ) = 0 The above equation demonstrated that premature breakdown is caused by the BJT effect. The avalanche multiplication or the feedback mechanism is acting as a self-limiting mechanism for breakdown as when build up of body potential will results in a higher saturation voltage. Below is a figure showing breakdown due to different gate voltage. Figure 3.1 VDID characteristics showing breakdown at different gate voltage. 3.2 Operation Modes of SOI devices The operation modes of SOI MOSFETs are somewhat similar to the conventional bulk silicon devices. There are three basic modes of SOS/SOI MOS devices; those are accumulation, depletion and inversion. Below is the basic structure of SOI MOS device Department of Electrical Engineering 29

30 Drain Gate Metal Contac Source N+ P N+ Insulating sapphire substrate Figure 3.2 N-channel transistor Accumulation Mode Accumulation is caused by the accumulation of majority carrier (holes) near the surface under the gate due to the gate bias such that movements of charges will maintain the charge balance within the transistor. Accumulation depends on V G < V FlatBand Depletion Mode Depletion is due to there is a layer of depletion region under the gate which is consists of depleted carriers such that the injected charge drives away the holes, leaving a depleted region on the surface. Depletion depends on Inversion Mode V < V < V Flatband G T Inversion is due to the continuous expansion of depletion region such that at a certain point that a conducting channel will be formed under the surface of the gate where current flows from the drain to the source. The point where depletion becomes in version depends on V G > V T Department of Electrical Engineering 30

31 Chapter 4: INTRODUCTION TO EXPERIMENT SETUP Device characterization is obtained via the hardware incorporated with software on Gated Diode measurement. Device dimension used are (W/L of the gate): 1. 50/50 um (in50*1.6) 2. 50/0.6 um (in50*2) 3. 50/0.5 um (in50*3) 4. 50/0.4 um (in50*4) 4.1 Hardware Hardware used to obtain the device characteristics are Microlabs Four-point probe Station HP 4145A Parameter Analyzer HP 4284A precision LCR meter Personal Computer Four point probe station is used to magnifying the surface of the wafer such that devices can be selected. The point probe can also be placed as desired, depending on which electrical characteristic is to be measured. The Parameter Analyzer is used to measure the selected device and also setting the boundary conditions of the measurements. The measurements are mainly on I-V characteristics. For C-V characteristics are measured on the HP 4284A precision LCR meter. Below are the figures of the Microlabs Four-point probe Station, HP 4145A Parameter Analyzer and HP 4284A precision LCR meter Department of Electrical Engineering 31

32 Figure Microlabs Four-point probe Station Figure HP 4145A Parameter Analyzer Figure HP 4284A precision LCR meter Department of Electrical Engineering 32

33 4.2 Software Tom (Chien-Ju) Chu HP VEE 5.0 is used to control the instrument and data collection. Below is a figure of HPVEE software (For all the programs that designed to measure the various characteristics can be found in the Appendix.) Figure 4.2 HP VEE program Department of Electrical Engineering 33

34 Chapter 5: RECOMBINATION CURRENT & PROCESS The requirement of this thesis is to perform the investigation of leakage currents and electrical characteristics on SOI devices. Recombination and generation currents are measure via Gated-Diode Measurement (GDM) techniques, based on the SOS gated-diodes 5.1 Recombination and Generation processes Generation process is when an electron is excited form the valence band to the conduction band, leaving behind a hole in the valence band and recombination is the reverse action. Direct transition between the valence and conduction band occurs in all types of silicon material. However, indirect recombination via intermediate states is more likely and it is the major recombination process in materials like silicon and germanium. These localized states existing inside the bandgap are referred by as the recombination centres. There are four possible carrier transitions via recombination centres such as electron capture, electron emission, hole capture and hole emission. These transitions are illustrated in figure below: Figure 5.1 Generation and recombination through recombination centres The Equations in the Shockley-Read-Hall (SRH) recombination quoted, for recombination centres at a single energy level E t and with a concentration of N t per unit volume, the rates of electron capture, electron emission, hole capture and hole emission are given by: Department of Electrical Engineering 34

35 Department of Electrical Engineering 35 ) f 1 ( N n c r t t b n a = t t n b f N e r = ) f ( 1 N e r f N p c r t t p d t t b p c = = Where C n and C p are the capture probability of electron and hole; e n and e p are the emission probability of electron and hole; n b and p b are the electron and hole concentrations; f t is the probability of occupancy of a centre at Et by an electron Under a steady state condition, the occupancy of a recombination centre at E t is given as: ) n e ( n c ) n e p ( c n e c n c f kt / ) E E ( i * b n kt / ) E E ( i * b p kt / ) E E ( i p * b n t i t i t i = And the net recombination rate per unit volume is ) e n ( n c ) e n p ( c n n p c c N r r r r U kt / ) E E ( i * b n kt / ) E E ( i * b p 2 i * b * b n p t d c b a t i t i = = = Where * b p and * b n are the non-equilibrium hole and electron concentration; n i is the intrinsic carrier concentration; E i is the intrinsic fermi level. With the low-level injection of excess carriers, the life time or the recombination time constant of holes in an n-type semiconductor is: t p b * b p N c 1 U p p = = τ

36 And the life time of electron in a p-type semiconductor is: Tom (Chien-Ju) Chu τ n = * nb nb U = 1 c N n t 5.2 Surface Recombination Recombination of the excess carriers via surface state is very similar to the indirect recombination in body. [Many 1971, Grove 1967] Under the steady state condition, the net surface recombination per unit area, corresponding to above equation, is: U s = N st c p c n c p ( p * s + n e i ( E E i t ) / p * s kt n * s n * ) + c ( n n 2 i s + n e i ( E E Where * p s and n * s are the non-equilibrium hole and electron concentrations at the surface; N st is the concentration of the surface states per unit area. Here, C n, C p, e n and e p are the capture and emission probability of electrons and holes. With the low-level injection of excess carriers, the surface recombination velocity of holes corresponding to above equation, in an n-type semiconductor is: i t ) / kt ) U s s p = = * pb pb c p N st And the surface recombination velocity of electrons in a p-type semiconductor is: U s s n = = * nb nb c n N st Surface recombination velocity is an extremely sensitive function of surface treatments. [Grove 1967] The lifetime or recombination time constant of holes at surface can be related to the surface recombination velocity [Grove 1967] by: Department of Electrical Engineering 36

37 τ p = d s p Similarly, the lifetime of electrons by: Where d is the thickness of the semiconductor. τ n = d s n All of the above equations are applicable to recombination centers which are at a single energy level and only accept at most one electron per recombination centre at any given time. This is the most simplest and basic case of recombination process. 5.3 Generation-Recombination currents in Gated-Diode Measurement A key monitor for SOI/SOS technologies and MOS devices is the concentration of defects at the front and back interfaces. Both Charge Pumping and Gated-Diode leakage are successful interface evaluation techniques, already adapted to SOI/SOS. [Cristoloveanu 1993] The reverse bias situation in a diode contributes to the initiation of the generation process. During this process, the electron-hole pairs will be generated and the strong electric fielding the body will separate and swept the electron and the holes out of the depletion region. As a result, this separation mechanism gives rise to a reverse current due to generation of electron-hole pairs. Thus, GDM can be used to investigate and monitor the concentration of recombination-generation centres at the front silicon-silicon dioxide and the back silicon dioxide-silicon-sapphire interfaces. In addition, recombination process occurs when diode is in the forward bias. Below is the figure of GDM used: Department of Electrical Engineering 37

38 Gate Cathode (Source) Metal Contacts Anode (Drain) N+ N- P+ Insulating sapphire substrate Figure 5.3 Gated-Diode structure The gated diode is supplied with a constant small forward biased drain (or anode) (V d ) voltage of 0.3V, and the gate voltage (V g ) is swept from +3Vto -3V. The source contact is connected to ground potential Department of Electrical Engineering 38

39 Chapter 6: Results and Discussions 6.1 Part I results Strong Inversion Depletion Strong Accumulation ID(A) 3.5E E E E E E E E+00 Vgate versus Idiode for different dimension in50*3 CGS(F) CGD(F) VG(V) 5E E-13 4E E-13 3E E-13 2E E-13 1E-13 5E-14 0 Capacitaance(F) Figure V g -I diode for device in50*3 Vg versus Idiode for different dimension 3.5E E E-09 ID(A) 2.0E E E E-10 in50*1.6 in50*2 in50*3 in50*4 0.0E VG(V) Figure V g -I diode for different device dimensions Department of Electrical Engineering 39

40 ID(A) 2.0E E E E E-10 Vg versus Idiode for the same dimension die1 die2 die3 die4 die5 die6 0.0E VG(V) Figure V g -I diode for different device dimensions Results Part I Analysis In figure 6.1, as studied in previous chapter that SOI/SOS device operates in three different modes those are accumulation, depletion and inversion. Accumulation, in this region the currents gathered is proven to be recombination currents due to the recombination process in the depletion region of the P+N- junction. [Streetman 2000] Or in other words, in the accumulation region, the diode operates in the sub-threshold region. Where the diode currents composed of a very small diffusion current (near negligible) and a large recombination-generation current component arising from the recombination-generation mechanism of the silicon-silicon dioxide interfaces traps. Depletion, as the gate varied from the accumulation region to depletion region, the maximum recombination condition will satisfied along the channel from the source edge towards the drain edge. As a result, the diode current demonstrates a sharp peak at a certain critical gate voltage as shown in figure which arises from the contribution of the Department of Electrical Engineering 40

41 generation-recombination processes. Tom (Chien-Ju) Chu As predicted by the SRH equation below, this sharp current peak increases exponentially with the diode gate voltage. Below is the SRH equation: R = τ po 2 ( p i ) n ( n + n' ) + τ no ( p + p' ) Inversion is when the V g becomes more negative the diode currents will suddenly decreases. This is because the front (silicon-silicon dioxide) and the back (silicon-sapphire) interfaces are been inverted; indicating the recombination rate is decreasing resulting in recombination currents decreases at the same time. In figure 6-2 as increase in gate length, the diode currents did not increase dramatically in magnitude. These demonstrate that the generation-recombination process and currents does not depend on the gate length. 6.2 Part II Results 6E-13 Cgd vs Vgs for various level of Vd Cgd (F) 5E-13 4E-13 3E-13 2E-13 1E-13 Vds = 0.3v Vds = 0.5v Vds = 0.7v Vds = 1.0v Vgs (V) Department of Electrical Engineering 41

42 Figure Cgd versus Vgs for various level of Vd 6E-13 Cgs vs Vgs for various level of VD 5E-13 4E-13 Cgs (F) 3E-13 2E-13 1E-13 0 Vds = 0.3v Vds = 0.5v Vds = 0.7v Vds = 1.0v Vgs (V) Figure Cgs versus Vgs for various levels of Vds Parts II Results Analysis Figure and Figure6.2-2 are the high frequency capacitance measurements (as it is measured with frequency of 1MHz). Cgd reaches its maximum value when the front surface reaches strong inversion and reaches its minimum value in the accumulation. In the inverted channel layer or when the channel is inverted it is connected to a region of minority carriers (electron) at the source and drain. The minority carriers can, therefore, respond promptly to the AC gate signal. [] On the other hand, there is no region for the majority carriers (holes) since the SOS/SOI body is isolated. And therefore the majority carriers than have a very long response time determined by the carrier generation-recombination rate. As a result, the high frequency capacitance in the SOS MOSFET initiates from the minority carrier flow, in and out of the inversion channel, and not from the majority carrier response, as in the Department of Electrical Engineering 42

43 case of the conventional MOS capacitor. Tom (Chien-Ju) Chu Department of Electrical Engineering 43

44 Chapter 7 Conclusions and future work Tom (Chien-Ju) Chu Conclusions The gathered results from Gated-Diode Measurements demonstrated the leakage currents could be a flaw to the performance of the SOS MOSFET. This leakage current is mainly contributed by the generation-recombination process which originated at the front (silicon-silicon dioxide) and the back (silicon-sapphire) interfaces. These interfaces contains the ionic charges and recombination centres which induces other charges to create a surface channel and initiate changes in the junction of the device s terminals such that increase in the surface leakage currents is unavoidable. However, it was suggested, device fabricated with other types of material and processes could resolve the surface leakage currents. Due to lack of variation of wafers and devices, a perfect investigation and modeling was not possible. And suggestion of minimizing the surface leakage current is not advisable until more devices are evaluated. 7.2 Future works There are several extensions of future work that could be done. Those are: Continuous investigation of leakage currents via gated diode measurement with several types of devices and different fabrication processed wafers. Investigation of the Floating body effects especially in areas of Hysteresis, premature breakdown, and sub-threshold voltage. Modeling of SOS CMOS devices and bipolar transistor effects Department of Electrical Engineering 44

45 Bibliography 1. Auberton-Herve, A. 1990, SOI Technology Applications: Trends in VLSI, SOI Conf. Dig., pp Bill, V.,. Paul, A., Automated Gated Diode Measurements for Device Characterization, Proc. IEEE Int. Conference on Microelectronic Test Structures, Vol 7, p.141, Bruel, M. 1995, Silicon on Insulator Material Technology, Electronic Letters, vol. 31, no.14, pp Burns, J., Young, K. 1988, Avalanche-Induced Drain-Source Breakdown in Silicon-on-Insulator n-mosfet, IEEE Trans. Elec. Dev., vol.35, no.4, pp Chen, Y., Kuo, J., Yu, Z. & Dutton, R.W. 1995, An analytical Drain current Model for Short-Channel Fully-Depleted Ultrathin Silicon-on-Insulator NMOS devices, Sol. Stat. Elec., vol.38, no.12, pp Colinge, J. 1988, Reduction of Kink effect in thin-film SOI MOSFET s, IEEE Electronic Device Letter, vol.9, no2, pp Colinge, J. 1989, Thin film SOI technology: The solution to many submicron CMOS problems, IEDM Dig., pp Cristoloveanu, S. 1995, Electrical characterization of silicon-on-insulator materials and devices, Kluwer Academic, Boston 9. Grove, A.S. 1967, Physics and Technology of Semiconductor Devices, John Wiley and Sons, New York 10. Kato, K., Wada, T., Taniguchi, K. 1985, Analysis of Kink characteristics in Silicon-on-Insulator MOSFET s using two-carrier Modeling, IEEE Trans. Elec. Dev., vol.32, no.2, pp Kawamura, S. 1993, Ultra-Thin-Film SOI technology and its application to Department of Electrical Engineering 45

46 Next Generation CMOS Devices, SOI Conf. Dig., pp Kuo, J., Chen, S. 1997, An analytical CAD Kink Effect Model of Partially-Depleted SOI NMOS devices operation in Strong Inversion, Sol. Stat. Elec., vol.41, no.3, pp Lam, H.W. 1983, Silicon on Insulating Substrates Recent Advances, IEDM Dig., pp Many, A., Goldstein, Y., Grover, N.B. 1971, Semiconductor surface, North-Holland Publishing Company, London. 15. McGreivy, D.J., On the Origin of Leakage Currents in Silicon-On- Sapphire MOS Transistors., IEEE Transactions on Electron Devices. Vol 24, No. 6, June Moore, G. 2003, No Exponential is Forever but We Can Delay Forever, Available at: Partridge, S. 1986, The current Status of Silicon-on-Insulator Technologies A comparison, IEDM Dig., pp Schlotterer, H., Tihanyi, J. 1975, Properties if ESFI MOS transistors due to the Floating Substate and the Finite volume, IEEE Trans. Elec. Dev., vol.22, no.11, pp Simpson, W. & Manasevit, H. 1964, Journal of Applied Physics, Vol. 35, pp Streetman, B. G. 2000, Solid State Electronic Devices. Prentice-Hall, Inc, Englewood Cliffs New Jersey 21. Suh, D., Fossum, J. 1995, A physical charge-based model for Non-fully depleted SOI MOSFET s and its use in assessing Floating-Body Effects in SOI CMOS Circuits, IEEE Trans. Elec. Dev., vol.42, no.4, pp Sze, 1981, Physics of Semiconductor Devices. Second Edition, John Wiley & Sons, New York, Department of Electrical Engineering 46

47 23. Zaravcky, P., Vu, D. & Batty, M. 1991, Silicon-on Insulator wafers by Zone Melting Recrystallization, Sol. St. Tech., pp Department of Electrical Engineering 47

48 Appendix 1 Program for measuring Vg-Id and Vd-Id Department of Electrical Engineering 48