NLAS6234. Audio DPDT Switch with Noise Suppression

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Audio DPDT Switch with Noise Suppression Description The NLAS6234 is a DPDT switch featuring Popless noise suppression circuitry designed to prevent pass through of undesirable transient signals

1 Audio DPDT Switch with Noise Suppression Description The NLAS6234 is a DPDT switch featuring Popless noise suppression circuitry designed to prevent pass through of undesirable transient signals known as pops. Intended for audio systems within portable applications, it provides protection against audible pops that are generated when switching between two different audio sources, such as an amplifier and a CODEC. The NLAS6234 incorporates two double throw switches controlled by a single select line which allows the system controller to simultaneously switch between two sets of signal lines. The Popless noise suppression circuitry controls the ON and OFF times that define the time interval when switching between the normally open (NO) and normally closed (NC) terminals. This allows any pops to be dissipated within the system before the switch settles into a closed position. The NLAS6234 operates off of a single supply voltage,, and is available in an ultra-thin UQFN1 package. Features Popless Noise Suppression Circuitry OVT up to +4.5 V on Control Pin R ON <.5 Across BCC Range, Typical THD <.2 %, Typical Off Isolation = -7 db, Typical Crosstalk Attenuation < -7 db, Typical Ultra Small, Thin Package: 1.4 mm x 1.8 mm UQFN1 This is a Pb-Free Device MARKING DIAGRAM 1 AR M UQFN1 MU SUFFIX CASE 488AT AR = Specific Device Code M = Date Code = Pb-Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. Typical Applications Cell Phones, PDAs, MP3 and Other Portable Media Players Semiconductor Components Industries, LLC, 27 October, 27 - Rev. 1 1 Publication Order Number: NLAS6234/D

2 NO2 COM2 TEST NO1 1 2 Timing/ Noise Reduction Control 7 6 NC2 GND COM1 S NC1 Figure 1. Pin Connections and Logic Diagram (Top View) NOTE: Pin 8 is for ATE use only, not intended for end customer use. PIN ASSIGNMENT PIN GND S TEST NC1, NO1, NC2, NO2 COM1, COM2 FUNCTION Supply Voltage Ground Control Select Line ATE Test Pin Independent Channels Common Channels TRUTH TABLE S NC1, NC2 NO1, NO2 ON OFF 1 OFF ON MAXIMUM RATINGS Symbol Pins Rating Value Unit Positive DC Supply Voltage -.5 to +5.5 V V IS NOx, NCx, COMx Analog Signal Voltage -.5 to +.5 V V IN S Control Voltage -.5 to +5.5 V I IS_CON NOx, NCx, COMx Analog Signal Continuous Current-Closed Switch 3 ma I IS_PK NOx, NCx, COMx Analog Signal Continuous Current 1% Duty Cycle 5 ma I IN S Control Current 2 ma T s T s Storage Temperature -65 to +15 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. RECOMMENDED OPERATING CONDITIONS Symbol Pins Parameter Min Max Unit Positive DC Supply Voltage 4.5 V V IS NOx, NCx, COMx Analog Signal Voltage GND V V IN S Control Voltage (OVT Protection) GND 4.5 V T A Operating Temperature Range C t r, t f Rise or Fall Time, S = 3. V to 3.6 V 1 ns/v 2

3 DC ELECTRICAL CHARACTERISTICS CONTROL INPUT (Typical: T =, = 3.3 V) -4 C to + Symbol Pins Parameter Test Conditions (V) V IH S Minimum High-Level Voltage, Select Min Typ Max Unit - - V V IL S Maximum Low-Level Voltage, Select V I IN S Control Leakage Current V IS = GND ±1 ±1 na SUPPLY CURRENT AND LEAKAGE (Typical: T =, = 3.3 V, V IN = or GND) Symbol Pins Parameter Test Conditions (V) -4 C to + Min Typ Max I CC Quiescent Supply Current V IS = or GND; I D = A <1 1 na I NC(OFF), I NO(OFF) NCx, NOx OFF State Leakage Current V COM = 4.5 V V NO, V NC = 1. V Unit ±1 ±1 na I OFF Power OFF Leakage Current V IS = GND - ±1 ±1 na ON RESISTANCE (Typical: T =, = 3.3 V) -4 C to + Symbol Pins Parameter Test Conditions (V) R ON On-Resistance V IN = V IL or V IN = V IH V IS = to ; I IS = 1 ma R FLAT On-Resistance Flatness V IS = to ; I IS = 1 ma Min Typ Max Unit R ON On-Resistance Match Between Channels V IS = to ; I IS = 1 ma

4 AC ELECTRICAL CHARACTERISTICS TIMING/FREQUENCY (Typical: T =, = 3.3 V, R L = 5, C L = 35 pf, f = 1 MHz) -4 C to +85 C Symbol Pins Parameter Test Conditions (V) Min Typ Max Unit t ON - Turn-ON Time (Figures 2, 3, ns 12) t OFF - Turn-OFF Time (Figures 2, 3, 13) t BBM - Minimum Break Before Make Time (Figure 14) V IS = 3., = 3.6 V ns ms BW - -3 db Bandwidth V IS = db MHz ISOLATION (Typical: T =, = 3.3 V, R L = 5, C L = 5 pf) -4 C to +85 C Symbol Pins Parameter Test Conditions (V) Min Typ Max Unit O IRR NOx OFF-Isolation V IS = 1. V RMS, db f = 1 khz XTALK COM 1 to COM 2 THD - Total Harmonic Distortion Crosstalk V IS = 1. V RMS, f = 1 khz db R L = 6, 3..2 % V COMn = 2. V p-p CAPACITANCE (Typical: T =, = 3.3 V, R L = 5, C L = 5 pf, f = 1 MHz) Symbol Pins Parameter Test Conditions (V) -4 C to +85 C Min Typ Max C IN S Select Capacitance 2.5 pf C OFF NOx OFF-Capacitance V IS = 3.3 V, S = V pf C ON COMx to NCx ON-Capacitance S = V pf Unit 4

5 DUT V 5% 5%.1 F Open 5 V OUT 35 pf V OH 9% 9% V OL t ON t OFF Figure 2. t ON / t OFF, V is = DUT 5 V 5% 5% V OUT V OH Open 35 pf V OL 1% 1% t OFF t ON Figure 3. t ON / t OFF, V is = GND 5 Reference DUT Transmitted 5 Generator 5 Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth of an On switch. V ISO, Bandwidth and V ONL are independent of the input signal direction. VISO Off Channel Isolation 2 Log V OUT VIN for V IN at 1 khz VONL On Channel Loss 2 Log V OUT VIN for V IN at 1 khz to 5 MHz Bandwidth (BW) = the frequency 3 db below V ONL V CT = Use V ISO setup and test to all other switch analog input/outputs terminated with 5 Figure 4. Off-Channel Isolation/On Channel Loss (BW)/Crosstalk (On Channel to Off Channel)/V ONL 5

6 MAGNITUDE (db) FREQUENCY (MHz) Figure 5. Crosstalk vs. 25 C MAGNITUDE (db) FREQUENCY (MHz) Figure 6. Bandwidth vs. = 3 V THD (%) R ON ( ) C FREQUENCY (khz) V IN (V) Figure 7. Total Harmonic = 3. V Figure 8. On-Resistance vs. = 3. V R ON ( ).2-4 C R ON ( ) V V V IN (V) V IN (V) Figure 9. On-Resistance vs. = 4.3 V Figure 1. On-Resistance vs. 25 C 6

7 25 E-9 12 I CC (A) 2 E-9 15 E-9 1 E-9 T ON (ns) E-9 E+ -5 E C C V IN (V) (V) Figure 11. I CC vs Figure 12. t ON vs T OFF (ns) C (V) Figure 13. t OFF vs 7

8 Popless Implementation on the NLAS6234 Audio sources such as amplifiers or CODECs can generate undesirable, transient voltage spikes when powering up and down. Those voltage spikes can be translated into current surges and ultimately lead to audible pop noises in the speaker if not diverted or suppressed. The NLAS6234 includes popless noise suppression circuitry designed to prevent such undesirable pops from propagating through to the speaker. This feature is realized through a deliberate increase in the Break-Before-Make time, t BBM, and is useful in applications where a switch is used to alternate between two different audio sources. When the signal from the common pin is removed from one terminal, the switch waits an extended amount of time before connecting to the opposite terminal. The time interval for t BBM is a function of the supply voltage of the switch,. Figure 14 shows the relationship of t BBM for each value within the recommended operating voltage range T BBM (ms) (V) Figure 14. NLAS6234 T BBM vs. DEVICE ORDERING INFORMATION NLAS6234MUTBG Device Package Shipping UQFN1 (Pb-Free) 3/Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD811/D. 8

9 PACKAGE DIMENSIONS UQFN1, 1.4x1.8,.4P CASE 488AT-1 ISSUE A PIN 1 REFERENCE 2X 2X 1X.1 C.1 C.5 C.5 C 9 X L L3 D ÉÉ 1 TOP VIEW A1 SIDE VIEW 6 BOTTOM VIEW A A 1 X b e E B e/2 C SEATING PLANE.1 C A B.5 C L1 EXPOSED Cu A1 NOTE 3 DETAIL A Bottom View (Optional) ÉÉÉ ÉÉÉ DETAIL B Side View (Optional) EDGE OF PACKAGE MOLD CMPD.2.79 A NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN.25 AND.3 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN MAX A.45.6 A1..5 A3.127 REF b D 1.4 BSC E e 1.8 BSC.4 BSC L L L3.4.6 MOUNTING FOOTPRINT X PITCH 1 X SCALE 2:1 mm inches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 8217 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative NLAS6234/D

NLAS7213. High-Speed USB 2.0 (480 Mbps) DPST Switch

NLAS7213. High-Speed USB 2.0 (480 Mbps) DPST Switch High-Speed USB 2.0 (480 Mbps) DPST Switch The NLAS723 is a DPST switch optimized for high speed USB 2.0 applications within portable systems. It features ultra low off capacitance, C OFF = 3.0 pf (typ),