High Speed, Logic Isolator AD261

Transcription

1 a FATURS Isolation Test Voltage: To. kv rms Five Isolated Logic Lines: Available in Six I/O Configurations Logic Signal Bandwidth: 0 MHz (min) CMV Transient Immunity: 10 kv/ s min Waveform dge Transmission Symmetry: 1 ns Field and System Output nable/three-state Functions Performance Rated Over C to + C UL190, IC90, N6090 Certification (V, C, Pending) APPLICATIONS PLC/CS Analog Input and Output Cards Communications Bus Isolation General ata Acquisition Applications IGBT Motor rive Controls High Speed igital I/O Ports High Speed, Logic Isolator A61 FUNCTIONAL BLOCK IAGRAM LIN 0 LIN 1 LIN LIN LIN NABL FL 1 6 NABL SYS GNRAL SCRIPTION The A61 is designed to isolate five digital control signals to/from a microcontroller and its related field I/O components. Six models allow all I/O combinations from five input lines to five output lines, including combinations in between. very A61 effectively replaces up to five opto-isolators. ach line of the A61 has a bandwidth of 0 MHz (min) with a propagation delay of only 1 ns, which allows for extremely fast data transmission. Output waveform symmetry is maintained to within ±1 ns of the input so the A61 can be used to accurately isolate time-based PWM signals. All field or system output pins of the A61 can be set to a high resistance three-state level by use of the two enable pins. A field output three-stated offers a convenient method of presetting logic levels at power-up by use of pull-up/down resistors. System side outputs being three-stated allows for easy multiplexing of multiple A61s. The isolation barrier of the A61 B Grade is 100% tested as high as. kv rms (system to field). The barrier design also provides excellent common-mode transient immunity from 10 kv/µs common-mode voltage excursions of field side terminals relative to the system side, with no false output triggering on either side. ach output is updated within nanoseconds by input logic transitions, the A61 also has a continuous output update feature that automatically updates each output based on the dc level of the input. This guarantees the output is always valid 10 µs after a fault condition or after the power-up reset interval. FL 16 V RTN FL 1 Vdc RTN FIL SYSTM TYPICAL MOL (A61-) Vdc RTN SYS V RTN SYS PROUCT HIGHLIGHTS Six Isolated Logic Line I/O Configurations Available: The A61 is available in six pin-compatible versions of I/O configurations to meet a wide variety of requirements. Wide Bandwidth with Minimal dge rror: The A61 affords extremely fast isolation of logic signals due to its 0 MHz bandwidth and 1 ns propagation delay. It maintains a waveform input-to-output edge transition error of typically less than ±1 ns (total) for positive vs. negative transition.. kv rms Test Voltage Isolation Rating: The A61 B Grade is rated to operate at 1. kv rms and is 100% production tested at. kv rms, using a standard AI test method. High Transient Immunity: The A61 rejects commonmode transients slewing at up to 10 kv/µs without false triggering or damage to the device. (Continued on page ) RV. 0 Information furnished by Analog evices is believed to be accurate and reliable. However, no responsibility is assumed by Analog evices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog evices. One Technology Way, P.O. Box 9106, Norwood, MA , U.S.A. Tel: 1/9-00 World Wide Web Site: Fax: 1/6-0 Analog evices, Inc., 199

2 A61 SPCIFICATIONS (Typical at T A = + C, + V dc SYS, + V dc FL, t RR = 0 ns max unless otherwise noted) Parameter Conditions Min Typ Max Units INPUT CHARACTRISTICS Threshold Voltage Positive Transition (V T+ ) + V dc SYS =. V.0..1 V + V dc SYS =. V.0.. V Negative Transition (V T ) + V dc SYS =. V V + V dc SYS =. V V Hysteresis Voltage (V H ) + V dc SYS =. V V + V dc SYS =. V V Input Capacitance (C IN ) pf Input Bias Current (I IN ) Per Input 0. µa OUTPUT CHARACTRISTICS Output Voltage 1 High Level (V OH ) + V dc SYS =. V, I O = 0.0 ma. V + V dc SYS =. V, I O = ma. V Low Level (V OL ) + V dc SYS =. V, I O = 0.0 ma 0.1 V + V dc SYS =. V, I O = ma 0. V Output Three-State Leakage Current NABL Logic Low/High Level Respectively 0. µa YNAMIC RSPONS 1 (Refer to Figure ) Max Logic Signal Frequency (f MIN ) 0% uty Cycle, + V dc SYS = V 0 MHz Waveform dge Symmetry rror (t RROR ) t PHL vs. t PLH ±1 ns Logic dge Propagation elay (t PHL, t PLH ) 1 ns Minimum Pulsewidth (t PWMIN ) ns Max Output Update elay on Fault or After Power-Up Reset Interval ( 0 µs) 1 µs ISOLATION BARRIR RATING Operating Isolation Voltage (V CMV ) A61A V rms A61B 10 V rms Isolation Rating Test Voltage (V CMV TST ) A61A 10 V rms A61B 00 V rms Transient Immunity (V TRANSINT ) 10,000 V/µs Isolation Mode Capacitance (C ISO ) Total Capacitance, All Lines 9 1 pf Capacitive Leakage Current (I LA ) 0 V 60 Hz µa rms POWR SUPPLY Supply Voltage (+ V dc SYS and + V dc FL ) Rated Performance.. V dc Operating.0. V dc Power issipation Capacitance ffective, per Input, ither Side pf ffective per Output, ither Side No Load pf Quiescent Supply Current ach, + V dc SYS & FL ma Supply Current All 10 MHz (Sum of + V dc SYS & FL ) 1 ma TMPRATUR RANG Rated Performance (T A ) + C Storage (T STG ) 0 + C NOTS 1 For best performance, bypass + V dc supplies to com., at or near the device (0.01 µf). + V dc supplies are also internally bypassed with 0.0 µf. As the supply voltage is applied to either side of the A61, the internal circuitry will go into a power-up reset mode (all lines disabled) for about 0 µs after the point where + V dc SYS & FL passes above. V. Operating isolation voltage is derived from the Isolation Test Voltage in accordance with such methods as found in V-0 wherein a device will be hi-pot tested at twice the operating voltage, plus one thousand volts. Partial discharge testing, with an acceptance threshold of 0 pc of discharge may be considered the same as a hi-pot test (but nondestructive). Partial ischarge at 0 pc THL. Supply Current will increase slightly, but otherwise the unit will function within specification to 0 C. Specifications are subject to change without notice. RV. 0

3 ABSOLUT MAXIMUM RATINGS* A61 Parameter Conditions Min Typ Max Units Supply Voltage (+ V dc SYS & FL ) V C Input Voltage (V IN MAX ) Referred to + V dc SYS & FL and V RTN SYS & FL Respectively V C Output Voltage (V OUT MAX ) Referred to + V RTN SYS & FL and V dc SYS & FL Respectively V Clamp iode Input Current (I IK ) For V I < 0. V or V I > V RTN SYS & FL +0. V + ma Clamp iode Output Current (I OK ) For V O < 0. V or V O > V RTN SYS & FL +0. V + ma Output C Current, per Pin (I OUT ) + ma C Current, V CC or GN (I CC or I GN ) 0 +0 ma Storage Temperature (T STG ) 0 + C Lead Temperature (Soldering, 10 sec) +00 C lectrostatic Protection (V S ) Per MIL-ST-, Method 01. kv *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. xposure to absolute maximum ratings for extended periods may effect device reliability. I/O CONFIGURATIONS AVAILABL The A61 is available in several configurations. The choice of model is determined by the desired number of input vs. output lines. All models have identical footprints with the power and enable pins always being in the same locations. PIN FUNCTION SCRIPTIONS Pin Mnemonic Function 1 * Through igital Xmt or Rcv from Through 6 NABL SYS System Output nable/three-state + V dc SYS System Power Supply (+ V dc Input) V RTN SYS System Power Supply Common 9 1 Not Present On Unit 1 V RTN FL Field Power Supply Common 16 + V dc FL Field Power Supply (+ V Input) 1 NABL FL Field Output nable/three-state 1 * Through igital Xmt or Rcv from Through *Function of pin determined by model. Refer to Table I. V RTN FL FL NABL FL PIN CONFIGURATION SYSTM FIL 1 6 BOTTOM VIW NABL SYS SYS V RTN SYS ORRING GUI Model Isolation Package Package Number escription Ratings escription Option A61AN-0 0 Inputs, Outputs 1. kv rms Plastic IP N-A A61AN-1 1 Input, Outputs 1. kv rms Plastic IP N-A A61AN- Inputs, Outputs 1. kv rms Plastic IP N-A A61AN- Inputs, Outputs 1. kv rms Plastic IP N-A A61AN- Inputs, 1 Output 1. kv rms Plastic IP N-A A61AN- Inputs, 0 Outputs 1. kv rms Plastic IP N-A A61BN-0 0 Inputs, Outputs. kv rms Plastic IP N-A A61BN-1 1 Input, Outputs. kv rms Plastic IP N-A A61BN- Inputs, Outputs. kv rms Plastic IP N-A A61BN- Inputs, Outputs. kv rms Plastic IP N-A A61BN- Inputs, 1 Output. kv rms Plastic IP N-A A61BN- Inputs, 0 Outputs. kv rms Plastic IP N-A CAUTION S (electrostatic discharge) sensitive device. lectrostatic charges as high as 000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the A61 features proprietary S protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper S precautions are recommended to avoid performance degradation or loss of functionality. RV. 0 WARNING! S SNSITIV VIC

4 A61 A61 CONFIGURATIONS A61-0 A61- LIN 0 LIN 0 LIN 1 LIN 1 LIN LIN LIN LIN LIN LIN NABL FL 1 6 NABL SYS NABL FL 1 6 NABL SYS FL 16 SYS FL 16 SYS V RTN FL 1 V RTN SYS V RTN FL 1 V RTN SYS FIL SYSTM FIL SYSTM A61-1 A61- LIN 0 LIN 0 LIN 1 LIN 1 LIN LIN LIN LIN LIN LIN NABL FL 1 6 NABL SYS NABL FL 1 6 NABL SYS FL 16 SYS FL 16 SYS V RTN FL 1 V RTN SYS V RTN FL 1 V RTN SYS FIL SYSTM FIL SYSTM RV. 0

5 A61 A61 CONFIGURATIONS A61- A61- LIN 0 LIN 0 LIN 1 LIN 1 LIN LIN LIN LIN LIN LIN NABL FL 1 6 NABL SYS NABL FL 1 6 NABL SYS FL 16 SYS FL 16 SYS V RTN FL 1 V RTN SYS V RTN FL 1 V RTN SYS FIL SYSTM FIL SYSTM (Continued from page 1) Field and System nable Functions: Both the isolated and nonisolated sides of the A61 have NABL pins that threestate all outputs. Upon reenabling these pins, all outputs are updated to reflect the current input logic level. C Certifiable: Simply by adding the external bypass capacitors at the supply pins, the A61 can attain C certification in most applications (to the MC directive) and conformance to the low voltage (safety) directive is assured by the N6090 certification. Table I. Model Number and Pinout Function Pin A61-0 A61-1 A61- A61- A61- A61-1 (Xmt) (Xmt) (Xmt) (Xmt) (Xmt) (Rcv) (Xmt) (Xmt) (Xmt) (Xmt) (Rcv) (Rcv) (Xmt) (Xmt) (Xmt) (Rcv) (Rcv) (Rcv) (Xmt) (Xmt) (Rcv) (Rcv) (Rcv) (Rcv) (Xmt) (Rcv) (Rcv) (Rcv) (Rcv) (Rcv) 6 NABL SYS * * * * * + V dc SYS * * * * * V RTN SYS * * * * * 9 1 Not Present 1 V RTN FL * * * * 16 + V dc FL * * * * * 1 NABL FL * * * * * 1 (Rcv) (Rcv) (Rcv) (Rcv) (Rcv) (Xmt) 19 (Rcv) (Rcv) (Rcv) (Rcv) (Xmt) (Xmt) 0 (Rcv) (Rcv) (Rcv) (Xmt) (Xmt) (Xmt) 1 (Rcv) (Rcv) (Xmt) (Xmt) (Xmt) (Xmt) (Rcv) (Xmt) (Xmt) (Xmt) (Xmt) (Xmt) *Pin function is the same on all models, as shown in the A61-0 column. GNRAL ATTRIBUTS The A61 provides five HCMOS compatible isolated logic lines with 10 kv/µs common-mode transient immunity. The case design and pin arrangement provides greater than 1 mm spacing between field and system side conductors, providing CSA/IS and IC creepage spacing consistent with 0 V mains isolation. The five unidirectional logic lines have six possible combinations of ins and outs, or transmitter/receiver pairs; hence there are six A61 part configurations (see Table I). ach 0 MHz logic line has a Schmidt trigger input and a threestate output (on the other side of the isolation barrier) and 1 ns of propagation delay. A single enable pin on either side of the barrier causes all outputs on that side to go three-state and all inputs (driven pins) to ignore their inputs and retain their last known state. Note: All unused logic inputs (1 ) should be tied either high or low, but not left floating. dge fidelity, or the difference in propagation time for rising and falling edges, is typically less than ±1 ns. Power consumption, unlike opto-isolators, is a function of operating frequency. ach logic line barrier driver requires about 160 µa per MHz and each receiver 0 µa per MHz plus, of course, ma total idle current (each side). The supply current diminishes slightly with increasing temperature (about 0.0%/ C). The total capacitance spanning the isolation barrier is less than 10 pf. The minimum period of a pulse that can be accurately coupled across the barrier is about ns. Therefore the maximum square-wave frequency of operation is 0 MHz. RV. 0

6 A61 Logic information is sent across the barrier as set-hi/set-lo data that is derived from logic level transitions of the input. At power-up or after a fault condition, an output might not represent the state of the respective channel input to the isolator. An internal circuit operates in the background which interrogates all inputs about every µs and in the absence of logic transitions, sends appropriate set-hi or set-lo data across the barrier. Recovery time from a fault condition or at power-up is thus between µs and 10 µs. ATA IN NABL SCHMITT TRIGGR BUFFR Q G GAT TRANSPARNT RIVR.kV ISOLATION BARRIR ATA RCIVR CONTINUOUS UPAT CIRCUIT Figure 1. Simplified Block iagram OUTPUT BUFFR OUT NABL C1 10/9 INPUT POSITIV GOING INPUT THRSHOL NGATIV GOING INPUT THRSHOL HYSTRSIS OUTPUT 6% % t ff PROPAGATION LAY t P = 1ns FFCTIV CIRCUIT MOL pf INPUT CAPACITANC BUFFR LAY LIN 1ns BUFFR t rr = t ff = 100 x C TOTAL OUTPUT CAPACITANC 0.ns NO LOA =.ns INTO 0pF 100 TOTAL LAY = t P t rr = 1ns (NO LOA), 1ns (0pF LOA) pf OUTPUT CAPACITANC Figure. Typical Timing and elay Models OUTLIN IMNSIONS imensions shown in inches and (mm). -Pin Plastic IP (N-A) 1.00 (.1) MAX 0.0 (1.9) MAX (.06) 0.10 (.6) 0.00 (1.) 0.0 (1.91) PIN 1 SI VIW (0.0 0.) 16 PLACS 0.0 (11.1) MAX (.) N VIW 0.0 (.9) PRINT IN U.S.A. 0.0 (6.) SYSTM BOTTOM VIW 0.* (1.) FIL 0.60 (16.1) *CRPAG PATH (SUBTRACT APPROXIMATLY 0.09 (mm) FOR SOLR PA RAII ON PC BOAR. THIS SPACING SUPPORTS TH INTRINSICALLY SAF RATING OF 0V (1.) 6 RV. 0