Internally Trimmed Integrated Circuit Multiplier AD532

Transcription

1 a Internally Trimmed Integrated Circuit Multiplier AD53 FEATURES PIN CONFIGURATIONS Pretrimmed to.0% (AD53K) Y No External Components Required Y V Guaranteed.0% max 4-Quadrant Error (AD53K) OS 4 +V S OUT 3 Y Diff Inputs for (X ) ( Y )/ Transfer Function +V 3 Monolithic Construction, Low Cost S GND VS Y AD53 AD53 4 TOP VIEW TOP VIEW V OS APPLICATIONS (Not to Scale) X (Not to Scale) 5 0 GND Multiplication, Division, Squaring, Square Rooting 6 9 Algebraic Computation OUT X 7 8 Power Measurements V Instrumentation Applications S = NO CONNECT Available in Chip Form OUT +V S V S AD53 TOP VIEW (Not to Scale) PRODUCT DESCRIPTION The AD53 is the first pretrimmed single chip monolithic multiplier/divider. 8 4 GND It guarantees a maximum multiplying error of ±.0% and a ± output voltage without the need for any external trimming resistors or output op amp. Because the = NO CONNECT AD53 is internally trimmed, its simplicity of use provides design engineers with an attractive alternative to modular multipliers, GUARANTEED PERFORMAE OVER TEMPERATURE and its monolithic construction provides significant advantages The AD53J and AD53K are specified for maximum multiplying in size, reliability and economy. Further, the AD53 can be used errors of ± % and ± % of full scale, respectively at 5 C, and as a direct replacement for other IC multipliers that require are rated for operation from 0 C to 70 C. The AD53S has a external trim networks. maximum multiplying error of ± % of full scale at 5 C; it is also 00% tested to guarantee a maximum error of ± 4% at the FLEXIBILITY OF OPERATION extended operating temperature limits of 55 C and +5 C. All The AD53 multiplies in four quadrants with a transfer func- devices are available in either the hermetically-sealed TO-00 tion of ( )( Y )/, divides in two quadrants with metal can, TO-6 ceramic DIP or LCC packages. J, K, and a /( ) transfer function, and square roots in one S grade chips are also available. quadrant with a transfer function of ±. In addition to these basic functions, the differential X and Y inputs provide ADVANTAGES OF ON-THE-CHIP TRIMMING OF THE significant operating flexibility both for algebraic computation and MONOLITHIC AD53 transducer instrumentation applications. Transfer functions,. True ratiometric trim for improved power supply rejection. such as XY/, ( Y )/, ± /, and /( ), are easily attained and are extremely useful in many modulation. Reduced power requirements since no networks across sup- and function generation applications, as well as in trigonometric plies are required. calculations for airborne navigation and guidance applications, 3. More reliable since standard monolithic assembly techniques where the monolithic construction and small size of the AD53 can be used rather than more complex hybrid approaches. offer considerable system advantages. In addition, the high 4. High impedance X and Y inputs with negligible circuit loading. CMRR (75 db) of the differential inputs makes the AD53 especially well qualified for instrumentation applications, as it 5. Differential X and Y inputs for noise rejection and additional can provide an output signal that is the product of two transducer- computational flexibility. generated input signals. 8 Y 7 6 V OS 5 REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 906, Norwood, MA , U.S.A. which may result from its use. No license is granted by implication or Tel: 78/ World Wide Web Site: otherwise under any patent or patent rights of Analog Devices. Fax: 78/ Analog Devices, Inc., 00

2 AD53 SPECIFICATIONS 5 C, V S = 5 V, R k V OS grounded, unless otherwise noted.) AD53J AD53K AD53S Model Min Typ Max Min Typ Max Min Typ Max Unit MULTIPLIER PERFORMAE Transfer Function ( )( Y ) ( )( Y ) ( )( Y ) Total Error ( X, Y +) ±.5.0 ± ± % T A = Min to Max ±.5 ± % Total Error vs. Temperature ± 0.04 ± 0.03 ± %/ C Supply Rejection (± 5 V ± 0%) ± 0.05 ± 0.05 ± 0.05 %/% Nonlinearity, X (X = 0 V p-p, Y = ) ± 0.8 ± 0.5 ± 0.5 % Nonlinearity, Y (Y = 0 V p-p, X = ) ± 0.3 ± 0. ± 0. % Feedthrough, X (Y Nulled, X = 0 V p-p 50 Hz) mv Feedthrough, Y (X Nulled, Y = 0 V p-p 50 Hz) mv Feedthrough vs. Temperature mv p-p/ C Feedthrough vs. Power Supply ± 0.5 ± 0.5 ± 0.5 mv/% DYNAMICS Small Signal BW (V OUT = 0. rms) MHz % Amplitude Error khz Slew Rate (V OUT 0 p-p) V/µs Settling Time (to %, V OUT = 0 V) µs NOISE Wideband Noise f = 5 Hz to 0 khz mv (rms) f = 5 Hz to 5 MHz mv (rms) OUTPUT Output Voltage Swing ± 0 ± 3 ± 0 ± 3 ± 0 ± 3 V Output Impedance (f khz) Ω Output Offset Voltage ± mv Output Offset Voltage vs. Temperature mv/ C Output Offset Voltage vs. Supply ±.5 ±.5 ±.5 mv/% INPUT AMPLIFIERS (X, Y, and ) Signal Voltage Range (Diff. or CM Operating Diff) ± 0 ± 0 ± CMRR db Input Bias Current X, Y Inputs µa X, Y Inputs T MIN to T MA0 8 8 µa Input ± 0 ± 5 5 ± 5 5 µa Input T MIN to T MAX ± 30 ± 5 ± 5 µa Offset Current ± 0.3 ± 0. ± 0. µa Differential Resistance MΩ DIVIDER PERFORMAE Transfer Function (X l > ) /( ) /( ) /( ) Total Error (V X =, V +) ± ± ± (V X = V, V +) ± 4 ± 3 ± 3 SQUARE PERFORMAE ( ) ( ) ( ) Transfer Function Total Error ± 0.8 ± 0.4 ± 0.4 % SQUARE ROOTER PERFORMAE Transfer Function Total Error (0 V V ) ±.5 ±.0 ±.0 % POWER SUPPLY SPECIFICATIONS Supply Voltage Rated Performance ± 5 ± 5 ± 5 V Operating ± 0 8 ± 0 8 ± 0 ± V Supply Current Quiescent ma PACKAGE OPTIONS TO-6 (D-4) AD53JD AD53KD AD53SD TO-00 (H-0A) AD53JH AD53KH AD53SH LCC (E-0A) AD53SE/883B % % Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. THERMAL CHARACTERISTICS H-0A: θ JC = 5 C/W; θ JA = 50 C/W E-0A: θ JC = C/W; θ JA = 85 C/W D-4: θ JC = C/W; θ JA = 85 C/W REV. C

3 AD53 ORDERING GUIDE Temperature Package Package Model Ranges Descriptions Options AD53JD 0 C to 70 C Side Brazed DIP D-4 AD53JD/+ 0 C to 70 C Side Brazed DIP D-4 AD53KD 0 C to 70 C Side Brazed DIP D-4 AD53KD/+ 0 C to 70 C Side Brazed DIP D-4 AD53JH 0 C to 70 C Header H-0A AD53KH 0 C to 70 C Header H-0A AD53JCHIPS 0 C to 70 C Chip AD53SD 55 C to +5 C Side Brazed DIP D-4 AD53SD/883B 55 C to +5 C Side Brazed DIP D-4 JM3850/3903BCA 55 C to +5 C Side Brazed DIP D-4 AD53SE/883B 55 C to +5 C LCC E-0A AD53SH 55 C to +5 C Header H-0A AD53SH/883B 55 C to +5 C Header H-0A JM3850/3903BIA 55 C to +5 C Header H-0A AD53SCHIPS 55 C to +5 C Chip CHIP DIMENSIONS AND BONDING DIAGRAM Contact factory for latest dimensions. Dimensions shown in inches and (mm) (.575) 0.07 (.78) V S GND V OS Y OUTPUT V S FUTIONAL DESCRIPTION The functional block diagram for the AD53 is shown in Figure, and the complete schematic in Figure. In the multiplying and squaring modes, is connected to the output to close the feedback around the output op amp. (In the divide mode, it is used as an input terminal.) The X and Y inputs are fed to high impedance differential amplifiers featuring low distortion and good common-mode rejection. The amplifier voltage offsets are actively laser trimmed to zero during production. The product of the two inputs is resolved in the multiplier cell using Gilbert s linearized transconductance technique. The cell is laser trimmed to obtain V OUT = ( )( Y )/0 volts. The built-in op amp is used to obtain low output impedance and make possible self-contained operation. The residual output voltage offset can be zeroed at V OS in critical applications... otherwise the V OS pin should be grounded. V X R R X OUTPUT V Y Y 0R V OS R V OUT = ( ) ( Y ) 0V (WITH TIED TO OUTPUT) Figure. Functional Block Diagram V S R Q Q R6 R8 R6 Q7 Q8 Q4 Q5 R3 Q6 Q7 C Q R7 R33 COM R34 R9 R Q3 Q4 R3 Q5 Q6 R0 Q9 Q R3 Q0 Q R0 R R Q8 Q Q3 Q6 Q5 R30 R3 R8 R9 V OS OUTPUT R3 R R9 Q0 Q4 Q7 Y R8 R4 R5 Q8 R R4 R5 Q3 Q9 R4 R5 R6 V S CAN Figure. Schematic Diagram REV. C 3

4 AD53 AD53 PERFORMAE CHARACTERISTICS Multiplication accuracy is defined in terms of total error at 5 C with the rated power supply. The value specified is in percent of full scale and includes X IN and Y IN nonlinearities, feedback and scale factor error. To this must be added such application-dependent error terms as power supply rejection, common-mode rejection and temperature coefficients (although worst case error over temperature is specified for the AD53S). Total expected error is the rms sum of the individual components since they are uncorrelated. Accuracy in the divide mode is only a little more complex. To achieve division, the multiplier cell must be connected in the feedback of the output op amp as shown in Figure 3. In this configuration, the multiplier cell varies the closed loop gain of the op amp in an inverse relationship to the denominator voltage. Thus, as the denominator is reduced, output offset, bandwidth and other multiplier cell errors are adversely affected. The divide error and drift are then m / ) where m represents multiplier full-scale error and drift, and ( ) is the absolute value of the denominator. NONLINEARITY Nonlinearity is easily measured in percent harmonic distortion. The curves of Figures 3 and 4 characterize output distortion as a function of input signal level and frequency respectively, with one input held at plus or minus dc. In Figure 4 the sine wave amplitude is 0 V (p-p). PERCENT DISTORTION X IN YIN PEAK SIGNAL AMPLITUDE Volts Figure 3. Percent Distortion vs. Input Signal AC FEEDTHROUGH AC feedthrough is a measure of the multiplier s zero suppression. With one input at zero, the multiplier output should be zero regardless of the signal applied to the other input. Feedthrough as a function of frequency for the AD53 is shown in Figure 5. It is measured for the condition V X = 0, V Y = 0 V (p-p) and V Y = 0, V X = 0 V (p-p) over the given frequency range. It consists primarily of the second harmonic and is measured in millivolts peak-to-peak. CMRR db FEEDTHROUGH mv Y FEEDTHROUGH X FEEDTHROUGH 00 k 0k 00k M 0M Figure 5. Feedthrough vs. Frequency COMMON-MODE REJECTION The AD53 features differential X and Y inputs to enhance its flexibility as a computational multiplier/divider. Common-mode rejection for both inputs as a function of frequency is shown in Figure 6. It is measured with = = 0 V (p-p), ( Y ) = dc and = Y = 0 V (p-p), ( ) = dc X COMMON-MODE REJ ( Y ) 0V Y COMMON-MODE REJ ( ) 0V 00 0 PERCENT DISTORTION 0.0 0V p-p SIGNAL X IN 0 00 k 0k 00k M 0M Figure 6. CMRR vs. Frequency Y IN k 0k 00k M Figure 4. Percent Distortion vs. Frequency 4 REV. C

5 AMPLITUDE Volts.0 0. R L k C L 0pF R L k C L 000pF AD53 POWER SUPPLY CONSIDERATIONS Although the AD53 is tested and specified with ± 5 V dc supplies, it may be operated at any supply voltage from ± to ± 8 V for the J and K versions, and ± to ± V for the S version. The input and output signals must be reduced proportionately to prevent saturation; however, with supply voltages below ± 5 V, as shown in Figure 9. Since power supply sensitivity is not dependent on external null networks as in other conventionally nulled multipliers, the power supply rejection ratios are improved from 3 to 40 times in the AD k 00k M 0M Figure 7. Frequency Response, Multiplying DYNAMIC CHARACTERISTICS The closed loop frequency response of the AD53 in the multiplier mode typically exhibits a 3 db bandwidth of MHz and rolls off at 6 db/octave thereafter. Response through all inputs is essentially the same as shown in Figure 7. In the divide mode, the closed loop frequency response is a function of the absolute value of the denominator voltage as shown in Figure 8. Stable operation is maintained with capacitive loads to 000 pf in all modes, except the square root for which 50 pf is a safe upper limit. Higher capacitive loads can be driven if a 00 Ω resistor is connected in series with the output for isolation. 0 PEAK SIGNAL VOLTAGE Volts SATURATED OUTPUT SWING MAX X OR Y INPUT FOR % LINEARITY POWER SUPPLY VOLTAGE Volts Figure 9. Signal Swing vs. Supply NOISE CHARACTERISTICS All AD53s are screened on a sampling basis to assure that output noise will have no appreciable effect on accuracy. Typical spot noise vs. frequency is shown in Figure 0. AMPLITUDE Volts V X V V 0. V X SIN T.0 4 V X 0V V X 5V 0. 0k 00k M 0M Hz SPOT NOISE V/ 5 3 Figure 8. Frequency Response, Dividing k 0k 00k Figure 0. Spot Noise vs. Frequency REV. C 5

6 AD53 APPLICATIONS CONSIDERATIONS The performance and ease of use of the AD53 is achieved through the laser trimming of thin-film resistors deposited directly on the monolithic chip. This trimming-on-the-chip technique provides a number of significant advantages in terms of cost, reliability and flexibility over conventional in-package trimming of off-the-chip resistors mounted or deposited on a hybrid substrate. First and foremost, trimming on the chip eliminates the need for a hybrid substrate and the additional bonding wires that are required between the resistors and the multiplier chip. By trimming more appropriate resistors on the AD53 chip itself, the second input terminals that were once committed to external trimming networks have been freed to allow fully differential operation at both the X and Y inputs. Further, the requirement for an input attenuator to adjust the gain at the Y input has been eliminated, letting the user take full advantage of the high input impedance properties of the input differential amplifiers. Thus, the AD53 offers greater flexibility for both algebraic computation and transducer instrumentation applications. Finally, provision for fine trimming the output voltage offset has been included. This connection is optional, however, as the AD53 has been factory-trimmed for total performance as described in the listed specifications. REPLACING OTHER IC MULTIPLIERS Existing designs using IC multipliers that require external trimming networks can be simplified using the pin-for-pin replaceability of the AD53 by merely grounding the, Y and V OS terminals. (The V OS terminal should always be grounded when unused.) APPLICATIONS MULTIPLICATION Y (OPTIONAL) AD53 V OS 0k OUT V OUT V OUT = ( ) ( Y ) 0V Figure. Multiplier Connection For operation as a multiplier, the AD53 should be connected as shown in Figure. The inputs can be fed differentially to the X and Y inputs, or single-ended by simply grounding the unused input. Connect the inputs according to the desired polarity in the output. The terminal is tied to the output to close the feedback loop around the op amp (see Figure ). The offset adjust V OS is optional and is adjusted when both inputs are zero volts to obtain zero out, or to buck out other system offsets. SQUARE V IN AD53 OUT V OUT Y +V V OS V V S S V OUT = IN 0V (OPTIONAL) 0k Figure. Squarer Connection The squaring circuit in Figure is a simple variation of the multiplier. The differential input capability of the AD53, however, can be used to obtain a positive or negative output response to the input... a useful feature for control applications, as it might eliminate the need for an additional inverter somewhere else. DIVISION.k V OUT = 0V X X AD53 OUT V OUT Y k (SF) 47k 0k 0k (X 0 ) Figure 3. Divider Connection The AD53 can be configured as a two-quadrant divider by connecting the multiplier cell in the feedback loop of the op amp and using the terminal as a signal input, as shown in Figure 3. It should be noted, however, that the output error is given approximately by m /( ), where m is the total error specification for the multiply mode; and bandwidth by f m ( )/, where f m is the bandwidth of the multiplier. Further, to avoid positive feedback, the X input is restricted to negative values. Thus for single-ended negative inputs (0 V to ), connect the input to X and the offset null to ; for single-ended positive inputs (0 V to +), connect the input to and the offset null to. For optimum performance, gain (S.F.) and offset (X 0 ) adjustments are recommended as shown and explained in Table I. For practical reasons, the useful range in denominator input is approximately 500 mv ( ). The voltage offset adjust (V OS ), if used, is trimmed with at zero and ( ) at full scale. Table I. Adjust Procedure (Divider or Square Rooter) DIVIDER SQUARE ROOTER Adjust Adjust With: for: With: for: Adjust X V OUT VOUT Scale Factor + + X 0 (Offset) V +0. V V +0. V V Repeat if required. 6 REV. C

7 AD53 SQUARE ROOT.k V OUT = 0V AD53 OUT V OUT Y k (SF) 47k 0k 0k (X 0 ) Figure 4. Square Rooter Connection The connections for square root mode are shown in Figure 4. Similar to the divide mode, the multiplier cell is connected in the feedback of the op amp by connecting the output back to both the X and Y inputs. The diode D is connected as shown to prevent latch-up as IN approaches 0 volts. In this case, the V OS adjustment is made with IN = +0. V dc, adjusting V OS to obtain.0 V dc in the output, V OUT =. For optimum performance, gain (S.F.) and offset (X 0 ) adjustments are recommended as shown and explained in Table I. DIFFEREE OF SQUARES X Y 0k 0k AD53 OUT V OUT Y 0k Y +V S V OS V S V OUT = Y Y 0V (OPTIONAL) 0k AD74KH Figure 5. Differential of Squares Connection The differential input capability of the AD53 allows for the algebraic solution of several interesting functions, such as the difference of squares, Y /. As shown in Figure 5, the AD53 is configured in the square mode, with a simple unity gain inverter connected between one of the signal inputs (Y) and one of the inverting input terminals ( Y IN ) of the multiplier. The inverter should use precision (0.%) resistors or be otherwise trimmed for unity gain for best accuracy. REV. C 7

8 AD53 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Side-Brazed DIP (D-4) (9.40) (8.5) (0.3) MIN (.49) MAX (7.87) 0.0 (5.59) 7 PIN (9.94) MAX (.5) 0.05 (0.38) 0.00 (5.08) MAX (5.08) (3.8) 0.5 (3.8) MAX 0.03 (0.58) (.78) SEATING 0.04 (0.36) (.54) (0.76) PLANE BSC (9.09) 0.34 (8.69) SQ (8.5) (7.75) TOP VIEW 0.85 (4.70) 0.65 (4.9) (.0) MAX (.4) 0.00 (0.5) Leadless Chip Carrier (E-0A) 0.00 (.54) (.63) (9.09) MAX SQ (.4) (.90) 0.0 (0.8) (0.8) R TYP (.9) REF 0.30 (8.3) 0.90 (7.37) 0.05 (0.38) (0.0) 0.00 (5.08) BSC (.9) REF 0.00 (.54) BSC BOTTOM VIEW (.4) (.40) 0.50 (3.8) (.37) (.4) BSC Metal Can (H-0A) REFEREE PLANE (9.05) (.70) 0.50 (6.35) MIN (.7) MAX 0.09 (0.48) 0.30 (5.84) 0.06 (0.4) BSC 0.0 (0.53) 0.06 (0.4) BASE & SEATING PLANE 0.60 (4.06) 0.0 (.79) (.9) BSC (0.38) MIN 0.08 (0.7) 0.0 (0.56) (.7) BSC 45 TYP (.4) 0.07 (0.69) (0.86) 0.07 (0.69) 36 BSC PRINTED IN U.S.A. C0050h 0 /0 (rev. C) 8 REV. C