Bidirectional Level Shifter

Size: px

Start display at page:

Download "Bidirectional Level Shifter"

Theresa Morgan
6 years ago
Views:

1 pplication Note C349 idirectional Level Shifter Table of Contents Introduction Design Example Overview Description of the Design Example Conclusion ppendix Design Files Introduction Semiconductor technology advancements, proliferating I/O standards, legacy support requirements, and the relentless drive to design and manufacture lower power systems require most applications to utilize a mix of power supply and I/O drive voltages. Today's lower power devices have to work in this ecosystem with the older, higher voltage devices, requiring solutions that interface with the multiple voltages that are in widespread use today. Level-translator integrated circuits (ICs) are a common solution, but they do not necessarily provide the flexibility to support multiple simultaneous translations to different voltages or I/O interface standards. Level-translator ICs can add unnecessary cost if the system already contains an FP on board. ll ILOO and ProSIC 3 low power FPs support multiple voltage options for I/O banks. The input/output supply voltage (VCCI) of each bank determines the voltage level of it is I/Os. The ILOO series of FPs supports 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V mixed-voltage operations, including several flexible wide range I/O voltage options. In addition to these features, flash-based ILOO FPs also offer other unique features, such as high reliability, being a single-chip solution, live at power-up, nonvolatile, and available in small footprint packages. These features make ILOO devices more suitable for level-translator applications than SRM-based CPLDs/FPs. ILOO and ProSIC3 low power FPs can also be used as unidirectional or bidirectional level shifters. Examples are 3.3 V to 2.5 V or 2.5 V to 3.3 V level translations. Refer to the Level Shifter Design Example application note for more details on the unidirectional level shifter. The level translator used in a bidirectional digital circuit such as the I 2 C bus must also be bidirectional with no requirement for a direction control signal. This application note describes the design of a bidirectional level shifter on an ILOO FP with no direction control signal, although the design can be easily adapted to work with any of the Fusion, ProSIC3, or SmartFusion devices. This bidirectional level shifter design example provides a low cost, low power, highly flexible solution that utilizes ILOO low power FPs. September Microsemi Corporation

2 idirectional Level Shifter Design Example Overview This design example demonstrates the bidirectional level shifter with no direction control signal using the ILOO nano Starter Kit. Figure 1 shows the system-level interface signals used in this design example. idirectional PD is connected to SIC with 3.3 V signaling; bidirectional PD is connected to SIC with 1.2 V signaling. 3.3 V 1.2 V ILOO PD PD SIC SIC Figure 1 System Level Interface Signals Description of the Design Example Figure 2 shows the bidirectional level shifter circuit diagram, which consists of an active high latch with active high preset and clear, bidirectional buffer, 2-input OR gate, inverter, and 2-input ND gate. ll these components are available for ILOO, ProSIC3, SmartFusion, and Fusion devices. Refer to the ILOO, ProSIC3, SmartFusion and Fusion Macro Library uide for more details. 3.3 V 1.2 V Latch Latch PD Q D D Q PD Y D D Y SIC SIC Figure 2 idirectional Level Shifter Circuit Diagram 2

3 Description of the Design Example Operation of the idirectional Level Shifter The following states are considered for explaining the operation of the bidirectional level shifter (Table 1). Table 1 idirectional PD States Sl No. PD States Latch State PD State 1 Hi-Z 0 Hi-Z 0 2 Hi-Z -> (drives) 0 Hi-Z -> > 1 (drives) 0 0 -> 1 -> Hi-Z (External pull-up that pulls the PD High) 4 Hi-Z -> 0 1 Hi -> Z -> 0 (drives) > 1 -> Hi-Z (external pull-up that pulls the PD High) Latch State 1 -> 0 1 -> 1 0 -> 1 (drives) 0 Initially both PDs are in tristate (Hi-Z). The ND gate output clears Latch and Latch via the OR gates, which in turn tristates PD and PD. This state is continued until any of the PDs are driven externally by a 0 input. When any of the PDs are driven externally from Hi-Z to 0, the latch on the other side is RESET, enabling bidirectional pad. Hence 0 is transferred to the other output. When any of the PDs are driven externally from 0 to 1, then 1 is transferred on the other pad. This starts charging the load driven by the other pad. When the output voltage level reaches above threshold, the ND gate output goes High. This clears Latch and Latch, leaving the output in Hi-Z state. oth Verilog and VHDL design files are provided (refer to "ppendix Design Files" on page 4) with this design example. ILOO FPs support several drive strengths and slew rates. You can choose these parameters while running Designer in Libero IDE, based on the characteristics of the chips that need to be driven. Figure 3 shows the bidirectional level shifter output waveform for the 1.2 V to 3.3 V translation at 400 KHz clock frequency. The green waveform indicates the input clock frequency with 1.2 V signaling and the yellow waveform indicates the output with 3.3 V signaling. The delay between input and output is measured as 8 ns under typical conditions. Figure 3 Voltage Translation from 1.2 V to 3.3 V 3

idirectional Level Shifter If the external circuit has high capacitance and must be charged by a Strong One, the UFD macro can be used to delay the Hi-Z state on the output, as shown in Figure 4. 3.

4 idirectional Level Shifter If the external circuit has high capacitance and must be charged by a Strong One, the UFD macro can be used to delay the Hi-Z state on the output, as shown in Figure V 1.2 V Latch Latch PD Q D D Q PD Y D D Y SIC SIC UFD UFD UFD UFD Figure 4 idirectional Level Shifter with Input Path Delay Figure 5 shows the bidirectional level shifter output waveform for the 1.2 V to 3.3 V translation at 400 KHz clock frequency with two UFD delay macros. Figure 5 Voltage Translation from 1.2 V to 3.3 V with Two UFD Delay Macros Conclusion This application note discussed the need for level shifters and the use of ILOO and ProSIC3 low power FPs for multiple simultaneous translations to different voltages or I/O interface standards. The design example demonstrated a bidirectional level shifter with no control signal on an ILOO FP, although the design can be easily adapted to work with any of the Fusion, ProSIC3, and SmartFusion devices. ppendix Design Files The design files are available for download at 4

5 Microsemi Corporation (NSDQ: MSCC) offers the industry s most comprehensive portfolio of semiconductor technology. Committed to solving the most critical system challenges, Microsemi s products include high-performance, high-reliability analog and RF devices, mixed signal integrated circuits, FPs and customizable SoCs, and complete subsystems. Microsemi serves leading system manufacturers around the world in the defense, security, aerospace, enterprise, commercial, and industrial markets. Learn more at Microsemmi Corporate Headquarters 2381 Morse venue, Irvine, C Phone: Fax: Microsemi Corporation. ll rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. ll other trademarks and service marks are the property of their respective owners /9.10

DC-22GHz, 16dB Gain Low-Noise Wideband Distributed Amplifier

DC-22GHz, 16dB Gain Low-Noise Wideband Distributed Amplifier Features Excellent combination of wide bandwidth, low noise and high associated gain 1.7dB NF with >15.5dB gain at 10GHz Output IP3 ~26-29dBm