Rad-Tolerant Current Mode PWM Controller

Transcription

1 SGR1844 / SGR1845 Rad-Tolerant Current Mode PWM Controller Description The SGR1844/SGR1845 is fit, form and function compatible to the SG1844/SG1845 with the addition of guaranteed performance after radiation exposure to Total Ionizing Dose (TID), Enhanced Low Dose Rate Sensitivity (ELDRS), and Single Event Latch-up (SEL) conditions. The family of control ICs provides all the required features to implement off-line Fixed Frequency, Current-mode switching power supplies with a minimum number of external components. Current-mode architecture demonstrates improved line regulation, improved load regulation, pulse-by pulse current limiting and inherent protection of the power supply output switch. The bandgap reference is trimmed to ±1% over temperature. Oscillator discharge current is trimmed to less than ±10%. The has undervoltage lockout, current-limiting circuitry and start-up current of less than 1mA. The totem-pole output is optimized to drive the gate of a power MOSFET. The output is low in the off state to provide direct interface to an N- channel device. Both operate up to a maximum duty cycle range of zero to <50% due to an internal toggle flip-flop which blanks the output off every other clock cycle. The is specified for operation over the full military ambient temperature range of -55 C to 125 C. Product Highlight Features Optimized for Off-Line Control Low Start-Up Current (<1mA) Automatic Feed Forward Compensation Trimmed Oscillator Discharge Current Pulse-By-Pulse Current Limiting Enhanced Load Response Characteristics Undervoltage Lockout with 6V Hysteresis (SGR1844 only) Double Pulse Suppression High-Current Totem-Pole Output Internally Trimmed Bandgap Reference 500kHz Operation Undervoltage Lockout SGR Volts SGR Volts Low Shoot-through Current <75mA Over Temperature High Reliability Features - SGR1844/SGR1845 Rad-tolerance: (Test data available) TID to a Minimum of 100krad(Si) w/ 150krads overtest and 168 hours anneal ELDRS to a Minimum of 50krad(Si) SEL Immunity to a Minimum of 87MeV-cm 2 /mg R ST AC INPUT V cc I ST SGR1844 Figure 1 Product Highlight March 2014 Rev Microsemi Corporation- Analog Mixed Signal Group

2 Current Mode PWM Controller Connection Diagrams and Ordering Information Ambient Temperature Type Package Part Number Packaging Type Connection Diagram SGR1844Y COM V REF Y 8-PIN CERAMIC DUAL INLINE PACKAGE SGR1844Y-EV* SGR1845Y SGR1845Y-EV* CERDIP V FB I SENSE R T /C T Y PACKAGE (Top View) PbSn Tin Lead Finish V CC OUTPUT GND SGR1844J COM N.C. V REF N.C. J 14-PIN CERAMIC DUAL INLINE PACKAGE SGR1844J-EV* SGR1845J CERDIP V FB N.C. I SENSE N.C. R T/C T V CC V C OUTPUT GND PGND SGR1845J-EV* J PACKAGE (Top View) PbSn Lead Finish -55 C to 125 C L 20-Pin CERAMIC LCC SGR1844L SGR1844L-EV* SGR1845L SGR1845L-EV* Ceramic (LCC) Leadless Chip Carrier N.C. 2. N.C. 3. COM. 4. N.C. 5. VFB 6. N.C. 7. ISENSE 8. RT/CT 9. N.C. 10. N.C. L PACKAGE (Top View) PbSn Lead Finish 11. N.C GND 14. N.C. 15. OUT UT 16. N.C. 17. Vc 18. Vcc 19. N.C. 20. VREF SGR1844F F 10-PIN CERAMIC FLAT PACK PACKAGE SGR1844F-EV* SGR1845F FLAT PACK COM V FB I SENSE R T/C T PGND F PACKAGE (Top View) PbSn Lead Finish V REF V CC V C OUTPUT GND SGR1845F-EV* * EV is Microsemi s Equivalent V flow that follows MIL-PRF requirements for Class V processing. 2

3 Absolute Maximum Ratings1-2 Absolute Maximum Ratings 1-2 Parameter Value Units Supply Voltage (Low Impedance Source) 30 V Output Current (Peak) ±1 A Output Current (Continuous) 350 ma Output Energy (Capacitive Load) 5 µj Analog Inputs (V FB, I SENSE) -0.3 to +6.3 V Error Amplifier Output Sink Current 10 ma Operating Junction Temperature Hermetic (Y, J, L, F Packages) 150 C Storage Temperature Range -65 to +150 C Lead Temperature (Soldering, 10 Seconds) 300 C RoHS / Pb-free Peak Package Solder Reflow Temp. (40 second max. exposure) Notes: 1. Exceeding these ratings could cause damage to the device. 2. All voltages are with respect to Pin 5. All currents are positive into the specified terminal. 260 (+0, -5) C Thermal Data Parameter Value Units Y Package: Thermal Resistance-Junction to Ambient, θ JA 130 C/W J Package Thermal Resistance-Junction to Ambient, θ JA 80 C/W F Package Thermal Resistance-Junction to Case, θ JC 80 C/W Thermal Resistance-Junction to Ambient, θ JA 145 C/W L Package Thermal Resistance-Junction to Case, θ JC 35 C/W Thermal Resistance-Junction to Ambient, θ JA 120 C/W Notes: Junction Temperature Calculation: T J = T A + (P D x θ JA ). The θ JA numbers are guidelines for the thermal performance of the device/pc-board system. All of the above assume no ambient airflow. 3

4 Current Mode PWM Controller Recommended Operating Conditions 3 Symbol Parameter Recommended Operating Conditions Min. Typ. Max. V S Supply Voltage Range 30 V I PK Output Current (Peak) ±1 A I OUT Output Current (Continuous) 200 ma Analog Inputs (Pin 2, Pin 3) V EA ISNK Error Amp Output Sink Current 5 ma OSC FR Oscillator Frequency Range khz R T Oscillator Timing Resistor kω C T Oscillator Timing Capacitor µf Operating Ambient Temperature Range: C Note: 3. Range over which the device is functional. Units Electrical Characteristics Unless otherwise specified, these specifications apply over the operating ambient temperatures for SGR1844/SGR1845 with -55 C T A 125 C. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature. Symbol Parameter Test Condition Reference Section Min Typ Max V REF Output Voltage T J = 25 C, I O = 1mA V V REG Line Regulation 12V V IN 25V 6 20 I REG Load Regulation 1mA I O 20mA 6 25 Units Temperature Stability mv/ C Total Output Variation 4 Line, Load, Temperature V V N Output Noise Voltage 4 10Hz f 10kHz, T J = 25 C 50 µv Long Term Stability 4 T A = 125 C,1000hrs 5 25 mv V ISC Output Short Circuit ma Oscillator Section 6 f Initial Accuracy T J = 25 C khz mv f REG Voltage Stability 12V V CC 25V.02 1 Temperature Stability 4 T MIN T A T MAX 5 % OSC PP Amplitude V RT/CT (Peak to Peak) 1.7 V I DSG Discharge Current T J = 25 C T MIN T A T MAX ma 4

5 Electrical Characteristics Symbol Parameter Test Condition Error Amp Section Min Typ Max EA IH Input Voltage V COMP = 2.5V V EA IIB Input Bias Current µa A VOL Open Loop Gain 2V V O 4V db EA BW Unity Gain Bandwidth 4 T J = 25 C MHz PSRR Power Supply Rejection Ratio 12V V CC 25V db EA SNK Output Sink Current V VFB = 2.7V, V COMP = 1.1V 2 6 EA SRC Output Source Current V VFB = 2.3V, V COMP = 5V EA VOH V OUT High V VFB = 2.3V, R L = 15k to GND 5 6 EA VOL V OUT Low V VFB = 2.7V, R L = 15k to VREF Current Sense Section CS AVOL Gain V/V PSRR Maximum Input Signal 5 V COMP = 5V V Power Supply Rejection Ratio 5 12V V CC 25V 70 db CS IIB Input Bias Current µa CS DELAY Delay to Output ns Output Section VOL VOH Output Low Level I SINK = 20mA I SINK = 200mA Output High Level I SOURCE = 200mA I SOURCE = 200mA RS Rise Time 4 T J = 25 C, C L = 1nF ns FT Fall Time 4 T J = 25 C, C L = 1nF ns Under-Voltage Lockout Section UVLO V SMIN PWM Section Start Threshold Min. Operation Voltage After Turn-On DC MAX Maximum Duty Cycle DC MIN Minimum Duty Cycle 0 Power Consumption Section Units ma V V V % 5

6 Current Mode PWM Controller Symbol Parameter Test Condition Min Typ Max I S Start-Up Current I Operating Supply Current V FB = V ISENSE = 0V Units ma Z V CC Zener Voltage I CC = 25mA 34 V Note: 4. These parameters, although guaranteed, are not 100% tested in production. 5. Parameter measured at trip point of latch with V VFB = Gain defined as: A = V COMP / V ISENSE ; 0 V ISENSE 0.8V 7. Adjust V CC above the start threshold before setting at 15V. 8. Output frequency equals one half of oscillator frequency. Block Diagram V CC * GROUND** 34 V UVLO S / R 5 V REF V REF 5.0 V 50 ma 16V (1844) 8.4 (1845) 6V (1844) 0.8V (1845) 2.5 V INTERNAL BIAS V REF GOOD LOGIC V C* R T /C T OSCILLATOR T OUTPUT ERROR AMP 2R S V FB COMP CURRENT SENSE R 1 V R CURRENT SENSE COMPARATOR PWM LATCH POWER GROUND** * - V CC and V C are internally connected for 8-pin packages. ** - POWER GROUND and GROUND are internally connected for 8-pin packages. Figure 1 Block Diagram 6

7 Characteristic Curves Characteristic Curves 2 Minimum Operating Voltage - (V) SGR1845 SGR1844 Frequency Drift - (%) 0 VIN = 15V Duty Cycle = 50% Junction Temperature - ( C) Junction Temperature - ( C) Figure 2 Dropout Voltage vs. Temperature Figure 3 Oscillator Temperature Stability Current Sense Delay - (ns) VPIN3 = 1.1V Start-Up Current - (ma) SGR SGR Junction Temperature - ( C) Figure 4 Current Sense to Output Delay vs. Temperature Junction Temperature - ( C) Figure 5 Start-Up Current vs. Temperature Reference Voltage - (V) VCC = 15V Reference Voltage - (V) SGR Junction Temperature - ( C) Junction Temperature - ( C) Figure 6 Reference Voltage vs. Temperature Figure 7 Start-Up Voltage Threshold vs. Temperature 7

8 Current Mode PWM Controller Start Up Voltage - (V) SGR1844 Oscillator Discharge Current - (ma) Junction Temperature - ( C) Junction Temperature - ( C) Figure 8 Start-Up Voltage Threshold vs. Temperature 2.5 Figure 9 Oscillator Discharge Current vs. Temperature Saturation Voltage - (V) C +25 C +125 C VIN = 15 V Duty Cycle < 5% Current Sense Threshold - (V) C 25 C -55 C Output Current - (ma) Error Amp Output Voltage - (V) Figure 10 Output Saturation Voltage vs. Output Current and Temperature (Sink Transistor) Figure 11 Current Sense Threshold vs. Error Amplifier Output 4.0 VIN = 15 V Saturation Voltage - (V) Duty Cycle < 5% +25 C +125 C -55 C +125 C +25 C Output Current - (ma) Figure 12 Output Saturation Voltage vs. Output Current and Temperature (Source Transistor) 8

9 Application Information Application Information The oscillator of the 1844/45 family of PWM's is programmed by the external timing components (R T, C T) as shown in Figure 14. V REF R T R T /C T GND C T F 1.86 Where R T 5kΩ R T C T Figure 13 Oscillator Timing Circuit RT - ( k Ω ) nF 47nF 22nF 10nF 4.7nF 2.2nF 1nF k 10k 100k 1M Oscillator Frequency - (Hz) Figure 14 Oscillator Frequency vs. R T for various C T 9

10 Current Mode PWM Controller Typical Application Circuits Pin numbers referenced are for 8-pin package and pin numbers in parenthesis are for 14-pin package. V CC V IN 7 (12) 7 (11) Q 1 6 (10) 5 (8) I PK R 3 (5) C R S I PK(MAX) = 1.0V R S Figure 15 Current Sense Spike Suppression The RC low-pass filter will eliminate the leading edge current spike caused by parasitic of Power MOSFET. V CC V IN 7 (12) 7 (11) 6 (10) R 1 Q 1 5 (8) R S 3 (5) Figure 16 MOSFET Parasitic Oscillations A resistor (R1) in series with the MOSFET gate reduce overshoot and ringing caused by the MOSFET input capacitance and any inductance in series with the gate drive. (Note: It is very important to have a low inductance ground path to insure correct operation of the I.C. This can be done by making the ground paths as short and as wide as possible.) 10

11 Typical Application Circuits VC + I B R2 V IN VC1 _ R1 II R2 V C 7 (11) VC1 C 1 6 (10) R 2 R 1 Q 1 5 (8) 3 (5) R S Figure 17 Bipolar Transistor Drive The 1844/45 output stage can provide negative base current to remove base charge of power transistor (Q 1) for faster turn off. This is accomplished by adding a capacitor (C 1) in parallel with a resistor (R 1). The resistor (R 1) is to limit the base current during turn on. V CC VIN 7 (12) Isolation Boundary 7 (11) Q1 6 (10) + V GS Waveforms 5 (8) 0 _ 50% DC R + 3 (5) C R S N S N P _ 0 25% DC I PK = V (PIN 1) 1.4 3R S ( ) N P N S Figure 18 Isolated MOSFET Drive Current transformers can be used where isolation is required between PWM and Primary ground. A drive transformer is then necessary to interface the PWM output with the MOSFET. 11

12 Current Mode PWM Controller V IN V CC 7 (12) 8 (14) 4 (7) 7 (11) Q 1 2 (3) 6 (10) 1N4148 C R 2 R 1 1 (1) 2N (9) 5 (8) 3 (5) R S 1 I PK = V 1 Where, 0 V R S R R 2 and V 1 = 1 + R1 R 2 V tsoftstart = -In1[ Vc Where, R2] V2 = R1R2 C R2+R2 R1 R2 Figure 19 Adjustable Buffered Reduction of Clamp Level with Softstart Softstart and adjustable peak current can be done with the external circuitry shown above. 8 (14) R A R B 555 TIMER 3 4 (7) C (9) f = f = 1.44 (R A + 2R B) C R B R A + 2R B To other Figure 20 External Duty Cycle Clamp and Multi-Unit Synchronization Precision duty cycle limiting for a duty cycle of <50%, as well as synchronizing several 1844/45's is possible with the above circuitry. 12

13 Typical Application Circuits 2.8 V 5 V 7 (11) 1.1 V _ R T + 6 (10) C T Discharge Current I d = 8.2 ma Figure 21 Oscillator Connection The oscillator is programmed by the values selected for the timing components RT and CT. Refer to application information for calculation of the component values. 2.5 V 0.5 ma 2 (3) R i 1 (1) R F R f 10K Figure 22 Error Amplifier Connection Error amplifier is capable of sourcing and sinking current up to 0.5mA. 13

14 Current Mode PWM Controller PACKAGE OUTLINE DIMENSIONS Controlling dimensions are in inches, metric equivalents are shown for general information. D 8 5 Dim MILLIMETERS INCHES MIN MAX MIN MAX A b E b c D E b2 ea e 2.54 BSC BSC ea H A L α H e b Q L SEATING PLANE c α Note: Q Dimensions do not include protrusions; these shall not exceed 0.155mm (.006 ) on any side. Lead dimension shall not include solder coverage. Figure 23 Y 8-Pin CERDIP Package Dimensions Dim MILLIMETERS INCHES MIN MAX MIN MAX D A b b E c D E e 2.54 BSC BSC ea ea H b2 A Q L c L α Q H e b α Note: Dimensions do not include protrusions; these shall not exceed 0.155mm (.006 ) on any side. Lead dimension shall not include solder coverage. Figure 24 J 14-Pin CERDIP Package Dimensions 14

15 PACKAGE OUTLINE DIMENSIONS Controlling dimensions are in inches, metric equivalents are shown for general information. PACKAGE OUTLINE DIMENSIONS b e A Q L E E c L S1 D Dim MILLIMETERS INCHES MIN MAX MIN MAX A b c D E E e 1.27 BSC BSC L Q S Note: 1. Lead No. 1 is identified by tab on lead or dot on cover. 2. Leads are within 0.13mm (.0005 ) radius of the true position (TP) at maximum material condition. 3. Dimension e determines a zone within which all body and lead irregularities lie. Figure 25 F 10-Pin Ceramic Flatpack Package Dimensions E3 D A A1 3 L2 8 E L Dim MILLIMETERS INCHES MIN MAX MIN MAX D/E E e BSC BSC B TYP TYP L A h TYP TYP A A L B R 0.008R 1 13 Note: All exposed metalized area shall be gold plated 60 micro-inch minimum thickness over nickel plated unless otherwise specified in purchase order. A2 h 18 B1 e B3 Figure 26 L 20-Pin Ceramic Leadless Chip Carrier Package Dimensions 15

16 Current Mode PWM Controller PRODUCTION DATA Information contained in this document is proprietary to Microsemi and is current as of publication date. This document may not be modified in any way without the express written consent of Microsemi. Product processing does not necessarily include testing of all parameters. Microsemi reserves the right to change the configuration and performance of the product and to discontinue product at any time. 16

17 Microsemi Corporate Headquarters One Enterprise, Aliso Viejo CA USA Within the USA: +1(949) Sales: +1 (949) Fax: +1 (949) Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor solutions for: aerospace, defense and security; enterprise and communications; and industrial and alternative energy markets. Products include high-performance, high-reliability analog and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners..0/01.0