Online Condition Monitoring of Insulated Gate Bipolar Transistor (IGBT)

Transcription

1 Online Condition Monitoring of Insulated Gate Bipolar Transistor (IGBT) A Thesis Submitted in Partial Fulfillment of the Requirements for the Degree of Master of Technology (M. Tech.) by Arun Singh ( ) to the DEPARTMENT OF ELECTRICAL ENGINEERING INDIAN INSTITUTE OF TECHNOLOGY KANPUR June, 2016

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3 Acknowledgement The first person I wish to thank is my professor Dr. Sandeep Anand because he has not only guided me in my thesis work but has also developed my way of thinking. I could feel the difference when I came to start the thesis work and now. It is in this duration of the research work that I learnt a lot of things and have matured in several ways and now I confidently can say that I can face any difficult situations in my life. I would like to thank my other professors Dr. S.P. Das, Dr. Santanu Mishra, Dr. S.N. Singh, Dr. B. Mazhari, Dr. Saikat Chakrabarti and Dr. Avinash Joshi for the knowledge they imparted me through the various courses they offered. I would like to thank my seniors Md.Waseem Ahmad and Shirazul Islam for their assistance and motivation all through my work.further, I would also like to thank all my lab mates Avinash, Anup, Ankul, Saurav, Rajender, Shoiab, Soumya, Paramhans and Nikunj I had great time with you people. Finally, I express my deep sense of reverence and gratitude to my parents for all their love, concern and encouragement.

4 Abstract Condition Monitoring (CM) provides an intelligent approach for improving the availability of the system by anticipating the failure of devices and planning a scheduled maintenance. Various methods are reported in literature for C.M. of IGBT. These methods require accurate knowledge of junction temperature which is either estimated or measured. Estimation is not accurate and increase the cost. Hence, they fails to provide accurate estimation the health of IGBT. In this thesis, a novel scheme is proposed for on-line C.M. of bond wires present in Insulated Gate Bipolar Transistor (IGBT) package. The proposed method detects bond wire degradation using on-state collector emitter voltage at the inflection point. The key advantage of the proposed scheme is that it monitors the bond wire degradation irrespective of the junction temperature and even in the presence of other degradation occurring because of ageing. Further to validate the proposed scheme, experiment setups for (i) Characterization (ii) Accelerated ageing (iii) full bridge inverter are developed, the proposed scheme is verified on the full bridge inverter prototype with one switch as device under test.

5 vi Abstract

6 Contents Abstract Table of content v vii 1 Introduction Background Past research in the field of reliability Thesis outline: Failure mechanism of IGBT Physical Structure of IGBT Turn on of IGBT: Failure Mechanism in IGBT Latch-up failure Dielectric Breakdown Bond wire lift-off Die attach degradation Literature Survey Bond wire degradation Non patent Literature survey Patent Literature Review Die-attach degradation Using Inverter Harmonics Using Case-above ambient temperature rise Using switching time based variation Problems associated with previous monitoring methods Proposed Scheme for on-line condition monitoring of IGBT Monitoring of bond wire degradation Inflection Point

7 viii CONTENTS 5 Experimental Results & Analysis Characterisation of IGBT Accelerated Ageing of IGBT DC Power Cycling AC Power Cycling Parameters of DC Power Cycling test bench Real time monitoring of V CE,ON Working of measurement circuit Evolution of V CE,ON at inflection point Conclusion and future work Conclusions Scope for Future Work

8 List of Figures 1.1 Distribution of fault in power converter [1] Model of IGBT Internal Structure of IGBT Internal Structure of a).discrete package (TO-220) b). Power module [2] Bond Wire lift off in IGBT power module [3] Cracks and Voids in Solder layer because of thermal cycling Increase in V CE,ON with ageing [4] Measurement of on-state resistance in linear region [5] Variation in Gate voltage waveform with degradation [6] Variation in peak gate current with ageing [7] Application of proposed method for C.M Block diagram of scheme [8] Condition monitoring of IGBT using high frequency measurement signal [9] Decrease in low order harmonic voltage because of solder fatigue [10] Decrease in T Case for same P Loss Change in turn-off time with die-attach degradation [11] IGBT model Flowchart for monitoring of bond wire degradation Full Bridge inverter circuit with D.U.T Circuit for characterisation of D.U.T Switching Pulses of switches for characterisation Experimental Setup for characterisation of IGBT inflection point in IGBT characteristics at gate votage 15V Circuit diagram for the DC power cycling of IGBT Switching Pulses for power cycling Increase in V CE,ON during on-duration of power pulse Measurement Circuit implemented on Gate Driver Board Output of Gate Driver Card Input v/s Output characteristics of Isolation Error amplifier Revised of Gate Driver card with measurement scheme along with dimension. 46

9 x LIST OF FIGURES 5.12 Full Bridge Inverter with D.U.T. along with measurement scheme Evolution of V CE,ON with ageing measured at inflection point

10 Chapter 1 Introduction This chapter provides an overview of this thesis topic presented. Initially, the relevant background which leads to the problem is given. Along with this, project objectives and what are the limitations also presented here. And finally, it contains the project outline. 1.1 Background Power electronics converter plays an important role in various electrical energy conversion process. And in these power electronic converter, power semiconductor switches are important components. Along with a proper control switching scheme for the switches, they provides a complete control on the power processing and it can be in terms of frequency,amplitude and phase shift. Their applications vary from laptop charger (few watts) to very high power solar inverter. From last few years, for energy, countries are trying to move their focus from non-renewable energy sources to renewable sources. But in order to do so, power electronics converter have to be more and more efficient, reliable along with this high power density also. But since they have

11 2 Introduction Figure 1.1: Distribution of fault in power converter [1] to work in very harsh environmental conditions without compromising with their performance, their reliability is important question. Hence, a lot of research is done in the field of increasing reliability of power electronic converter. However, according to industry surveys [1] [12], it has reported that power semiconductors are second largest most unreliable components as shown in Fig. 1.1 [1]. Therefore, condition monitoring of these semiconductor switches is required. But the normal operation should not be affected from the regular check-ups of the converter. Hence, an on-line condition monitoring for power semiconductors switches is required. In India, there is large scope of using solar energy. Currently, as of 31 st March, 2016, installed grid connected solar power capacity is MW and India expects to install an additional 10,000 MW by 2017 [13]. For this goal to achieved, it is required that efficiency as well as reliability of power electronics converter should be increased. In this thesis, a novel method to monitor the health of insulated gate bipolar transistors (IGBT) switches is proposed which are being used as switches of power electronic solar inverter.

12 1.2 Past research in the field of reliability Past research in the field of reliability The reliability of an item is defined as its ability to perform its required function under stated conditions (mission profile) for a stated period of time (mission time) [14]. In general, it is expressed by the probability of failure, or the frequency of failure. The necessity of addressing reliability issues in power electronics came up even since the 1950s mostly for transport and military applications. In these initial stages, for the prediction of the lifetime of a power electronic product handbook-based models were used (e.g. military hand-book MIL-HDBK-217F [14]) (e.g. mean-time-to-failure (MTTF), mean-time-between-failures (MTBF)).However, military handbook techniques are based on statistical data gathered from identical products. In the past years, various international standards already issued to build common guidelines over the testing methods in order to quantify the expected lifetime of a product. In the 1990s a new era in reliability studies has begun with the introduction of a different approach, the so-called Physicsof-Failure (PoF). This called for a paradigm shift to the physics of failure based analysis to determine the reliability of power semiconductor devices [15]. The main idea behind it to identify the main cause of failure, mechanism behind the failure [16]. The PoF infers to model and to analyse what cause the ageing in devices, such as temperature cycles, humidity etc., and how it cause a specific failure in device because of ageing. Instead of using statistical methods to determine the reliabilty of device, the information gained by PoF, provides important insights which can be used further in design phase, resulting in improving the overall performance of system. In order to perform reliability studies, Accelerated Life Tests (ALT) are used. The main idea behind it is, during ALT, the stress conditions on the device-under-test (DUT) is increased

13 4 Introduction than the stress conditions which device faces in the normal operation, causing the time of failure to decrease. By performing these ALT, they help in finding the weak points present in the device in the minimal period of time. In this thesis, a proposed scheme is validated on IGBT by accelerated ageing of device and testing the proposed scheme under realistic conditions as the device ages. 1.3 Thesis outline: Chapter 1 give the introduction of need if on-line condition monitoring of IGBT. Chapter 2 give the different failure mechanism in IGBT. Chapter 3 contains the past work done in the field of condition monitoring of IGBT. Chapter 4 explains the proposed scheme to monitor the health of IGBT on-line. Chapter 5 contains the description of experimental setup for the validation of proposed scheme. Chapter 6 presents the results and Chapter 7 include future work and conclusions.

14 Chapter 2 Failure mechanism of IGBT This chapter gives an overview of failure mechanism in IGBT. Section 2.1 contains the brief introduction about the physical structure of IGBT. Section 2.2 contains the details about the various failure mechanism of IGBT. 2.1 Physical Structure of IGBT Insulated Gate Bipolar Transistor is a three terminal power semiconductor device named as gate collector and emitter. Fig. shows the symbol. IGBT combine both the features of Power MOS- FET as well as bipolar junction transistor. In IGBT internal structure, MOSFET part provide the base current for the bipolar transistor and bipolar transistor modulates the conductivity of the drift region for the MOSFET structure. Advantage of having a input characteristics similar to MOSFET is having a high input impedance and making it a voltage controlled device. IGBT is modelled as a diode and mosfet in series as shown in Fig.2.1.

15 6 Failure mechanism of IGBT MOSFet Diode Figure 2.1: Model of IGBT Turn on of IGBT:- When positive voltage is applied between gate and emitter greater than the threshold voltage, then an inversion layer is created under the gate terminal in P-base region. Because of positive voltage applied between collector and emitter terminals, the electrons start flowing from emitter to collector drift region. As a result of which, the potential of the drift region decreases and causing the P-N junction between p + collector and n - layer to become forward biased. As a result, a high density of minority carrier holes are injected in the drift region from the p + collector. These injected holes in the n - drift region attract holes from the emitter to make it neutral. This result in high concentration of both electrons and holes causing the conductivity of drift region to increase. In the this way current flows through IGBT in the on-state. The more information can be found in [17].

16 2.2 Failure Mechanism in IGBT Failure Mechanism in IGBT Different failure mechanism in IGBT package are described in following section: Latch-up failure IGBT structure contains a parasitic thyristor as shown in Fig. 2.2 which if gets turned on then the control of IGBT by the gate voltage gets lost and IGBT is short circuited which can lead to very high current to pass through it causing burnout of semiconductor chip. Drift Region Resistance Collector Direction of current flow Gate Body region resistance Emitter Figure 2.2: Internal Structure of IGBT The parasitic thyristor is prevented from turning on by limiting the current gain of the two transistor as well as to reduce the value of resistance R B [17]. But when the collector current is very high, at the time of turn off, MOSFET channel is reducing and because of this, large amount of current flows through the R B. Causing the voltage

17 8 Failure mechanism of IGBT drop across the resistance to increases and result in turn on of the parasitic BJT. At this moment of time, control of gate voltage is no longer effective and the device reaches in the latch-up state. In this state high amount of current flow through the IGBT causing the burn-out of the IGBT semiconductor chip. The current at which latch-up phenomenon occurs is called latch-up current and its value is very high than the nominal current at normal operating temperature. But its value decreases as the junction temperature increases. Hence, IGBT is more likely to have latch-up failure as higher junction temperature. Latch-up failure is a type of chip related failure. Die level failure are those failure which occurs because of alteration of the semiconductor die. Usually, when the device is operated under normal operating condition then the probability of occurring of die level failure is very low in comparison to package level failure. [18] Dielectric Breakdown This failure is caused because of damage in insulating gate oxide layer during normal operation i.e. the electrons trapped in the oxide layer which creates a conductive channel. So, even when the gate voltage is less than the threshold voltage of IGBT, the conductive channel remain between collector and emitter of device, creating a short circuit and the control on the device is lost [18].

18 2.2 Failure Mechanism in IGBT Bond wire lift-off Bond wire are present in a package to provide the contact between external terminal and semiconductor die. Bond wire are connected in parallel to increase the current carrying capability of device. Internal structure of different packages of IGBT is shown in Fig. 2.3 [2]. When the Bond Wire Insulator IGBT semiconductor chip Solder Leads Copper Tab Mounting Hole (a) (b) Figure 2.3: Internal Structure of a).discrete package (TO-220) b). Power module [2] IGBT is used a switch in the application as inverter, current flows through the device, which cause power dissipation to occur on the chip and because of switching loss occur on the die. These losses contribute to increase the junction temperature of device. When the load current

19 10 Failure mechanism of IGBT changes or over a fundamental cycle of current the temperature of silicon die also under goes thermal cycle. Since, the IGBT package has different layers. So when the chip faces the thermal cycling, the temperature of different layers also faces the thermal cycles (but of different amplitude). Since the coefficient of thermal expansion is different for different materials used in the package, they expand and contract at different rates which creates thermo-mechanical stress between layers [19]. Overtime because of this stress, the junction between the bond wire and silicon die becomes weak and finally bond wire lift off from the silicon die and causes a open circuit failure in device as shown in Fig. 2.4 [3] and sometimes it breaks and creating a open circuit fault in the device because even if the gate voltage is greater than the threshold voltage, since the contact between external terminal and silicon die is lost and no current can flow through the device. Figure 2.4: Bond Wire lift off in IGBT power module [3]

20 2.2 Failure Mechanism in IGBT 11 But before the bond wire lift off, the contact between bond wire and silicon die increases, as a result, voltage drop across the IGBT during on-state increase resulting in increase in power dissipation increases which causes increase in junction temperature. Sometime this increase in junction temperature can cause catastrophic failures like latch-up or thermal run-away. In that case, bond wire degradation can cause short circuit failure Die attach degradation Die attach degradation or solder fatigue is the cracks or voids formation in the solder layer because of thermal cycling inside the IGBT package due to difference in coefficient of thermal expansion [19]. Because of solder fatigue, thermal resistance between junction to case increases causing increase in junction temperature. When junction temperature increases beyond safe operating area of device, it can cause latch-up failure as latch-up current is inversely proportional to junction temperature or can cause thermal run away in device. Bond wire degradation and solder fatigue are the most common type of failure mechanism which causes failure in IGBT when used as a switch. Fig.2.5 shows the cross-sectional view of IGBT module and the presence of cracks and voids in the solder layer. Cracks & voids IGBT chip Solder Layer Bond Wire Base Plate } DBC Substrate Figure 2.5: Cracks and Voids in Solder layer because of thermal cycling

21 12 Failure mechanism of IGBT

22 Chapter 3 Literature Survey This chapter gives the overview of past research work done in the field of C.M. monitoring of IGBT. As described in chapter 2, because of ageing, IGBT is more prone to failure mechanism which are related to packaging of IGBT. However, in failure mechanism related to packaging, bond wire degradation and die-attach degradation are most common types which occurs in IGBT as thermal stress is the most strong stress which IGBT has to face when it is used as a switch in real world applications. First section describes the past work done in the field of condition monitoring of bond wire degradation.

23 14 Literature Survey 3.1 Bond wire degradation Non patent Literature survey This section describes the research papers published in the field of condition monitoring of bond wire degradation Based on V CE,ON monitoring As described in chapter 2, the bond wire degradation causes increase in resistance, causing increasing the on-state voltage drop across switch to increase. Hence, for condition monitoring purposes, the on-state voltage drop is used. There is a gradual increase in V CE,ON as contact degraded and a step increase in voltage when the bond wire lift off event occur because in IGBT package bond wire are connected in parallel to increase the current capability of device. Hence when bond wire lift off, it causes the resistance to increase in step reflecting the same in V CE,ON. Fig. 3.1 shows the increase in V CE,ON with ageing [4]. Increase in resistance because of degradation of contact between bond wires and silicon die Figure 3.1: Increase in V CE,ON with ageing [4]

24 3.1 Bond wire degradation 15 However, in [20], to determine the bond wire degradation, the on-state collecter-emitter voltage is measured by injecting two different amplitudes of current,one with high value for determining the bond wire degradation and one with lower value (in ma) to estimate the junction temperature,when the converter is idle. By the information of junction temperature, the V CE,ON measured at the end of high amplitude current pulse, is compared with the healthy value of V CE,ON at injected current and increase in its value is attributed to degradation in bond wire degradation. This scheme was proposed for health monitoring of IGBT used in vehicle and injects current pulses during the vehicle idle time Based on on-state resistance Since, the bond wire degradation causes increase in on-state resistance. In [21], the on-state resistance is calculated by measuring on-state voltage at two different current level along with sensing case temperature and comparing it with resistance of healthy IGBT at that case temperature.initial look up table is made between on-state resistance and case temperature, and stored for comparison. Increase in on-state value is attributed to bond wire degradation. It can be implemented on on-line and can be used for condition monitoring without interrupting the normal operation of converter. Fig. 3.2 show the condition monitoring method.

25 16 Literature Survey Figure 3.2: Measurement of on-state resistance in linear region [5] Based on Gate voltage variation The method is to monitor the variation in gate voltage transient waveform during turn-on of device [6]. Change in gate voltage waveform is observed due to change in input capacitance of device because of bond wire degradation. Bond wire degradation causes increase in junction temperature because of increased power loss. But there is not significant change in gate voltage waveform when partial bond wire lift off from the silicon die. But when one of the chip failed, the variation is significant. This method is applicable to high power modules in which multiple IGBT chips are connected in parallel to increase the current carrying capability of module and one chip failure will not cause much complete module failure and can be used to generate a signal to notify the user to change the module. It is an offline monitoring method. Fig.3.3 show the variation in gate voltage as the module degrades [6].

26 3.1 Bond wire degradation 17 Figure 3.3: Variation in Gate voltage waveform with degradation [6] Based on Gate current variation In this method, for health monitoring of IGBT, peak gate current is used [7]. It was observed that the peak gate current changes as the degradation in the chip occurs. But there is not much significant change when partial bond wire lift off failure. However, noticeable change occurs when one of chip failed in multiple parallel connected chips in high power modules fails. As the previous method, this method is also an off-line method of condition monitoring. Fig. 3.4 shows the variation of peak gate current when one of chip failed in high power modules [7].

27 18 Literature Survey Figure 3.4: Variation in peak gate current with ageing [7] Patent Literature Review This section contains the description of patents in the field of condition monitoring of bond wire degradation. In DE A1 [22], it is proposed to monitor the saturation voltage using a measurement circuit implemented on gate driver board. Increase in value of V sat by 5% of pre-stored V sat of healthy IGBT module is considered as failure of device. Since V sat depends on load current and temperature, hence it was specified to measure V sat at pre-defined conditions (particular load and temperature) to avoid the effect the varying load conditions and varying ambient temperature. Fig. 3.5 shows the application of applying the condition monitoring method in drives [22].

28 3.1 Bond wire degradation 19 Supply Motor Figure 3.5: Application of proposed method for C.M. The patent US A1 [8], identified power semiconductor devices as the second most unreliable components after capacitor. In this patent, it is proposed to sense the case temperature and voltage drop across the switch in on-state condition. The measured V CE,ON is used to determine the remaining useful life (R.U.L.) of IGBT and when the R.U.L. decreases beyond the set limit, maintenance activity is schedule. Fig. 3.6 shows the block diagram of scheme [8]. Direct Current Power Source DC to AC current converter Communications System Decision Engine Sensors Service Provider Figure 3.6: Block diagram of scheme [8] The patent CN A proposed to monitor the V CE,ON periodically and compare it with the previously stored value of healthy IGBT module to determine whether the health of

29 20 Literature Survey IGBT is degraded or not. If the measured value of V CE,ON increases beyond the set critical value, then it is considered as the device has been failed. However, when the device is not degraded, the measured value of V CE,ON is used to determine the remaining useful life (R.U.L.) of device using simulation model. Further, the patent DE A1 [9], describes a method to monitor the health of IGBT using a high frequency measurement signal (having range of frequency from 100MHz to 240GHz). This signal is to the measurement point either by wire or by a coupling antenna. The reflected signal signature is used to compare with the healthy IGBT module to determine the amount of ageing and then use it to calculate the remaining useful life of power module. Fig. 3.7 shows the method of monitoring of IGBT using high frequency measurement signal [9]. Figure 3.7: Condition monitoring of IGBT using high frequency measurement signal [9]

30 3.2 Die-attach degradation Die-attach degradation As described in chapter 2, die attach degradation also occurs because of temperature cycling inside the IGBT package. And it causes cracks and voids formation in the die-attach layer of device, resulting in increase in thermal resistance between junction to case. This section describe the past work done to monitor the die attach degradation in IGBT package Using Inverter Harmonics To monitor the health of die attach of an IGBT module, the proposed method is to monitor the low order harmonics present in the output voltage of inverter because of non-ideal switching behaviour of switches [10]. This method uses the change in turn-off time of switch because of ageing. Because of die-attach degradation,junction temperature increases for a particular load current and ambient temperature, which increases the turn off time. Figure 3.8: Decrease in low order harmonic voltage because of solder fatigue [10]

31 22 Literature Survey However, to monitor the small change in magnitude of low-order harmonics, a controlled harmonic resonance is introduced at the harmonic frequency. In addition to this, an outer loop is also placed, to suppress the harmonic current because of resonance. The voltage signal of outer loop is used for condition monitoring. Fig. 3.8 show the result of this method [10]. This is an on-line condition monitoring method Using Case-above ambient temperature rise In [23], a three dimensional lookup table was created between device current, case aboveambient temperature and power loss for a healthy IGBT module. Using the thermal model of heat-sink (which was assumed to be constant during the whole operation of inverter), power loss in the each IGBT was estimated. For the same power loss and for the same device current, decrease in case temperature is used to detect the increased junction to case resistance because of solder fatigue. It is however assumed that the solder fatigue causes a rise in the junction-case thermal resistance and the junction temperature which causes an increase in power loss. Fig shows the result of proposed method in a device having die attach degradation [23]. The proposed method is an on-line condition monitoring method.

32 3.2 Die-attach degradation 23 Figure 3.9: Decrease in T Case for same P Loss due to solder fatigue [10] Using switching time based variation The increase in turn-off time because of increased junction temperature caused due to die attach degradation. In [11], it has been showed that this change in turn-off time can be used as a precursor for solder-fatigue. However, this is method of off-line condition monitoring. The increased turn-off time with ageing is shown in Fig Figure 3.10: Change in turn-off time with die-attach degradation [11]

33 24 Literature Survey 3.3 Problems associated with previous monitoring methods 1. Methods using V CE,ON Advantage: The direct implication of health of bond wire contact as degradation will cause increase in on-state voltage Disadvantage: Depends on both current and junction temperature. Difficult to isolate the effect of junction temperature and ageing on increase in V CE,ON. The voltage between collector and emitter switches between high blocking voltage to few volts. Further, because of ageing, change in on-state voltage is in millivolts, it is difficult to correctly detect the increase. Depends on the load current. 2. Method to monitor the change in peak gate current Advantage: Independent of load current Does not require the knowledge of junction temperature Disadvantage:

34 3.3 Problems associated with previous monitoring methods 25 Can be applied only to high power module which contains multiple parallel connected chips are present. Not applicable to low power IGBT package (like discrete devices) The change in peak gate current is very small and difficult to implement the proposed scheme for on-line monitoring An off-line condition monitoring method 3. Method to monitor the change in gate voltage variation Advantage: Independent of load current Independent of junction temperature Disadvantage: Can be applied only to high power module which contains multiple parallel connected chips are present. Not applicable to low power IGBT package containing single silicon chip (like discrete devices). Change in the transient waveform of gate voltage is very small (within few nano seconds) An off-line monitoring method 4. Using high frequency measurement signal Advantage:

35 26 Literature Survey Independent of junction temperature Independent of load current Can accurately find the location and type of degradation Disadvantage: Require the modification in IGBT module to make a measurement point. High cost of implementation and high complexity. 5. Using low order harmonics in output of inverter Advantage: Can detect the solder fatigue accurately but if only die attach degradation is present Does not require other sensors for implementation Disadvantage: In the presence of bond wire degradation, give erroneous results Also change in ambient temperature, could give wrong information about ageing This method is ineffective in telling which specific IGBT is aged and the type of degradation it is suffering from. 6. Using case above temperature rise Advantage: Can detect solder fatigue accurately only if other degradation are absent

36 3.3 Problems associated with previous monitoring methods 27 Disadvantage: It requires large look-up table to be made between P Loss, load current and case temperature. In presence of other degradation (bond wire), can give inaccurate results. Requires additional temperature sensors.

37 28 Literature Survey

38 Chapter 4 Proposed Scheme for on-line condition monitoring of IGBT This chapter describe the proposed scheme for on-line condition monitoring of IGBT to determine the condition of bond wire and die attach within the package as they are the most common type of degradation occurring in IGBT when used in real world as switch. 4.1 Monitoring of bond wire degradation As described in Chapter 3, for bond wire degradation, V CE,ON is used for condition monitoring purposes. But since the V CE,ON is temperature is dependent, so it is very difficult to remove the effect of temperature on increase in on-state voltage. However the proposed method for online condition monitor the health of IGBT at inflection current.

39 30 Proposed Scheme for on-line condition monitoring of IGBT Inflection Point IGBT model consists of diode in series with a MOSFET in conducting state as shown in Fig. 4.1 [20]. MOSFet Diode Figure 4.1: IGBT model Voltage drop across the IGBT in on-state condition is given in 4.1 [20]. V CE,ON = V Diode + V MOSF ET (4.1) Diode has negative temperature coefficient but MOSFET has positive temperature coefficient. Hence, on-state voltage of IGBT can be written as a function of temperature in 4.2, where and are the temperature coefficient of the diode and R DS,ON of MOSFET, respectively [20]. V CE,ON (T J, I C ) = [V D0 α(t J T J0 )] + [R ON0 + β(t J T J0 )] I C (4.2) When the current flowing through the IGBT is low, the voltage drop across the MOSFET is small and diode drop is dominating. Hence the on-state voltage drop of IGBT have characteristics of diode drop and shows the negative temperature. However, when the current through the IGBT is high, the on-state voltage drop is governed by the MOSFET voltage drop and shows

40 4.1 Monitoring of bond wire degradation 31 the positive temperature coefficient. So, as the current increases, the on-state voltage drop shifts from negative temperature coefficient to positive temperature coefficient and the point where the on-state voltage is independent of temperature is knows as inflection Point. Start Sense inductor current I L & V ce,on of each IGBT Is I L = I inflection Yes No Go to Step 1 Is V ce,on > (V ce ) critical. No Go to Step 1 Yes IGBT is failed Figure 4.2: Flowchart for monitoring of bond wire degradation As a result, in Ic v/s Vce,on characteristics, inflection point is present. So, the Vce,on at the inflection point current can only increase because of degradation of bond wire and emitter metallization only. Even in the presence of other type of degradation, this method can be used to find the health of bond wire. Hence, it was proposed to monitor the V CE,ON of IGBT when current passing through the IGBT is equal to inflection point current and when it is increases from its healthy state value by

41 }Switching Signals 32 Proposed Scheme for on-line condition monitoring of IGBT S 1 S 3 L-C Filter DC Voltage Source S 2 S 4 to S 1 S 4 D.U.T. V CE,ON of D.U.T. Inductor Current (I L ) R-Load D.S.P. Figure 4.3: Full Bridge inverter circuit with D.U.T. 15%, it is considered as failure of IGBT. Fig. 4.2 shows the proposed scheme to monitor the bond wire degradation in the form of flow chart.

42 Chapter 5 Experimental Results & Analysis This chapter describes the experimental setup for the validation of proposed scheme for bond wire degradation. For experimental validation, the device under test was a discrete IGBT (TO- 220 package) of STMicroelectronics STGB40V60F (rated 600V/40A). 5.1 Characterisation of IGBT As described in chapter 4, the proposed scheme to monitor the bond wire degradation require the knowledge of inflection point. In order to find the inflection point, the characteristics of IGBT is required at different temperature. As described earlier, on-state voltage depends on temperature. So, when the current flows through the device because of conduction losses, it can increase the junction temperature and since it is not possible to measure junction temperature, the measured on-state voltage will be at different temperature from ambient temperature. In order to prevent the self heating, the

43 34 Experimental Results & Analysis duration of current has to be minimum. Hence, the injected current in D.U.T. was only for 500s and it was assumed that in this duration of time, the self heating in device will not create significant change in junction temperature. Similarly to prevent the switching losses to occur and causing change in the junction temperature, the D.U.T. was kept on for the whole duration. To make the junction temperature same as ambient temperature, device was allowed to cool down for 2s and in this duration, current was allowed to flow through the by-pass leg. Circuit diagram for characterisation is shown in Fig 5.1. S 1 S 3 Current Source S 2 S 4 D.U.T. By Pass Leg Figure 5.1: Circuit for characterisation of D.U.T. To prevent the switching of power supply, 100s was overlap was given in the switching pulses as shown in Fig.5.2. The by-pass leg was of FSBB20CH60C. For characterisation, the current was varied from 0A to 11A with a fixed temperature. In order to maintain a constant ambient temperature, a thermal chamber was used and K-type thermocouple used to measure the inside temperature of

44 5.1 Characterisation of IGBT µs S1 2s time (s) S3 & S4 time (s) 100µs overlap time Figure 5.2: Switching Pulses of switches for characterisation thermal chamber. Fig. 5.3 shows the experimental setup of characterisation. Since the value of inflection point depends on gate voltage, hence in the whole experiment the gate voltage was maintained constant equal to 15V. The experiment was repeated for four different temperature. The I C v/s V CE,ON was plotted and the inflection point was found to be equal to 5.8A at gate voltage 15V as shown in Fig. 5.4.

45 36 Experimental Results & Analysis Figure 5.3: Experimental Setup for characterisation of IGBT 5.2 Accelerated Ageing of IGBT When IGBT is used as a switch in applications, the stress faced by device is because of temperature cycling which causes ageing in device and finally causing failure as explained in Chapter 2. Therefore, for highly accelerated ageing of device, the magnitude of temperature cycling has to be increased. In literature, two methods are described for accelerated ageing [24] :-

46 Current (in ma) 5.2 Accelerated Ageing of IGBT C C C C Inflection point =5.8A Voltage (in mv) Figure 5.4: inflection point in IGBT characteristics at gate votage 15V Active Thermal Cycling Passive Thermal Cycling In passive thermal cycling, the ambient temperature, in which the D.U.T.is placed, is cycled to create cycling in the junction temperature of IGBT. This method is not recommended for acclerated ageing, as the stress when IGBT is used in applications is different because the power cycling causes the cycling in junction temperature. This method does not exactly replicate the stress [24]. In active thermal cycling, by switching(on and off) the power loss on the silicon die, cycling in the junction temperature is created. Hence, by creating a high magnitude of temperature cycling on the junction, the accelerated ageing of IGBT is carried out in laboratory conditions.

47 38 Experimental Results & Analysis Power cycling of smaller duration causes degradation in bond wire and silicon die contact while power cycling of larger duration causes degradation in die-attach. Active power cycling are also of two types as following [24]:- DC power cycling AC power cycling DC Power Cycling A constant current flows through the device for some duration which causes power loss on the die. Due to power loss, the temperature of device increase and then the device is turned off and allowed the junction temperature to cool down to ambient temperature. In this way, the temperature cycling on junction is created. The magnitude of T depends on the on-duration and off duration. At the end of the on-duration, junction temperature will maximum and T Jmax. must be less than the maximum operating junction temperature of device. The maximum junction temperature of IGBT chip can be calculated by eq. 5.1 T J = P Loss R th,jc + T Case (5.1) The DC power cycling method is simple and the monitoring of parameters is also easy. However, in DC power cycling method, ageing of IGBT occurs only and not the diode. Hence it is different from the real world stress as diode also ages. But usually, IGBT undergoes failure and not the diode [put the ref.]. Hence this method can also be used for ageing of IGBT.

48 5.2 Accelerated Ageing of IGBT AC Power Cycling In the AC power cycling, the pulse width modulated switching sequence is applied till the junction temperature reaches a maximum temperature and then the device is allowed to cool down to ambient temperature. Since it involves switching of device causing switching loss to occurs which is more realistic stress on the device. Since the IGBT faces temperature cycling while used in inverter because of sinusoidal current. But the fundamental frequency is high causing a small magnitude of T on the junction. So, to create a high amplitude of T on the junction, a much lower fundamental frequency current is given as reference and causing the accelerated ageing of device. Since in this case, diode also conducts and switching of device also occurs. Hence it is considered to be very much closer to the real world stress the IGBT faces Parameters of DC Power Cycling test bench However, because of simplicity of DC power cycling method, it was used for ageing of IGBT and validation of proposed scheme. For accelerated ageing of IGBT, DC power cycling method. For 4s continuously, 11.6A current was forced to flow through the D.U.T. which increases its junction temperature because of power loss and then for 6s, no current flows through the device causing junction temperature to cool down. In this way, high magnitude of temperature cycling was created on the junction of IGBT to accelerate the ageing. With this frequency of power cycling, the V CE,ON was varying by 50mV in one cycle. From the characterization curve, this amount of variation in V CE,ON at gate voltage equal to 15V and

49 40 Experimental Results & Analysis S 1 S 3 Current Source S 2 S 4 D.U.T. By Pass Leg Figure 5.5: Circuit diagram for the DC power cycling of IGBT current equal to 11A, will cause a T of 50 0 C in junction. Further the current source was made using a DC power supply in constant current mode. To prevent the switching of DC supply, a overlap of 200s was given between the switching pulses of two legs which was similar to characterization case. Fig. 5.5 shows the circuit diagram for the accelerated ageing of IGBT (DC Power Cycling Setup) Since the current for creating power loss on the junction is of low value and resulting lower magnitude of T. Since gate voltage is inversely related to the on-state resistance of the device. To increase the on-state state resistance value, gate voltage was decreased from 15V to 7.5V and the To increase the magnitude of T on the junction, gate voltage was decreased from 15V to 7.5V. Switching pulses of S 1,S 3,S 4 is shown in Fig. 5.6 for power cycling. Fig. 5.7 shows the change in V CE,ON during the on-duration when 11.6A current flows through the D.U.T. indicating the change in junction temperature also during power cycling setup.

50 5.2 Accelerated Ageing of IGBT 41 4s 6s time (s) S3 & S4 S1 time (s) 100µs overlap time Figure 5.6: Switching Pulses for power cycling Figure 5.7: Increase in V CE,ON during on-duration of power pulse

51 42 Experimental Results & Analysis 5.3 Real time monitoring of V CE,ON The main challenge in using V CE,ON as a monitoring parameter is the switching of V CE,ON switches from few volts to hundred volts. Further, because of ageing, the change in V CE,ON is also very small. But by using the measurement circuit, shown in Fig. 5.8, which was implemented on the gate driver board, the V CE,ON can be measured accurately [25]. I dc V 2 D 1 D 2 VCE,ON V 1 R 1 R 2 +V SS V out -V EE Figure 5.8: Measurement Circuit implemented on Gate Driver Board The normal operation of gate driver card is shown in Fig Figure 5.9: Output of Gate Driver Card

52 5.3 Real time monitoring of V CE,ON Working of measurement circuit When the IGBT is on:- Value of resistances R 1 and R 2 equals to 100Ω. Current source value equal to 100mA. When the IGBT is in turned on state, the current source will make the diodes D 1 and D 2 forward biased. To measure the V CE,ON correctly, both the diodes has to be thermally coupled. Voltage at node 1 will be V 1 = V CE,ON + V D1 (5.2) Since both the diodes are thermally coupled, hence the voltage at node 2 will be:- V 2 = V CE,ON + V D1 2 (5.3) Since the op-amp is in negative feedback, virtual short between inverting and non-inverting terminal exist. Hence voltage of inverting terminal will be equal to V = V + = V CE,ON + V D1 (5.4) Hence, V out will be equal to V 2 V R 1 (V CE,ON + 2 V D1 ) (V CE,ON + V D1 ) R 1 = V V out R 2 = (V CE,ON + V D1 ) V out R 2 (5.5)

53 44 Experimental Results & Analysis Since R1 and R2 are equal, hence the above equation becomes, V out = 2 (V CE,ON + V D1 ) (V CE,ON + 2 V D1 ) V out = V CE,ON (5.6) When IGBT is off:- When the IGBT is off,the voltage between collector emitter is high, as the switch is blocking the voltage. The high voltage is blocked by the diode D 1 block, to prevent the op-amp. In this duration, current I DC flows through the resistance R 1 and R 2. And there exist a finite voltage difference between inverting and non-inverting terminal of the op-amp. Hence, in this case, the output voltage of the op-amp will be V SS. For high side IGBT, the problem of high common mode voltage. The measured small voltage cannot be used for C.M. purpose. Hence to remove the common mode voltage, the isolation error amplifier (ADuM3190) was used. The ADuM3190 is having a linear response which was found by initial calibration. Fig shows the input v/s output voltage relationship of ADuM3190 where input voltage is the voltage at the collector position in the measurement circuit and output voltage is the voltage after low pass filter (with cut-off frequency of 1MHz) put at the output of the ADuM3190. The equation of this line was put in the microcontroller to find the actual V CE,ON of the IGBT.

54 Output Voltage of Isolator (in mv) 5.3 Real time monitoring of V CE,ON Input Voltage to Isolator (in mv) Figure 5.10: Input v/s Output characteristics of Isolation Error amplifier

55 49 mm 46 Experimental Results & Analysis The first version of gate driver board with the measurement scheme is shown in Fig IGBT gate driver card with measurement scheme The revised version of gate driver card is shown in Fig mm Figure 5.11: Revised of Gate Driver card with measurement scheme along with dimension

56 5.4 Evolution of V CE,ON at inflection point Evolution of V CE,ON at inflection point To validate the proposed scheme, D.U.T. was replaced by the one of the switch of full bridge inverter. The measured V CE,ON was send to ADC pin of microcontroller. At the output of the full bridge inverter, before load, a LC filter was connected to attenuate the switching frequency components. Since the change in measured V CE,ON was very small which was very difficult to detect using normal differential probes. Hence, the V CE,ON was taken out the duty cycle of the PWM signal. When the sensed current was in the range of 5.8A and 6.0A, the sensed voltage was made as duty cycle of PWM signal. To make sure that the while calculating the duty cycle current was flowing through the IGBT only, the gate voltage was also sensed. When gate voltage was high and direction of current is positive, then the duty cycle of PWM signal was changed according to the sensed voltage. The parameters of full bridge inverter is shown in table 5.1 Inverter Parameters Values DC link Voltage 70 volts DC link Capacitor 470 F(Electrolytic) Peak current 6.5A Inductor (Filter) 1.5 mh Capacitor (Filter) 10 F Modulation Index Modulation Scheme Unipolar Modulation Table 5.1: Parameters Of Inverter From the filter parameters, the cut-off frequency of the filter was 1.3kHz. Fig.5.12 shows

57 }Switching Signals 48 Experimental Results & Analysis the circuit for full bridge inverter with the measurement scheme. S 1 S 3 L-C Filter DC Voltage Source S 2 S 4 to S 1 S 4 D.U.T. V CE,ON of D.U.T. Inductor Current (I L ) R-Load D.S.P. Figure 5.12: Full Bridge Inverter with D.U.T. along with measurement scheme To determine the evolution of V CE,ON with ageing of IGBT at inflection point, the power cycling test was interrupted after some cycles and the V CE,ON was measured. Initially, the difference of power cycles between two measurement of V CE,ON was larger. But as the device aged, the difference of power cycles continue to decrease from twenty thousand cycles to one thousand cycles. Fig show the evolution of V CE,ON with ageing at inflection point.