F.Y. Diploma : Sem. II [DE/EJ/IE/IS/EE/MU/ET/EN/EX] Basic Electronics

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F.Y. Diploma : Sem. II [DE/EJ/IE/IS/EE/MU/ET/EN/EX] Basic Electronics Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 70 Q.1 Attempt any FIE of the following : [10] Q.

1 F.Y. Diploma : Sem. II [DE/EJ/IE/IS/EE/MU/ET/EN/EX] Basic Electronics Time: 3 Hrs.] Prelim Question Paper Solution [Marks : 70 Q.1 Attempt any FIE of the following : [10] Q.1(a) Draw the symbols for (i) LED (ii) Photodiode [2] [1 mark each symbol] (i) Symbol of LED (ii) Symbol of Photodiode Q.1(b) State any two application of MOSFET [2] Applications of MOSEFT [1 mark each application] MOSEFT are used in realization of digital logic gates or switches. MOSEFT are used in design of amplifier. MOSEFT can be used to transfer charge from one node to another node i.e. pass transistor. Q.1(c) Why CE configuration is preferred for amplifier. [2] [Any two point 2 marks] CE configuration is preferred for amplifier due to the following reasons : (i) It has a high voltage gain as well as a high current gain. (ii) As voltage gains as well as current gains are high, it has a very high power gain. (iii) The CE configuration has moderate value of input impedance ( i ) and output impedance ( o ). Therefore many such stages can be coupled to each other without using any additional impedance matching circuits. Q.1(d) Draw the symbols of nchannel and pchannel JFET. [2] [1 mark each symbol] (i) Symbol of nchannel JFET (ii) Symbol of pchannel JFET D D G G S S Q.1(e) State any two applications of LED [2] Applications of LED [½ mark each application] (i) In 7segments, 16segment and dot matrix displays. (ii) For indicating power ON/OFF conditions, power level indicators in stereo amplifiers. (iii) In optical switching applications. (iv) For image sensing circuits in picturephone. Q.1(f) Define TUF for a rectifier and state its value for half wave rectifier and full [2] wave rectifier. TUF : Transfer Utilization Factor : It is the ratio of DC power delivered to the load to the AC rating of the transformer secondary. TUF = DCPowerdeliveredtotheload. ACratingofthetransformersecondary TUF for a halfwave rectifier is whereas for centertap and bridge rectifier is and respectively

2 F.Y. Diploma BE Q.2 Attempt any THEE of the following : [12] Q.2(a) Draw and explain zener diode as voltage regulator [4] [Diagram 1 mark each and Explanation 1 mark] Zener oltage egulator I characteristics of a zener diode is as shown below A B Under the reverse bias condition, the voltage across the diode remains almost constant although the current through the diode increases as shown in region AB. Thus, the voltage across the zener diode serves as a reference voltage. Hence, the diode can be used as a voltage regulator. Circuit diagram of zener voltage regulator is as shown below, it is required to provide across load resistance L. Whereas the input voltage may be varying over a range. Zener diode is reverse biased and as long as the input voltage does not fall below z (zener breakdown voltage), the voltage across the diode will be constant and hence the load voltage will also be constant. Q.2(b) What is need of biasing for BJT? Draw the voltage divider bias Ckt for BJT? [4] [Diagram 1 mark each and Explanation 1 mark] (i) Biasing is need to make o/p current independent of change in temperature as output current (I C ) depends on 3 parameters viz I CO (Leakage current), BE (voltage between base and emitter) and (current gain). Each of 3 parameters depending on temperature. (ii) Transfer can operate in any of the three regions (cutoff, active or saturation). To operate the transistor in these regions, the junctions of a transistor should be forward or reverse biased. The required bias voltage can be obtained by means of biasing. CC 1 C I B I C B CE I E L E oltage divider bias - 2 -

3 Prelim Question Paper Solution Q.2(c) Compare avalanche breakdown with zener breakdown. [4] [1 mark each point] Parameter Avalanche Breakdown Zener Breakdown 1. Doping concentration Lightly doped junction are Highly doped junction are likely to undergo likely to undergo zener avalanche breakdown. breakdown. 2. Width of depletion layer Wider depletion layer Narrow depletion layer 3. oltage Level Avalanche breakdown occurs above 6 4. Characteristics Gradually decreasing i.e. not very sharp Zener breakdown occurs below 6 ery sharp 5. Application Used in rectifying diode Used in regulator circuit Q.2(d) Explain concept of DC Loud Line and Qpoint in BJT. [4] Consider the common emitter configuration C i C C BB B i B BE E CE CC In this circuit CC and BB are used to bias transistor in active region. This condition of amplifier is known as QUIESCENT CONDITION or dc bias condition because there is no ac signal is applied. From Collector loop CC I C C CE = 0 (KUI to collector loop) CC CE = I C C I C = 1 C CE CC C This equation is similar to the general equation of a straight line i.e. y = mx C. 1 y = I C, x = CE, m = and C = CC C C Plotting above equation gives dc load line as shown below - 3 -

4 F.Y. Diploma BE I C (max) = CC C I C (ma) Active egion I B = 40 A Saturation region I CQ Q- Point DC load line I B = 30 A I B = 20 A I B = 10 A I c = I CE = I B = 0 A 0 CEQ Cut-off region CE = CC CE (olts) Since slope of the line is inversely proportional to DC load ( C ) it is known as DC load line. The DC load line is used to set up maximum dc voltage and current of the amplifier. All the points at which I C and CE intersect on DC load line are known as operating points. Operating point is also known as quiescent point (Q point) or bias point because it represents the dc bias condition. Significance of Qpoint Application of transistor depends on the position of the Qpoint on the load line as shown below Application Open Switch Closed Switch Amplifier Position of Qpoint In the cutoff region In the saturation region In the active region Q.3 Attempt any THEE of the following : [12] Q.3(a) Draw experimental setup to obtain Input and Output characteristics of CE [4] configuration. [Diagram 2 marks and Explanation 2 marks] Experimental setup to obtain Input and Output characteristics BB I B ma BE ma CE I C CC To determine the input characteristics, the collector to emitter voltage ( CE ) is kept constant at zero volt and base current is increased from zero in equal steps by increasing BE in the circuit shown above. The value of BE is noted for each setting of I B. This procedure is repeated for higher fixed values of CE and the curves of I B vs BE are drawn. To determine the output characteristics, the base current I B is kept constant at a suitable value by adjusting baseemitter voltage, BE. The magnitude of collectoremitter voltage CE is increased in suitable equal steps from zero and the collector current I C is noted for each setting CE. Now the curves of I C vs CE are plotted for different constant values of I B

5 Prelim Question Paper Solution Q.3(b) Draw the inputoutput waveform for following circuit. Explain the working of circuit (Assume input to be sinusoidal) S i [4] Given Circuit i 1 o S i i 1 o InputOutput Waveform in 1.7 t out 1.7 t Given circuit is biased positive parallel clipper in which a battery of potential 1 is connected in series with diode D in such a way that due to battery diode becomes reverse biased. Working (i) During the positive half cycle, as long as input is below 1 the diode D is reverse biased and acts as an open circuit and no current flows through the circuit Then o = i But when i (1 0.7), then diode starts conducting and acts as a short circuit. o = 1.7 (ii) During the entire negative half cycle, diode remains reverse biased. Therefore no current flows through the circuit. Hence o = in Q.3(c) A JFET has train current of 3.5 ma, If I DSS = 10 ma, GS (off) = 4. Find the value of (i) GS (ii) g m (Transconductance) Given I D = 3.5 ma, I DSS = 10 ma, GS (off) = 4 GS =?, g m =? 2 GS I D = I DSS 1 GS (off) GS 3.5 m = 10m1 4 2 [4] - 5 -

6 F.Y. Diploma BE 3.5m = 10m 0.35 = 0.35 = = 1 GS 4 1 GS 4 GS 1 4 GS GS = 4 GS = g m = 2I DSS GS 1 p p = 210mA = ma 1 4 g m = m Q.3(d) Sketch the block diagram of regulated DC power supply. Explain O/P waveform of [4] each block. [Diagram 2 marks and Description of each block 2 marks] Block diagram of regulated DC power supply A transformer supplies a.c. voltage at the required level. This bidirectional a.c. voltage is converted into a unidirectrional pulsating d.c. using a rectifier. The unwanted ripple contents of this pulsating d.c. are removed by a filter to get pure d.c. voltage. The output of the filter is fed to a regulator which gives a steady d.c. output independent of load variations and input supply fluctuations. Q.4 Attempt any THEE of the following : [12] Q.4(a) Sketch filter with fullwave bridge rectifier and state advantages of filter. [4] [3 marks] Filter L - 6 -

7 Prelim Question Paper Solution Advantages of filter (i) It has very low and smallest amount of ripple factor. (ii) It is useful for low load current i.e. light loads. (iii) The quality of output DC voltage is very good. (iv) It is easy to design. Q.4(b) Sketch fixed bias and base bias with emitter feedback circuit. [4] (i) Fixed Bias CC B C Stability of the circuit is very poor, hence rarely used in amplifier circuit. (ii) Base Bias with emitter feedback CC C B It is also known as collector to base bias. Stability is better than fixed bias. Due to negative feedback between input and output (in CE configuration) voltage gain reduces. Q.4(c) Explain thermal runway in BJT. [4] Thermal runway in BJT I CEO = (1 ) I CBO I CBO T I CEO P D I C = I B I CEO P D = I 2 C t I C Thermal runaway as egenerative - 7 -

8 F.Y. Diploma BE For CE configuration, output current I C is given as I C = I B (1 )I Co Where I Co is leakage current, which doubles for every 10C rise in temperature. As the temperature increases, leakage current I Co increases, which increase the collector current I C. Increase in I C, will increase power dissipation (P D ) in collector region. Since P D is in the form of heat, temperature of collector further increases. This cumulative action continues and temperature of transistor reaches to an extent that transistor burns. This is known as thermal runaway. Q.4(d) Draw the self biasing circuit for JFET and explain why gate current is zero in JFET. Self biasing circuit for JFET [4] Self biasing is used in JFET to achieve zero temperature draft i.e. to have no effect of change in temperature on drain current I D. For self bias GS = I D S and for JFET 2 GS I D = I DSS 1 p On solving above two equation, we get Qpoint for the circuit. Why gate current is zero in JFET Under no bias condition, the depletion layer at each junction does not allow any conduction. Due to presence of depletion layer at gate terminal, current through gate terminal is zero. I G = 0 is an important characteristics of JFET. Q.4(e) With an example explain Clamper Circuit. [4] Sometimes it is necessary to add a dc level to the ac signal. The circuits which are used to add dc levels as per the requirement into the ac signal are known as Clamper circuits. Example of clamper Circuit i D O - 8 -

9 Prelim Question Paper Solution i 0 T/2 T t o o t 2 A square wave with maximum amplitude of is given as the input to the network. During the positive half cycle, the diode conducts i.e. it acts like a short circuit. The capacitor charges to volts. During this interval, the output which is taken across the short circuit will be o = o. During the negative half cycle, the diode is open. The output voltage can be found out by applying Kirchhoff s law. o = 0 o = 2 Q.5 Attempt any TWO of the following : [12] Q.5(a)Sketch structure of Etype MOSFET. Explain how channel is enhanced? [6] Etype MOSEFT Fig. : n-channel enhancement type MOSFET Creation of Channel : The positive potential at the gate will pressure the holes in the Psubstrate along the edge of the SiO 2 layer to leave the area and enter deeper region of the Psubstrate

10 F.Y. Diploma BE Fig. : Channel formation in the n-channel enhancement type MOSFET As GS increases in magnitude, the concentration of electron near the SiO 2 surface increases until eventually the induced nregion can support a measurable flow between drain and source. The level of GS that results in the significance increase in drain current is called the threshold voltage ( T ). Since the channel is nonexistence with GS = o and enhanced by application of a positive gate to source voltage, this type of MOSFET is called an enhancement type MOSFET. [4 mark] Q.5(b) Define the following parameters of rectifier [6] (i) ripple factor (ii) efficiency (iii) P. I. (i) ripple factor : the ripple factor of a rectifier is a ratio of r.m.s. value of the alternating component in the load to the DC components in the load of a rectifier. r MSalue ofaccomponentsin theload = Averageord.c. componentsin theload r = 1.21 for HW = for FW (ii) Efficiency (ectification efficiency) : The rectification efficiency of a rectifier is a ratio of the DC power output delivered to the load to the AC power input supplied to the rectifier circuit. DCPowerOuptut = ACinputpower fromtransformersecondary = 40.6 % for HW = 81.2 % for FW (iii) Peak Inverse oltage (P. I. ) : The maximum value of reverse voltage that a diode can withstand without destroying its P N junction during the nonconduction period is called peak inverse voltage. P.I.. = m for HW = 2 m for center tap FW = m for bridge FW

11 Prelim Question Paper Solution Q.5(c) Draw structure and characteristics of photodiode. Also state its applications. [6] Structure of photodiode Light P N Characteristics of Photodiode Dark Current 10,000 m/m 2 15,000 m/m I (ma) 20,000 m/m Applications of Photodiode : (i) Detection of both visible and invisible. (ii) Demodulation of modulated signles. (iii) Switching (iv) Logic circuit that require stability and high speed. (v) Character recognition etc. Q.6 Attempt any TWO of the following : [12] Q.6(a) Draw experimental setup to obtain I characteristics of P junction diode. [6] Draw I characteristics for the same and mark important levels. (i) Circuit arrangement for forward characteristics Diode ma AB (ii) Circuit arrangement for reverse characteristics. Diode ma AB p

12 F.Y. Diploma BE Forward Current (ma) B B A 0.7 I o Forward oltage everse Current (ma) Q.6(b) Compare BJT and JFET [6] [Any Six points 1 mark each] BJT JFET 1. BJT is a bipolar device, both majority and minority carriers take place in electrical conduction 2. BJT is current operated device, it is a current controlled current source 3. BJT has high g m and hence provides large gain. 4. BJT has low input resistance ( k) input junction is forward biased. 5. Thermal runaway is possible in BJT. I C increases when temperature increases. 6. BJT can be operated with low values of supply voltage (3 10) JFET is an unipolar device, electron current in Nchannel and hole current in Pchannel. JFET is voltage operated device, it is a voltage controlled current source. JFET has low g m and hence provides low gain. JFET has high input resistance (M) input junction is reverse biased. Thermal runaway is not possible in JFET. I D decreases when temperature increases. JFET requires large supply voltage (>10). 7. BJT is noisy in operation. JFET is less noisy in operation. 8. equires large area while fabrication of IC s. 9. Less susceptible to damage while handling. 10. ery complex biasing circuits required to provide stability. 11. Cannot be used as a voltage variable resistance. equires less area while fabrication of IC s. More susceptible to damage while handling. Biasing circuits are less complex when compared to that of BJT. It can be used as a voltage variable resistance. Q.6(c) Sketch the energy band diagram for insulators, conductors and semiconductors. [6] (i) Energy band diagram for Insulator

13 Prelim Question Paper Solution (ii) Energy band diagram for Conductors. (iii) Energy band diagram for semiconductors. [3 mark] The semiconducting materials have conduction and valence bands separates by small energy gap (1 e). In conductors conduction bands and valence bands overlap each other. The overlapping indicates a large number of electrons available for conduction. In insulator the conduction and valence bands are separated by a wide energy gap ( 15 e)

SUMMER 13 EXAMINATION Subject Code: Model Answer Page No: / N

SUMMER 13 EXAMINATION Subject Code: Model Answer Page No: / N Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate