IPS024G QUAD FULLY PROTECTED POWER MOSFET SWITCH

Transcription

1 Data Sheet No.PD6 IPSG QUAD FULLY PROTECTED POWER MOSFET SWITCH Features Over temperature shutdown Over current shutdown Active clamp Low current & logic level input E.S.D protection Description The IPSG are fully protected quad low side SMART POWER MOSFETs respectively. They feature overcurrent, over-temperature, ESD protection and drain to source active clamp.these devices combine a HEXFET POWER MOSFET and a gate driver. They offer full protection and high reliability required in harsh environments. The driver allows short switching times and provides efficient protection by turning OFF the power MOSFET when the temperature exceeds 65 o C or when the drain current reaches 5A. These devices restart once the input is cycled. The avalanche capability is significantly enhanced by the active clamp and covers most inductive load demagnetizations. Product Summary R ds(on) V clamp Package I shutdown T on/ T off 5mΩ (max) 5V 6A.5µs 6-Lead SOIC IPSG (Quad) Typical Connection Load R in series (if needed) IN control ƒ D S Logic signal (Refer to lead assignment for correct pin configuration)

2 Absolute Maximum Ratings Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are referenced to SOURCE lead. (TAmbient = 5 o C unless otherwise specified). PCB mounting uses the standard footprint with 7 µm copper thickness. Symbol Parameter Min. Max. Units Test Conditions V ds Maximum drain to source voltage 7 V in Maximum input voltage Iin, max Maximum IN current - + ma Isd cont. Diode max. continuous current () ( lsd mosfets, rth=5 o C/W).3 Isd pulsed Diode max. pulsed current () (for ea. mosfet) Pd Maximum power dissipation () ( Pd mosfets, rth=5 o C/W) W ESD Electrostatic discharge voltage (Human Body) kv C=pF, R=5Ω, ESD Electrostatic discharge voltage (Machine Model).5 C=pF, R=Ω, L=µH T stor. Max. storage temperature Tj max. Max. junction temperature - +5 V A o C Thermal Characteristics Symbol Parameter Min. Typ. Max. Units Test Conditions Rth Thermal resistance with standard footprint ( mos on) ( mosfets on) 75 Rth Thermal resistance with standard footprint (mos on) ( mosfet on) o C/W Rth3 Thermal resistance with " square footprint ( mos on) ( mosfets on) 6 () Limited by junction temperature (pulsed current limited also by internal wiring)

3 Recommended Operating Conditions These values are given for a quick design. For operation outside these conditions, please consult the application notes. Symbol Parameter Min. Max. Units Vds (max) Continuous drain to source voltage 35 VIH High level input voltage 6 V VIL Low level input voltage.5 Ids Continuous drain current (TAmbient = 85 o C, IN = 5V, rth = o C/W, Tj = 5 o C).7 A Rin Recommended resistor in series with IN pin.5 5 kω Tr-in (max) Max recommended rise time for IN signal (see fig. ) µs Fr-Isc () Max. frequency in short circuit condition (Vcc = V) khz Static Electrical Characteristics Standard footprint 7 µm copper thickness. (Tj = 5 o C unless otherwise specified.) Symbol Parameter Min. Typ. Max. Units Test Conditions Rds(on) ON state resistance Tj = 5 o C 35 6 Tj = 5 o C 35 9 mω Vin = 5V, Ids = A Idss Drain to source leakage current. 5 Vcc = V, Tj = 5 o C µa Idss Drain to source leakage current. 5 Vcc = V, Tj = 5 o C V clamp Drain to source clamp voltage Id = ma (see Fig.3 & ) V clamp Drain to source clamp voltage Vin clamp IN to source clamp voltage V Iin = ma Vth IN threshold voltage.5 Id = 5mA, V ds = V Iin, -on ON state IN positive current 5 9 Vin = 5V Iin, -off OFF state IN positive current µa Vin = 5V over-current triggered Id=Ishutdown (see Fig.3 & ) Switching Electrical Characteristics Vcc = V, Resistive Load = Ω, Rinput = 5Ω, µs pulse, T j = 5 o C, (unless otherwise specified). Symbol Parameter Min. Typ. Max. Units Test Conditions Ton Turn-on delay time.5.5 Tr Rise time..9 See figure Trf Time to 3% final Rds(on) 6 µs Toff Turn-off delay time See figure Tf Fall time Qin Total gate charge 3.3 nc Vin = 5V () Operations at higher switching frequencies is possible. See Appl. notes. 3

4 Protection Characteristics Symbol Parameter Min. Typ. Max. Units Test Conditions Tsd Over temperature threshold 65 o C See fig. Isd Over current threshold 6 8 A See fig. V reset IN protection reset threshold V Treset Time to reset protection µs Vin = V, Tj = 5 o C EOI_OT Short circuit energy (see application note) µj Vcc = V Functional Block Diagram All values are typical DRAIN 7 V Ω k Ω IN S Q 8. V 8 µ A R Q T > 65 c I sense I > Isd SOURCE Lead Assignments D D D D D3 D3 D D S I S I S3 I3 S I 6 Lead SOIC (Quad) IPSG Part Number

5 Vin 5 V Ids Isd V I shutdown t < T reset t > T reset Vin Ids 9 % % Tr-in 9 % % T Tsd (65 c) T shutdown Vds Td on tr Td off tf Figure - Timing diagram Figure - IN rise time & switching time definitions T clamp Vin L V load Ids Vds Vds clamp ( Vcc ) Rem : V load is negative during demagnetization 5 v v Vin IN R D S Vds Ids + V - ( see Appl. Notes to evaluate power dissipation ) Figure 3 - Active clamp waveforms Figure - Active clamp test circuit 5

6 All curves are typical values with standard footprints. Operating in the shaded area is not recommended. 3 5 Tj = 5 o C 5 Tj = 5 o C % 8% 6% % % % 8% 6% % % % Figure 5 - Rds ON (mω) Vs Input Voltage (V) Figure 6 - Normalized Rds(on) (%) Vs Tj ( o C) ton delay rise time 3% rdson toff delay fall time Figure 7 - Turn-ON Delay Time, Rise Time & Time to 3% final Rds(on) (us) Vs Input Voltage (V) Figure 8 - Turn-OFF Delay Time & Fall Time (us) Vs Input Voltage (V) 6

7 delay on rise time 3% rdson delay off fall time. Figure 9 - Turn-ON Delay Time, Rise Time & Time to 3% final Rds(on) (us) Vs IN Resistor (Ω). Figure - Turn-OFF Delay Time & Fall Time (us) Vs IN Resistor (Ω) Isd 5 C Ilim 5 C Figure - Current Iim. & I shutdown (A) Vs Vin (V) Figure - I shutdown (A) Vs Temperature ( o C) 7

8 5 3 Std. footprint 75 C/W o o mosfet mofet on on mosfet on Std. footprint C/W o mosfet on mosfets on T=5 C Std. footprint T= C Std footprint Current path capability should be above this curve Load characteristic should be below this curve Figure 3 - Max.Cont. Ids (A) Vs Amb. Temperature ( o C) - IPSG Figure - Ids (A) Vs Protection Resp. Time (s) single pulse Hz rth= C/W dt=5 C khz rth= C/W dt=5 C. Vbat = V Tjini = T sd for single pulse all curves for mosfet active.... Single pulse rth mosfet on rth mofets on Figure 5 - Max. Iclamp (A) Vs Inductive Load (mh) Figure 6 - Transient Thermal Imped. ( o C/W) Vs Time (s) 8

9 Iin,on Iin,off Treset rise time fall time Figure 7 - Input Current (ua) Vs Junction Temperature ( o C) Figure 8 - Rise Time, Fall Time and Treset (µs) Vs Tj ( o C) % 5% % 5% % 95% 9% Vds Isd 85% Vin ma 8% Figure 9 -Vin clamp and Vds clamp (%) Vs Tj ( o C) 9

10 Case Outline 6 -Lead SOIC (narrow body) (MS-AC) IR WORLD HEADQUARTERS: 33 Kansas St., El Segundo, California 95 Tel: (3) 5-75 Data and specifications subject to change without notice. /6/