2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs

Transcription

1 9-2442; Rev 4; 5/09 EVLUTION KIT VILBLE 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/2-Channel 2-Wire erial -Bit DCs General Description The MX036 MX039 low-power, -bit, multichannel, analog-to-digital converters (DCs) feature internal track/hold (T/H), voltage reference, clock, and an I 2 C-compatible 2-wire serial interface. These devices operate from a single supply and require only 350µ at the maximum sampling rate of ksps. uto- hutdown powers down the devices between conversions reducing supply current to less than µ at low throughput rates. The MX036/MX037 have four analog input channels each, while the MX03/MX039 have twelve analog input channels. The analog inputs are software configurable for unipolar or bipolar and singleended or pseudo-differential operation. The full-scale analog input range is determined by the internal reference or by an externally applied reference voltage ranging from V to V DD. The MX037/ MX039 feature a 2.04V internal reference and the MX036/MX03 feature a 4.096V internal reference. The MX036/MX037 are available in -pin OT23 packages. The MX03/MX039 are available in 6- pin QOP packages. The MX036 MX039 are guaranteed over the extended industrial temperature range (-40 C to +5 C). Refer to MX36 MX39 for 0-bit devices and to the MX236 MX239 for 2-bit devices. Handheld Portable pplications Medical Instruments Battery-Powered Test Equipment olar-powered Remote ystems Received-ignal-trength Indicators ystem upervision pplications Features High-peed I 2 C-Compatible erial Interface 400kHz Fast Mode.7MHz High-peed Mode ingle upply 2.7V to 3.6V (MX037/MX039) 4.5V to 5.5V (MX036/MX03) Internal Reference 2.04V (MX037/MX039) 4.096V (MX036/MX03) External Reference: V to V DD Internal Clock 4-Channel ingle-ended or 2-Channel Pseudo- Differential (MX036/MX037) 2-Channel ingle-ended or 6-Channel Pseudo- Differential (MX03/MX039) Internal FIFO with Channel-can Mode Low Power 350µ at ksps 0µ at 75ksps µ at 0ksps µ in Power-Down Mode oftware Configurable Unipolar/Bipolar mall Packages -Pin OT23 (MX036/MX037) 6-Pin QOP (MX03/MX039) Pin Configurations and Typical Operating Circuit appear at end of data sheet. Ordering Information/elector Guide MX036 MX039 PRT PIN-PCKGE TUE (LB) INPUT CHNNEL I 2 C LVE DDRE INTERNL REFERENCE (V) TOP MRK MX036EK+T OT23 ± JE MX037EK+T OT23 ± JG MX03EEE+ 6 QOP ± MX039EEE+ 6 QOP ± Denotes a lead(pb)-free/roh-compliant package. T = Tape and reel. utohutdown is a trademark of Maxim Integrated Products, Inc. Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim's website at

2 4-/2-Channel 2-Wire erial -Bit DCs MX036 MX039 BOLUTE MXIMUM RTING V DD to GND V to +6V IN0 IN, REF to GND V to the lower of (V DD + 0.3V) and +6V D, CL to GND V to +6V Maximum Current Into ny Pin...±50m Continuous Power Dissipation (T = +70 C) -Pin OT23 (derate 7.mW/ C above +70 C)...567mW 6-Pin QOP (derate.3mw/ C above +70 C) mW ELECTRICL CHRCTERITIC Operating Temperature Range C to +5 C Junction Temperature C torage Temperature Range C to +50 C Lead Temperature (soldering, 0s) C tresses beyond those listed under bsolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (V DD = 2.7V to 3.6V (MX037/MX039), V DD = 4.5V to 5.5V (MX036/MX03). External reference, V REF = 2.04V (MX037/MX039), V REF = 4.096V (MX036/MX03). External clock, f CL =.7MHz, T = T MIN to T MX, unless otherwise noted. Typical values are at T = +25 C.) PRMETER YMBOL CONDITION MIN TYP MX UNIT DC CCURCY (Note ) Resolution Bits Relative ccuracy INL (Note 2) ± LB Differential Nonlinearity DNL No missing codes over temperature ± LB Offset Error ±.5 LB Offset Error Temperature Coefficient 3 ppm/ C Gain Error (Note 3) ± LB Gain Temperature Coefficient ± ppm/ C Total Unadjusted Error Channel-to-Channel Offset Matching TUE MX036/MX037 ±0.5 ±2 MX03/MX039 ±0.5 ± LB ±0. LB Channel-to-Channel Gain Matching Input Common-Mode Rejection Ratio ±0.5 LB CMRR Pseudo-differential input mode 75 db DYNMIC PERFORMNCE (f IN(sine wave) = 25kHz, V IN = V REF(P-P), f MPLE = ksps, R IN = 00Ω) ignal-to-noise Plus Distortion IND 49 db Total Harmonic Distortion THD Up to the 5th harmonic -69 db purious-free Dynamic Range FDR 69 db Channel-to-Channel Crosstalk (Note 4) 75 db Full-Power Bandwidth -3dB point 2.0 MHz Full-Linear Bandwidth IND > 49dB 200 khz CONVERION RTE Internal clock 6. Conversion Time (Note 5) t CONV External clock 4.7 µs 2

3 4-/2-Channel 2-Wire erial -Bit DCs ELECTRICL CHRCTERITIC (continued) (V DD = 2.7V to 3.6V (MX037/MX039), V DD = 4.5V to 5.5V (MX036/MX03). External reference, V REF = 2.04V (MX037/MX039), V REF = 4.096V (MX036/MX03). External clock, f CL =.7MHz, T = T MIN to T MX, unless otherwise noted. Typical values are at T = +25 C.) Throughput Rate PRMETER YMBOL CONDITION MIN TYP MX UNIT f MPLE Internal clock, CN[:0] = 0 (MX036/MX037) Internal clock, CN[:0] = 00 C[3:0] = 0 (MX03/MX039) External clock Track/Hold cquisition Time 5 ns Internal Clock Frequency 2.25 MHz External clock, fast mode 45 perture Delay t D External clock, high-speed mode 30 NLOG INPUT (IN0 IN) Input Voltage Range, ingle Unipolar 0 V REF Ended and Differential (Note 6) Bipolar ±V REF / ksps ns V MX036 MX039 Input Multiplexer Leakage Current On/off-leakage current, V IN _= 0 or V DD, no clock, f CL = 0 ±0.0 ± µ Input Capacitance C IN pf INTERNL REFERENCE (Note 7) Reference Voltage V REF T = +25 C Reference Temperature Coefficient MX037/MX MX036/MX TC REF 20 ppm/ C Reference hort-circuit Current 0 m Reference ource Impedance (Note ) 675 Ω EXTERNL REFERENCE Reference Input Voltage Range V REF (Note 9).0 V DD V REF Input Current I REF f MPLE = ksps 4 30 µ DIGITL INPUT/OUTPUT (CL, D) Input High Voltage V IH 0.7 x V DD V Input Low Voltage V IL 0.3 x V DD V Input Hysteresis V HYT 0. x V DD V Input Current I IN V IN = 0 to V DD ±0 µ Input Capacitance C IN 5 pf Output Low Voltage V OL I INK = 3m 0.4 V V 3

4 4-/2-Channel 2-Wire erial -Bit DCs MX036 MX039 ELECTRICL CHRCTERITIC (continued) (V DD = 2.7V to 3.6V (MX037/MX039), V DD = 4.5V to 5.5V (MX036/MX03). External reference, V REF = 2.04V (MX037/MX039), V REF = 4.096V (MX036/MX03). External clock, f CL =.7MHz, T = T MIN to T MX, unless otherwise noted. Typical values are at T = +25 C.) PRMETER YMBOL CONDITION MIN TYP MX UNIT POWER REQUIREMENT MX037/MX upply Voltage (Note 0) V DD MX036/MX upply Current I DD f MPLE = Internal REF, external clock ksps External REF, external clock 250 f MPLE = External REF, external clock 0 75ksps External REF, internal clock 50 f MPLE = External REF, external clock 0ksps External REF, internal clock 0 f MPLE = External REF, external clock 2 ksps External REF, internal clock 2.5 Power-down 0 Power-upply Rejection Ratio PRR (Note ) ±0.25 ± LB/V TIMING CHRCTERITIC FOR 2-WIRE FT MODE (Figures and 2) erial Clock Frequency f CL 400 khz Bus Free Time Between a TOP and a TRT Condition t BUF.3 µs Hold Time for tart Condition t HD, T 0.6 µs Low Period of the CL Clock t LOW.3 µs High Period of the CL Clock t HIGH 0.6 µs etup Time for a Repeated TRT Condition (r) t U, T 0.6 µs Data Hold Time t HD, DT (Note 2) 0 50 ns Data etup Time t U, DT 00 ns Rise Time of Both D and CL ignals, Receiving t R (Note 3) C B 300 ns Fall Time of D Transmitting t F (Note 3) C B 300 ns etup Time for TOP Condition t U, TO 0.6 µs Capacitive Load for Each Bus Line C B 400 pf Pulse Width of pike uppressed t P 50 ns TIMING CHRCTERITIC FOR 2-WIRE HIGH-PEED MODE (Figures B and 2) erial Clock Frequency f CLH (Note 4).7 MHz Hold Time (Repeated) tart Condition t HD, T 60 ns Low Period of the CL Clock t LOW 320 ns High Period of the CL Clock t HIGH 20 ns V µ 4

5 4-/2-Channel 2-Wire erial -Bit DCs ELECTRICL CHRCTERITIC (continued) (V DD = 2.7V to 3.6V (MX037/MX039), V DD = 4.5V to 5.5V (MX036/MX03). External reference, V REF = 2.04V (MX037/MX039), V REF = 4.096V (MX036/MX03). External clock, f CL =.7MHz, T = T MIN to T MX, unless otherwise noted. Typical values are at T = +25 C.) PRMETER YMBOL CONDITION MIN TYP MX UNIT etup Time for a Repeated TRT Condition (r) t U, T 60 ns Data Hold Time t HD, DT (Note 2) 0 50 ns Data etup Time t U, DT 0 ns Rise Time of CL ignal (Current ource Enabled) Rise Time of CL ignal fter cknowledge Bit t RCL (Note 3) 20 0 ns t RCL (Note 3) ns Fall Time of CL ignal t FCL (Note 3) 20 0 ns Rise Time of D ignal t RD (Note 3) ns Fall Time of D ignal t FD (Note 3) ns etup Time for TOP Condition t U, TO 60 ns Capacitive Load for Each Bus Line C B 400 pf Pulse Width of pike uppressed t P 0 0 ns MX036 MX039 Note : The MX036/MX03 are tested at V DD = 5V and the MX037/MX039 are tested at V DD = 3V. ll devices are configured for unipolar, single-ended inputs. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offsets have been calibrated. Note 3: Offset nulled. Note 4: Ground on channel; sine wave applied to all off channels. Note 5: Conversion time is defined as the number of clock cycles () multiplied by the clock period. Conversion time does not include acquisition time. CL is the conversion clock in the external clock mode. Note 6: The absolute voltage range for the analog inputs (IN0 IN) is from GND to V DD. Note 7: When IN_/REF is configured to be an internal reference (EL[2:] = ), decouple IN_/REF to GND with a 0.0µF capacitor. Note : The switch connecting the reference buffer to IN_/REF has a typical on-resistance of 675Ω. Note 9: DC performance is limited by the converter s noise floor, typically.4mv P-P. Note 0: Electrical characteristics are guaranteed from V DD(min) to V DD(max). For operation beyond this range, see the Typical Operating Characteristics. Note : Power-supply rejection ratio is measured as: N 2 [ VF( 33. V) VF( 27. V) ] VREF 33. V 27. V, for the MX037/MX039 where N is the number of bits and V REF = 2.04V. Power-supply rejection ratio is measured as: N 2 [ VF( 55. V) VF( 45. V) ] VREF 55. V 45. V, for the MX036/MX03 where N is the number of bits and V REF = 4.096V. Note 2: master device must provide a data hold time for D (referred to V IL of CL) in order to bridge the undefined region of CL s falling edge (Figure ). Note 3: C B = total capacitance of one bus line in pf. t R, t FD, and t F measured between 0.3V DD and 0.7V DD. The minimum value is specified at +25 C with C B = 400pF. Note 4: f CLH must meet the minimum clock low time plus the rise/fall times. 5

6 4-/2-Channel 2-Wire erial -Bit DCs MX036 MX039 Typical Operating Characteristics (V DD = 3.3V (MX037/MX039), V DD = 5V (MX036/MX03), f CL =.7MHz, external clock (33% duty cycle), f MPLE = ksps, single ended, unipolar, T = +25 C, unless otherwise noted.) IDD (µ) UPPLY CURRENT vs. VOLTGE ) INTERNL 4.096V REF B) INTERNL 2.04V REF C) EXTERNL 4.096V REF D) EXTERNL 2.04V REF V DD (V) B C D MX036 toc0 IDD (µ) UPPLY CURRENT vs. TEMPERTURE INTERNL 4.096V REF INTERNL 2.04V REF EXTERNL 4.096V REF EXTERNL 2.04V REF TEMPERTURE ( C) MX036 toc02 IDD (µ) HUTDOWN UPPLY CURRENT vs. UPPLY VOLTGE D = CL = V DD V DD (V) MX036 toc03 IDD (µ) HUTDOWN UPPLY CURRENT vs. TEMPERTURE D = CL = V DD V DD = 5V V DD = 3.3V TEMPERTURE ( C) MX036 toc04 VERGE IDD (µ) VERGE UPPLY CURRENT vs. CONVERION RTE (INTERNL CLOCK) ) INTERNL REF LWY ON B) INTERNL REF UTOHUTDOWN C) EXTERNL REF CONVERION RTE (ksps) B C INTERNL CLOCK MODE f CL =.7MHz MX036 toc05 VERGE IDD (µ) VERGE UPPLY CURRENT V. CONVERION RTE (EXTERNL CLOCK) ) INTERNL REF LWY ON B) INTERNL REF UTOHUTDOWN C) EXTERNL REF B C EXTERNL CLOCK MODE f CL =.7MHz CONVERION RTE (ksps) MX036 toc06 NORMLIZED 4.096V REFERENCE VOLTGE vs. UPPLY VOLTGE MX036 toc INTERNL 4.096V REFERENCE VOLTGE vs. TEMPERTURE MX036 toc INTERNL 2.04V REFERENCE VOLTGE vs. UPPLY VOLTGE MX036 toc09 VREF NORMLIZED VREF NORMLIZED VREF NORMLIZED V DD (V) TEMPERTURE ( C) V DD (V) 6

7 4-/2-Channel 2-Wire erial -Bit DCs Typical Operating Characteristics (continued) (V DD = 3.3V (MX037/MX039), V DD = 5V (MX036/MX03), f CL =.7MHz, external clock (33% duty cycle), f MPLE = ksps, single ended, unipolar, T = +25 C, unless otherwise noted.) VREF NORMLIZED INTERNL 2.04V REFERENCE VOLTGE vs. TEMPERTURE TEMPERTURE ( C) MX036 toc0 DNL (LB) DIFFERENTIL NONLINERITY vs. DIGITL CODE DIGITL OUTPUT CODE MX036 toc INL (LB) INTEGRL NONLINERITY vs. DIGITL CODE DIGITL OUTPUT CODE MX036 toc2 MX036 MX FFT PLOT f MPLE = ksps f IN = 25kHz MX036 toc OFFET ERROR vs. UPPLY VOLTGE V REF = 2.04V MX036 toc4 MPLITUDE (dbc) OFFET ERROR (LB) k 40k 60k 0k 00k FREQUENCY (Hz) V DD (V) OFFET ERROR (LB) OFFET ERROR vs. TEMPERTURE V DD = 3.3V V REF = 2.04V TEMPERTURE ( C) MX036 toc5 GIN ERROR (LB) GIN ERROR vs. UPPLY VOLTGE V REF = 2.04V V DD (V) MX036 toc6 7

8 4-/2-Channel 2-Wire erial -Bit DCs MX036 MX039 MX036/ MX037 PIN MX03/ MX039 NME, 2, 3, 7, 6 IN0 IN2 5, 4, 3, 2, IN3 IN7 6, 5, 4 IN IN0 4 IN3/REF nalog Inputs FUNCTION Pin Description nalog Input 3/Reference Input or Output. elected in the setup register. 3 IN/REF nalog Input /Reference Input or Output. elected in the setup register. 5 9 CL Clock Input 6 0 D Data Input/Output 7 GND Ground 2 V DD Positive upply. Bypass to GND with a 0.µF capacitor. Detailed Description The MX036 MX039 DCs use successiveapproximation conversion techniques and input T/H circuitry to capture and convert an analog signal to a serial -bit digital output. The MX036/MX037 are 4-channel DCs, and the MX03/MX039 are 2- channel DCs. These devices feature a high-speed 2- wire serial interface supporting data rates up to.7mhz. Figure 3 shows the simplified functional diagram for the MX03/MX039. Power upply The MX036 MX039 operate from a single supply and consume 350µ at sampling rates up to ksps. The MX037/MX039 feature a 2.04V internal reference and the MX036/MX03 feature a 4.096V internal reference. ll devices can be configured for use with an external reference from V to V DD. nalog Input and Track/Hold The MX036 MX039 analog input architecture contains an analog input multiplexer (MUX), a T/H capacitor, T/H switches, a comparator, and a switched capacitor digital-to-analog converter (DC) (Figure 4). In single-ended mode, the analog input multiplexer connects C T/H to the analog input selected by C[3:0] (see the Configuration/etup Bytes (Write Cycle) section). The charge on C T/H is referenced to GND when converted. In pseudo-differential mode, the analog input multiplexer connects C T/H to the + analog input selected by C[3:0]. The charge on C T/H is referenced to the - analog input when converted. The MX036 MX039 input configuration is pseudodifferential in that only the signal at the + analog input is sampled with the T/H circuitry. The - analog input signal must remain stable within ±0.5LB (±0.LB for best results) with respect to GND during a conversion. To accomplish this, connect a 0.µF capacitor from - analog input to GND. ee the ingle-ended/pseudo- Differential Input section. During the acquisition interval, the T/H switches are in the track position and C T/H charges to the analog input signal. t the end of the acquisition interval, the T/H switches move to the hold position retaining the charge on C T/H as a sample of the input signal. During the conversion interval, the switched capacitive DC adjusts to restore the comparator input voltage to zero within the limits of -bit resolution. This action requires eight conversion clock cycles and is equivalent to transferring a charge of pf (V IN + - V IN -) from C T/H to the binary weighted capacitive DC forming a digital representation of the analog input signal. ufficiently low source impedance is required to ensure an accurate sample. source impedance below.5kω does not significantly degrade sampling accuracy. To minimize sampling errors with higher source impedances, connect a 00pF capacitor from the analog input to GND. This input capacitor forms an RC filter with the source impedance limiting the analog input bandwidth. For larger source impedances, use a buffer amplifier to maintain analog input signal integrity. When operating in internal clock mode, the T/H circuitry enters its tracking mode on the ninth falling clock edge

9 4-/2-Channel 2-Wire erial -Bit DCs. F/-MODE I 2 C ERIL INTERFCE TIMING D t U.DT t HD.DT thd.t t LOW t U.T CL t HD.T t HIGH t R t F r B. H-MODE I 2 C ERIL INTERFCE TIMING D t LOW t U.DT t HD.DT t U.T t HD.T t U.TO t U.TO t RD t R P t BUF t BUF t F t t FD MX036 MX039 CL t HD.T t HIGH t RCL t FCL t RCL r H-MODE F/-MODE Figure. I 2 C erial Interface Timing of the address byte (see the lave ddress section). The T/H circuitry enters hold mode two internal clock cycles later. conversion or series of conversions are then internally clocked (eight clock cycles per conversion) and the MX036 MX039 hold CL low. When operating in external clock mode, the T/H circuitry enters track mode on the seventh falling edge of a valid slave address byte. Hold mode is then entered on the falling edge of the eighth clock cycle. The conversion is performed during the next eight clock cycles. The time required for the T/H circuitry to acquire an input signal is a function of input capacitance. If the analog input source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. The acquisition time (t CQ ) is the minimum time needed for the signal to be acquired. It is calculated by: t CQ 6.25 (R OURCE + R IN ) C IN where R OURCE is the analog input source impedance, R IN = 2.5kΩ, and C IN = pf. t CQ is /f CL for external D Figure 2. Load Circuit V DD I OL = 3m I OH = 0m V OUT 400pF clock mode. For internal clock mode, the acquisition time is two internal clock cycles. To select R OURCE, allow 625ns for t CQ in internal clock mode to account for clock frequency variations. 9

10 4-/2-Channel 2-Wire erial -Bit DCs MX036 MX039 D CL V DD GND IN0 IN IN2 IN3 IN4 IN5 IN6 IN7 IN IN9 IN0 INPUT HIFT REGITER NLOG INPUT MUX ETUP REGITER CONFIGURTION REGITER T/H REF -BIT DC REFERENCE 4.096V (MX03) 2.04V (MX039) CONTROL LOGIC INTERNL OCILLTOR OUTPUT HIFT REGITER ND 2-BYTE RM MX03 MX039 IN/REF Figure 3. MX03/MX039 implified Functional Diagram NLOG INPUT MUX REF C T/H IN0 IN TRCK HOLD CPCITIVE DC TRCK HOLD IN2 IN3/REF DIFFERENTIL INGLE ENDED GND MX036 MX037 Figure 4. Equivalent Input Circuit nalog Input Bandwidth The MX036 MX039 feature input tracking circuitry with a 2MHz small signal-bandwidth. The 2MHz input bandwidth makes it possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the DC s sampling rate by using undersampling techniques. To avoid high frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. nalog Input Range and Protection Internal protection diodes clamp the analog input to V DD and GND. These diodes allow the analog inputs to swing from (GND - 0.3V) to (V DD + 0.3V) without causing damage to the device. For accurate conversions, the inputs must not go more than 50mV below GND or above V DD. If the analog input exceeds V DD by more than 50mV, the input current should be limited to 2m. 0

11 4-/2-Channel 2-Wire erial -Bit DCs Table. etup Byte Format BIT 7 (MB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT REG EL2 EL EL0 CLK BIP/UNI RT X BIT NME DECRIPTION 7 REG Register bit. = etup Byte, 0 = Configuration Byte (Table 2). 6 EL2 Three bits select the reference voltage and the state of IN_/REF (Table 6). Default to 000 at 5 EL power-up. 4 EL0 3 CLK = External clock, 0 = Internal clock. Defaulted to zero at power-up. 2 BIP/UNI = Bipolar, 0 = Unipolar. Defaulted to zero at power-up (see the Unipolar/Bipolar section). RT = No action, 0 = Resets the configuration register to default. etup register remains unchanged. 0 X Don t care, can be set to or 0. BIT 0 (LB) MX036 MX039 ingle-ended/pseudo-differential Input The GL/DIF bit of the configuration byte configures the MX036 MX039 analog input circuitry for singleended or pseudo-differential inputs (Table 2). In singleended mode (GL/DIF = ), the digital conversion results are the difference between the analog input selected by C[3:0] and GND (Table 3). In pseudo-differential mode (GL/DIF = 0), the digital conversion results are the difference between the + and the - analog inputs selected by C[3:0] (Table 4). The - analog input signal must remain stable within ±0.5LB (±0.LB for best results) with respect to GND during a conversion. Unipolar/Bipolar When operating in pseudo-differential mode, the BIP/ UNI bit of the setup byte (Table ) selects unipolar or bipolar operation. Unipolar mode sets the differential analog input range from zero to V REF. negative differential analog input in unipolar mode causes the digital output code to be zero. electing bipolar mode sets the differential input range to ±V REF /2, with respect to the negative input. The digital output code is binary in unipolar mode and two s complement binary in bipolar mode (see the Transfer Functions section). In single-ended mode, the MX036 MX039 always operate in unipolar mode regardless of the BIP/UNI setting, and the analog inputs are internally referenced to GND with a full-scale input range from zero to V REF. Digital Interface The MX036 MX039 feature a 2-wire interface consisting of a serial data line (D) and a serial clock line (CL). D and CL facilitate bidirectional communication between the MX036 MX039 and the master at rates up to.7mhz. The MX036 MX039 are slaves that transmit and receive data. The master (typically a microcontroller) initiates data transfer on the bus and generates CL to permit that transfer. D and CL must be pulled high. This is typically done with pullup resistors (500Ω or greater) (see Typical Operating Circuit). eries resistors (R ) are optional. They protect the input architecture of the MX036 MX039 from high-voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each CL clock cycle. Nine clock cycles are required to transfer the data in or out of the MX036 MX039. The data on D must remain stable during the high period of the CL clock pulse. Changes in D while CL is high are control signals (see the TRT and TOP Conditions section). Both D and CL idle high when the bus is not busy. TRT and TOP Conditions The master initiates a transmission with a TRT condition (), a high-to-low transition on D with CL high. The master terminates a transmission with a TOP condition (P), a low-to-high transition on D, while

12 4-/2-Channel 2-Wire erial -Bit DCs MX036 MX039 CL is high (Figure 5). repeated TRT condition (r) can be used in place of a TOP condition to leave the bus active and in its current timing mode (see the H- Mode section). cknowledge Bits uccessful data transfers are acknowledged with an acknowledge bit () or a not-acknowledge bit (). Both the master and the MX036 MX039 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull D low before the rising edge of the acknowledge related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (Figure 6). To generate a not acknowledge, the receiver allows D to be pulled high before the rising edge of the acknowledge related clock pulse and leaves it high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. n unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. lave ddress bus master initiates communication with a slave device by issuing a TRT condition followed by a slave address. When idle, the MX036 MX039 continuously wait for a TRT condition followed by their slave address. When the MX036 MX039 recognize their slave address, they are ready to accept or send data. The slave address has been factory programmed and is always 0000 for the MX036/ MX037, and 000 for MX03/ MX039 (Figure 7). The least significant bit (LB) of the address byte (R/W) determines whether the master is writing to or reading from the MX036 MX039 (R/W = zero selects a write condition. R/W = selects a read condition). fter receiving the address, the MX036 MX039 (slave) issue an acknowledge by pulling D low for one clock cycle. Bus Timing t power-up, the MX036 MX039 bus timing defaults to fast mode (F/-mode) allowing conversion rates up to 44ksps. The MX036 MX039 must operate in high-speed mode (H-mode) to achieve conversion rates up to ksps. Figure shows the bus timing for the MX036 MX039 s 2-wire interface. H-Mode t power-up, the MX036 MX039 bus timing is set for F/-mode. The master selects H-mode by addressing all devices on the bus with the H-mode master D CL Figure 5. TRT and TOP Conditions D CL Figure 6. cknowledge Bits r NOT CKNOWLEDGE CKNOWLEDGE 2 9 code 0000 XXX (X = Don t care). fter successfully receiving the H-mode master code, the MX036 MX039 issues a not acknowledge, allowing D to be pulled high for one clock cycle (Figure ). fter the not acknowledge, the MX036 MX039 are in H-mode. The master must then send a repeated TRT followed by a slave address to initiate H-mode communication. If the master generates a TOP condition, the MX036 MX039 return to F/-mode. Configuration/etup Bytes (Write Cycle) Write cycles begin with the master issuing a TRT condition followed by 7 address bits (Figure 7) and write bit (R/W = zero). If the address byte is successfully received, the MX036 MX039 (slave) issue an acknowledge. The master then writes to the slave. The slave recognizes the received byte as the setup byte (Table ) if the most significant bit (MB) is. If the MB is zero, the slave recognizes that byte as the configuration byte (Table 2). The master can write either or 2 bytes to the slave in any order (setup byte then configuration byte; configuration byte then setup byte; setup byte only; configuration byte only; Figure 9). If the slave receives bytes successfully, it issues an acknowledge. The master ends the write cycle by issuing a TOP condition or a repeated TRT condition. When operating in H-mode, a TOP condition returns the bus to F/-mode (see the H-Mode section). Data Byte (Read Cycle) read cycle must be initiated to obtain conversion results. Read cycles begin with the bus master issuing P 2

13 4-/2-Channel 2-Wire erial -Bit DCs D CL DEVICE MX036/MX037 MX03/MX039 LVE DDRE Figure 7. MX036/MX037 lave ddress Byte LVE DDRE R/W MX036 MX039 H-MODE MTER CODE X X X r D CL F/-MODE H-MODE Figure. F/-Mode to H-Mode Transfer a TRT condition followed by 7 address bits and a read bit (R/W = ). If the address byte is successfully received, the MX036 MX039 (slave) issue an acknowledge. The master then reads from the slave. fter the master has received the results, it can issue an acknowledge if it wants to continue reading or a not acknowledge if it no longer wishes to read. If the MX036 MX039 receive a not acknowledge, they release D allowing the master to generate a TOP or repeated TRT. ee the Clock Mode and can Mode sections for detailed information on how data is obtained and converted. Clock Mode The clock mode determines the conversion clock, the acquisition time, and the conversion time. The clock mode also affects the scan mode. The state of the setup byte s CLK bit determines the clock mode (Table ). t power-up, the MX036 MX039 default to internal clock mode (CLK = zero). Internal Clock When configured for internal clock mode (CLK = zero), the MX036 MX039 use their internal oscillator as the conversion clock. In internal clock mode, the MX036 MX039 begin tracking analog input on the ninth falling clock edge of a valid slave address byte. Two internal clock cycles later, the analog signal is acquired and the conversion begins. While tracking and converting the analog input signal, the MX036 MX039 hold CL low (clock stretching). fter the conversion completes, the results are stored 3

14 4-/2-Channel 2-Wire erial -Bit DCs MX036 MX039 MTER TO LVE LVE TO MTER. -BYTE WRITE CYCLE LVE DDRE B. 2-BYTE WRITE CYCLE 7 W ETUP OR CONFIGURTION BYTE MB DETERMINE WHETHER ETUP OR CONFIGURTION BYTE 7 LVE DDRE W ETUP OR CONFIGURTION BYTE P OR r ETUP OR CONFIGURTION BYTE NUMBER OF BIT P OR r NUMBER OF BIT MB DETERMINE WHETHER ETUP OR CONFIGURTION BYTE Figure 9. Write Cycle in random access memory (RM). If the scan mode is set for multiple conversions, they all happen in succession with each additional result being stored in RM. The MX036/MX037 contain bytes of RM, and the MX03/MX039 contain 2 bytes of RM. Once all conversions are complete, the MX036 MX039 release CL, allowing it to be pulled high. The master can now clock the results out of the output shift register at a clock rate of up to.7mhz. CL is stretched for a maximum acquisition and conversion time of 7.6µs per channel (Figure 0). The device RM contains all of the conversion results when the MX036 MX039 release CL. The converted results are read back in a first-in-first-out (FIFO) sequence. If IN_/REF is set to be a reference input or output (EL =, Table 6), IN_/REF is excluded from a multichannel scan. RM contents can be read continuously. If reading continues past the last result stored in RM, the pointer wraps around and points to the first result. Note that only the current conversion results are read from memory. The device must be addressed with a read command to obtain new conversion results. The internal clock mode s clock stretching quiets the CL bus signal, reducing the system noise during conversion. Using the internal clock also frees the master (typically a microcontroller) from the burden of running the conversion clock. External Clock When configured for external clock mode (CLK = ), the MX036 MX039 use CL as the conversion clock. In external clock mode, the MX036 MX039 begin tracking the analog input on the seventh falling clock edge of a valid slave address byte. One CL clock cycle later, the analog signal is acquired and the conversion begins. Unlike internal clock mode, converted data is available immediately after the slave-address acknowledge bit. The device continuously converts input channels dictated by the scan mode until given a not acknowledge. There is no need to readdress the device with a read command to obtain new conversion results (Figure ). The conversion must complete in 9ms or droop on the T/H capacitor degrades conversion results. Use internal clock mode if the CL clock period exceeds ms. The MX036 MX039 must operate in external clock mode for conversion rates up to ksps. can Mode CN0 and CN of the configuration byte set the scan mode configuration. Table 5 shows the scanning configurations. If IN_/REF is set to be a reference input or output (EL =, Table 6), IN_/REF is excluded from a multichannel scan. 4

15 4-/2-Channel 2-Wire erial -Bit DCs Table 2. Configuration Byte Format BIT 7 (MB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT BIT 0 (LB) REG CN CN0 C3 C2 C C0 GL/DIF BIT NME DECRIPTION 7 REG Register bit. = etup Byte (Table ), 0 = Configuration Byte. 6 CN 5 CN0 4 C3 3 C2 2 C C0 0 GL/DIF can select bits. Two bits select the scanning configuration (Table 5). Default to 00 at power-up. Channel select bits. Four bits select which analog input channels are to be used for conversion (Tables 3, 4). Default to 0000 at power-up. For MX036/MX037, C3 and C2 are internally set to 0. = single-ended, 0 = pseudo-differential (Tables 3, 4). Default to at power-up (see the ingle- Ended/Pseudo-Differential Input section). MX036 MX039 pplications Information Power-On Reset The configuration and setup registers (Tables and 2) default to a single-ended, unipolar, single-channel conversion on IN0 using the internal clock with V DD as the reference and IN_/REF configured as an analog input. The RM contents are unknown after power-up. utomatic hutdown EL[2:0] of the setup byte (Tables and 6) controls the state of the reference and IN_/REF. If automatic shutdown is selected (EL[2:0] = 00), shutdown occurs between conversions when the MX036 MX039 are idle. When operating in external clock mode, a TOP condition must be issued to place the devices in idle mode and benefit from automatic shutdown. TOP condition is not necessary in internal clock mode to benefit from automatic shutdown because power-down occurs once all contents are written to memory (Figure 0). ll analog circuitry is inactive in shutdown and supply current is less than µ. The digital conversion results are maintained in RM during shutdown and are available for access through the serial interface at any time prior to a TOP or repeated TRT condition. When idle, the MX036 MX039 wait for a TRT condition followed by their slave address (see the lave ddress section). Upon reading a valid address byte, the MX036 MX039 power up. The analog circuits do not require any wakeup time from shutdown, whether using external or internal reference. utomatic shutdown results in dramatic power savings, particularly at slow conversion rates. For example, at a conversion rate of 0ksps, the average supply current for the MX036 is µ and drops to 2µ at ksps. t 0.ksps the average supply current is just µ (see verage upply Current vs. Conversion Rate in the Typical Operating Characteristics section). Reference Voltage EL[2:0] of the setup byte (Table ) controls the reference and the IN_/REF configuration (Table 6). When IN_/REF is configured to be a reference input or reference output (EL = ), conversions on IN_/REF appear as if IN_/REF is connected to GND (see Note 2 of Tables 3 and 4). Internal Reference The internal reference is 4.096V for the MX036/ MX03 and 2.04V for the MX037/MX039. EL of the setup byte controls whether IN_/REF is used for an analog input or a reference (Table 6). When IN_/REF is configured to be an internal reference output (EL[2:] = ), decouple IN_/REF to GND with a 0.0µF capacitor. Due to the decoupling capacitor and the 675Ω reference source impedance, allow 0µs for the reference to stabilize during initial power-up. Once powered up, the reference always remains on until reconfigured. The reference should not be used to supply current for external circuitry. 5

16 4-/2-Channel 2-Wire erial -Bit DCs MX036 MX039. INGLE CONVERION WITH INTERNL CLOCK 7 LVE DDRE R CLOCK TRETCH B. CN MODE CONVERION WITH INTERNL CLOCK MTER TO LVE LVE TO MTER t CQ 7 LVE DDRE t CQ R t CONV CLOCK TRETCH t CONV REULT t CQ2 t CONV2 P or r CLOCK TRETCH t CQN t CONVN NUMBER OF BIT REULT REULT 2 REULT N P OR r NUMBER OF BIT NOTE: t CQ + t CONV 7.6μs PER CHNNEL. Figure 0. Internal Clock Mode Read Cycles MTER TO LVE LVE TO MTER. INGLE CONVERION WITH EXTERNL CLOCK 7 NUMBER OF BIT LVE DDRE R REULT P OR r t CQ t CONV B. CN MODE CONVERION WITH EXTERNL CLOCK 7 NUMBER OF BIT LVE DDRE R REULT REULT 2 REULT N P OR r t CQ t CONV t CQ2 t CONV2 t CQN t CONVN Figure. External Clock Mode Read Cycles 6

17 4-/2-Channel 2-Wire erial -Bit DCs Table 3. Channel election in ingle-ended Mode (GL / DIF = ) C3 C2 C C0 IN0 IN IN2 IN3 2 IN4 IN5 IN6 IN7 IN IN9 IN0 IN 2 GN D REERVED 0 REERVED 0 REERVED REERVED Note : For MX036/MX037, C3 and C2 are internally set to zero. Note 2: When EL =, a single-ended read of IN3/REF (MX036/MX037) or IN/REF (MX03/MX039) returns GND. MX036 MX039 7

18 4-/2-Channel 2-Wire erial -Bit DCs MX036 MX039 Table 4. Channel election in Pseudo-Differential Mode (GL / DIF = 0) C3 C2 C C0 IN0 IN IN2 IN3 2 IN4 IN5 IN6 IN7 IN IN9 IN0 IN REERVED 0 REERVED 0 REERVED REERVED Note : For MX036/MX037, C3 and C2 are internally set to zero. Note 2: When EL =, a pseudo-differential read between IN2 and IN3/REF (MX036/MX037) or IN0 and IN/REF (MX03/MX039) returns the difference between GND and IN2 or IN0, respectively. For example, a pseudo-differential read of 0 returns the negative difference between IN0 and GND. Note 3: When scanning multiple channels (CN0 = 0), C0 = 0 causes the even-numbered channel-select bits to be scanned, while C0 = causes the odd-numbered channel-select bits to be scanned. For example, if the MX03/MX039 CN[:0] = 00 and C[3:0] = 00, a pseudo-differential read returns IN0 IN, IN2 IN3, IN4 IN5, IN6 IN7, IN IN9, and IN0 IN. If the MX03/MX039 CN[:0] = 00 and C[3:0] = 0, a pseudo-differential read returns IN IN0, IN3 IN2, IN5 IN4, IN7 IN6, IN9 IN, and IN IN0.

19 4-/2-Channel 2-Wire erial -Bit DCs Table 5. canning Configuration CN CN0 CNNING CONFIGURTION 0 0 cans up from IN0 to the input selected by C3 C0 (default setting). 0 Converts the input selected by C3 C0 eight times.* 0 cans up from IN2 to the input selected by C and C0. When C and C0 are set for IN0 IN2, the scanning stops at IN2 (MX036/MX037). cans up from IN6 to the input selected by C3 C0. When C3 C0 is set for IN0 IN6 scanning stops at IN6 (MX03/MX039). Converts the channel selected by C3 C0.* *When operating in external clock mode, there is no difference between CN[:0] = 0 and CN[:0] = and converting continues until a not acknowledge occurs. Table 6. Reference Voltage and IN_/REF Format EL2 EL EL0 REFERENCE VOLTGE IN_/REF INTERNL REFERENCE TTE 0 0 X V DD nalog input lways Off 0 X External reference Reference input lways Off 0 0 Internal reference nalog input uto hutdown 0 Internal reference nalog input lways On X Internal reference Reference output lways On MX036 MX039 X = Don t care. External Reference The external reference can range from.0v to V DD. For maximum conversion accuracy, the reference must be able to deliver up to 30µ and have an output impedance of kω or less. If the reference has a higher output impedance or is noisy, bypass it to GND as close to IN_/REF as possible with a 0.µF capacitor. Transfer Functions Output data coding for the MX036 MX039 is binary in unipolar mode and two s complement binary in bipolar mode with LB = (V REF /2 N ) where N is the number of bits (). Code transitions occur halfway between successive-integer LB values. Figures 2 and 3 show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively. Layout, Grounding, and Bypassing For best performance, use PC boards. Wire-wrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. Do not run analog and digital lines parallel to each other, and do not lay out digital signal paths underneath the DC package. Use separate analog and digital PC board ground sections with only one star point (Figure 4) connecting the two ground systems (analog and digital). For lowest noise operation, ensure the ground return to the star ground s power supply is low impedance and as short as possible. Route digital signals far away from sensitive analog and reference inputs. High-frequency noise in the power supply (V DD ) could influence the proper operation of the DC s fast comparator. Bypass VDD to the star ground with a 0.µF capacitor located as close as possible to the MX036 MX039 power-supply pin. Minimize capacitor lead length for best supply-noise rejection, and add an attenuation resistor (5Ω) if the power supply is extremely noisy. Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The INL is measured using the endpoint method. 9

20 4-/2-Channel 2-Wire erial -Bit DCs MX036 MX039 OUTPUT CODE REF INPUT VOLTGE (LB) V REF LB = OUTPUT CODE (TWO' COMPLEMENT) REF '-' INPUT INPUT VOLTGE (LB) V REF LB = 256 Figure 2. Unipolar Transfer Function Figure 3. Bipolar Transfer Function UPPLIE Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of LB. DNL error specification of less than LB guarantees no missing codes and a monotonic transfer function. R* = 5Ω 3V/5V V LOGIC = 3V/5V GND V DD *OPTIONL 0.μF GND MX036 MX037 MX03 MX039 3V/5V DGND DIGITL CIRCUITRY Figure 4. Power-upply and Grounding Connections perture Jitter perture jitter (t J ) is the sample-to-sample variation in the time between the samples. perture Delay perture delay (t D ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. ignal-to-noise Ratio For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (NR) is the ratio of full-scale analog input (RM value) to the RM quantization error (residual error). The ideal, theoretical minimum analogto-digital noise is caused by quantization error only and results directly from the DC s resolution (N bits): NR = (6.02 N +.76)dB 20

21 4-/2-Channel 2-Wire erial -Bit DCs In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, NR is computed by taking the ratio of the RM signal to the RM noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. ignal-to-noise Plus Distortion ignal-to-noise plus distortion (IND) is the ratio of the fundamental input frequency s RM amplitude to RM equivalent of all other DC output signals. IND (db) = 20 log (ignalrm / NoiseRM) Effective Number of Bits Effective number of bits (ENOB) indicates the global accuracy of an DC at a specific input frequency and sampling rate. n ideal DC s error consists of quantization noise only. With an input range equal to the DC s full-scale range, calculate the ENOB as follows: ENOB = (IND -.76) / 6.02 Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RM sum of the input signal s first five harmonics to the fundamental itself. This is expressed as: THD = V + V + V + V 20 log / V where V is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. purious-free Dynamic Range purious-free dynamic range (FDR) is the ratio of RM amplitude of the fundamental (maximum signal component) to the RM value of the next-largest distortion component. MX036 MX039 PROCE: BiCMO Chip Information Package Information For the latest package outline information and land patterns, go to Note that a +, #, or - in the package code indicates RoH status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoH status. PCKGE TYPE PCKGE CODE DOCUMENT NO. OT23 KCN QOP E

22 4-/2-Channel 2-Wire erial -Bit DCs MX036 MX039 TOP VIEW IN0 IN IN2 IN3/REF IN7 IN6 IN5 IN4 IN Pin Configurations MX036 MX037 OT23 MX03 MX V DD GND D CL IN 5 IN9 4 IN0 3 IN/REF 2 V DD NLOG INPUT Typical Operating Circuit IN0 IN IN2 IN3/REF 5V V DD MX036 MX037 MX03 MX039 GND 5V D CL 5V *R *R R P R P IN2 IN GND D μc D CL IN0 9 CL QOP *OPTIONL 22

23 4-/2-Channel 2-Wire erial -Bit DCs REVIION NUMBER REVIION DTE DECRIPTION Revision History PGE CHNGED 2 5/0 Updated Ordering Information table, 2 3 2/09 Discontinued some versions of the family, 5,, 2 4 5/09 Updated Note 3 in Electrical Characteristics table 5 MX036 MX039 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 20 an Gabriel Drive, unnyvale, C Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.