Low-Power, 1-/2-Channel, I 2 C, 10-Bit ADCs in Ultra-Tiny 1.9mm x 2.2mm Package

Transcription

1 9-534; Rev ; 9/0 EVLUTION KIT VILBLE Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package General Description The MX646/MX647 low-power, 0-bit, -/2- channel analog-to-digital converters (DCs) feature internal track/hold (T/H), voltage reference, a clock, and an I 2 C-compatible 2-wire serial interface. These devices operate from a single supply of 2.7V to 3.6V (MX647) or 4.5V to 5.5V (MX646) and require only 6µ at a ksps sample rate. utohutdown powers down the devices between conversions, reducing supply current to less than µ at lower throughput rates. The MX646/MX647 each measure two single-ended or one differential input. The fully differential analog inputs are software configurable for unipolar or bipolar and single-ended or differential operation. The full-scale analog input range is determined by the internal reference or by an externally applied reference voltage ranging from V to V DD. The MX647 features a 2.04V internal reference and the MX646 features a 4.096V internal reference. The MX646/MX647 are available in an ultra-tiny.9mm x 2.2mm WLP package and an -pin µmx package. These DCs are guaranteed over the extended temperature range (-40 C to +5 C). For pin-compatible 2-bit parts, refer to the MX644/MX645 data sheet. Handheld Portable pplications Medical Instruments Battery-Powered Test Equipment Power-upply Monitoring olar-powered Remote ystems Received-ignal-trength Indicators ystem upervision pplications Features Ultra-Tiny.9mm x 2.2mm Wafer Level Package High-peed I 2 C-Compatible erial Interface 400kHz Fast Mode.7MHz High-peed Mode ingle upply 2.7V to 3.6V (MX647) 4.5V to 5.5V (MX646) Internal Reference 2.04V (MX647) 4.096V (MX646) External Reference: V to V DD Internal Clock 2-Channel ingle-ended or -Channel Fully Differential Internal FIFO with Channel-can Mode Low Power 670µ at 94.4ksps 230µ at 40ksps 60µ at 0ksps 6µ at ksps 0.5µ in Power-Down Mode oftware-configurable Unipolar/Bipolar Ordering Information PRT TEMP RNGE PIN- PCKGE I 2 C LVE DDRE MX646EU+ -40 C to +5 C μmx 000 MX647EU+ -40 C to +5 C μmx 000 MX647EWC+ -40 C to +5 C 2 WLP 000 +Denotes a lead(pb)-free/rohs-compliant package. MX646/MX647 Typical Operating Circuit and elector Guide appear at end of data sheet. utohutdown is a trademark of Maxim Integrated Products, Inc. µmx is a registered trademark of Maxim Integrated Products, Inc. Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at

2 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package MX646/MX647 BOLUTE MXIMUM RTING V DD to GND V to +6V IN0, IN, REF to GND V to the lower of (V DD + 0.3V) and 6V D, CL to GND V to +6V Maximum Current Into ny Pin...±50m Continuous Power Dissipation (T = +70 C) -Pin µmx (derate 4.5mW/ C above +70 C)...362mW 2-Pin WLP (derate 6.mW/ C above +70 C)...2mW ELECTRICL CHRCTERITIC Operating Temperature Range C to +5 C Junction Temperature C torage Temperature Range C to +50 C Lead Temperature (soldering, 0s) µmx only C oldering Temperature (reflow) C tresses beyond those listed under bsolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. (V DD = 2.7V to 3.6V (MX647), V DD = 4.5V to 5.5V (MX646), V REF = 2.04V (MX647), V REF = 4.096V (MX646), f CL =.7MHz, T = T MIN to T MX, unless otherwise noted. Typical values are at T = +25 C. ee Tables 5 for programming notation.) (Note ) PRMETER YMBOL CONDITION MIN TYP MX UNIT DC CCURCY (Note 2) Resolution 0 Bits Relative ccuracy INL (Note 3) ± LB Differential Nonlinearity DNL No missing codes over temperature ± LB Offset Error ± LB Offset-Error Temperature Coefficient Relative to FR 0.3 ppm/ C Gain Error (Note 4) ± LB Gain-Temperature Coefficient Relative to FR 0.3 ppm/ C Channel-to-Channel Offset Matching ±0. LB Channel-to-Channel Gain Matching ±0. LB DYNMIC PERFORMNCE (f IN(INE-WVE) = 0kHz, V IN(P-P) = V REF, f MPLE = 94.4ksps) ignal-to-noise and Distortion IND 60 db Total Harmonic Distortion THD Up to the fifth harmonic -70 db purious-free Dynamic Range FDR 70 db Full-Power Bandwidth IND > 57dB 3.0 MHz Full-Linear Bandwidth -3dB point 5.0 MHz CONVERION RTE Internal clock 6. Conversion Time (Note 5) t CONV External clock 0.6 μs Internal clock, CN[:0] = 0 53 Throughput Rate f MPLE External clock 94.4 ksps Track/Hold cquisition Time 00 ns 2

3 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package ELECTRICL CHRCTERITIC (continued) (V DD = 2.7V to 3.6V (MX647), V DD = 4.5V to 5.5V (MX646), V REF = 2.04V (MX647), V REF = 4.096V (MX646), f CL =.7MHz, T = T MIN to T MX, unless otherwise noted. Typical values are at T = +25 C. ee Tables 5 for programming notation.) (Note ) PRMETER YMBOL CONDITION MIN TYP MX UNIT Internal Clock Frequency 2. MHz External clock, fast mode 60 perture Delay (Note 6) t D External clock, high-speed mode 30 NLOG INPUT (IN0/IN) Input Voltage Range, ingle- Unipolar 0 V REF Ended and Differential (Note 7) Bipolar 0 ±V REF /2 Input Multiplexer Leakage On/off-leakage current, V IN_ = 0V or V DD ±0.0 ± μ Current Input Capacitance C IN 22 pf INTERNL REFERENCE (Note ) MX Reference Voltage V REF T = +25 C MX V Reference-Voltage Temperature Coefficient T CVREF 25 ppm/ C REF hort-circuit Current 2 m REF ource Impedance.5 k EXTERNL REFERENCE ns V MX646/MX647 REF Input Voltage Range V REF (Note 9) V DD V REF Input Current I REF f MPLE = 94.4ksps 40 μ DIGITL INPUT/OUTPUT (CL, D) Input High Voltage V IH 0.7 x V DD V Input Low Voltage V IL 0.3 x V DD V Input Hysteresis V HYT 0. x V DD V Input Current I IN V IN = 0V to V DD ±0 μ Input Capacitance C IN 5 pf Output Low Voltage V OL I INK = 3m 0.4 V POWER REQUIREMENT MX upply Voltage V DD MX f MPLE = 94.4ksps Internal reference external clock External reference f MPLE = 40ksps Internal reference 530 internal clock External reference 230 V upply Current I DD f MPLE = 0ksps Internal reference 30 internal clock External reference 60 μ f MPLE =ksps Internal reference 330 internal clock External reference 6 hutdown (internal reference off)

4 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package MX646/MX647 ELECTRICL CHRCTERITIC (continued) (V DD = 2.7V to 3.6V (MX647), V DD = 4.5V to 5.5V (MX646), V REF = 2.04V (MX647), V REF = 4.096V (MX646), f CL =.7MHz, T = T MIN to T MX, unless otherwise noted. Typical values are at T = +25 C. ee Tables 5 for programming notation.) (Note ) PRMETER YMBOL CONDITION MIN TYP MX UNIT POWER REQUIREMENT Power-upply Rejection Ratio PRR Full-scale input (Note 0) ±0.0 ±0.5 LB/V TIMING CHRCTERITIC (Figure ) (V DD = 2.7V to 3.6V (MX647), V DD = 4.5V to 5.5V (MX646), V REF = 2.04V (MX647), V REF = 4.096V (MX646), f CL =.7MHz, T = T MIN to T MX, unless otherwise noted. Typical values are at T = +25 C. ee Tables 5 for programming notation.) (Note ) PRMETER YMBOL CONDITION MIN TYP MX UNIT TIMING CHRCTERITIC FOR FT MODE erial-clock Frequency f CL 400 khz Bus Free Time Between a TOP (P) and a TRT () Condition Hold Time for a TRT () Condition t BUF.3 μs t HD:T 0.6 μs Low Period of the CL Clock t LOW.3 μs High Period of the CL Clock t HIGH 0.6 μs etup Time for a REPETED TRT Condition (r) t U:T 0.6 μs Data Hold Time t HD:DT (Note ) ns Data etup Time t U:DT 00 ns Rise Time of Both D and CL ignals, Receiving t R Measured from 0.3V DD to 0.7V DD C B 300 ns Fall Time of D Transmitting t F Measured from 0.3V DD to 0.7V DD (Note 2) C B 300 ns etup Time for a TOP (P) Condition t U:TO 0.6 μs Capacitive Load for Each Bus C B 400 pf Pulse Width of pike t P 50 ns TIMING CHRCTERITIC FOR HIGH-PEED MODE (C B = 400pF, Note 3) erial-clock Frequency f CLH (Note 4).7 MHz Hold Time, REPETED TRT Condition (r) t HD:T 60 ns Low Period of the CL Clock t LOW 320 ns High Period of the CL Clock t HIGH 20 ns etup Time for a REPETED TRT Condition (r) t U : T 60 ns Data Hold Time t HD : DT (Note ) 0 50 ns Data etup Time t U : DT 0 ns 4

5 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package TIMING CHRCTERITIC (Figure ) (continued) (V DD = 2.7V to 3.6V (MX647), V DD = 4.5V to 5.5V (MX646), V REF = 2.04V (MX647), V REF = 4.096V (MX646), f CL =.7MHz, T = T MIN to T MX, unless otherwise noted. Typical values are at T = +25 C. ee Tables 5 for programming notation.) (Note ) PRMETER YMBOL CONDITION MIN TYP MX UNIT Rise Time of CL ignal (Current ource Enabled) Rise Time of CL ignal fter cknowledge Bit Note : ll WLP devices are 00% production tested at T = +25 C. pecifications over temperature limits are guaranteed by design and characterization. Note 2: For DC accuracy, the MX646 is tested at V DD = 5V and the MX647 is tested at V DD = 3V, with an external reference for both DCs. ll devices are configured for unipolar, single-ended inputs. Note 3: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offsets have been calibrated. Note 4: Offset nulled. Note 5: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion time does not include acquisition time. CL is the conversion clock in the external clock mode. Note 6: filter on the D and CL inputs suppresses noise spikes and delays the sampling instant. Note 7: The absolute input voltage range for the analog inputs (IN0/IN) is from GND to V DD. Note : When the internal reference is configured to be available at REF (EL[2:] = ), decouple REF to GND with a 0.µF capacitor and a 2kΩ series resistor (see the Typical Operating Circuit). Note 9: DC performance is limited by the converter s noise floor, typically 300µV P-P. Note 0: Measured as follows for the MX647: 2N VF( 36. V) VF( 27. V) VREF ( 36. V 27. V) and for the MX646, where N is the number of bits: 2N V F ( 55. V) V F ( 45. V) V REF ( 55. V 45. V) t RCL Measured from 0.3V DD to 0.7V DD 20 0 ns t RCL Measured from 0.3V DD to 0.7V DD ns Fall Time of CL ignal t FCL Measured from 0.3V DD to 0.7V DD 20 0 ns Rise Time of D ignal t RD Measured from 0.3V DD to 0.7V DD ns Fall Time of D ignal t FD Measured from 0.3V DD to 0.7V DD (Note 2) ns etup Time for a TOP (P) Condition Capacitive Load for Each Bus Line t U : TO 60 ns C B 400 pf Pulse Width of pike t P (Notes and 4) 0 0 ns Note : master device must provide a data hold time for D (referred to V IL of CL) to bridge the undefined region of CL s falling edge (see Figure ). Note 2: The minimum value is specified at T = +25 C. Note 3: C B = total capacitance of one bus line in pf. Note 4: f CL must meet the minimum clock low time plus the rise/fall times. MX646/MX647 5

6 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package MX646/MX647 Typical Operating Characteristics (V DD = 3.3V (MX647), V DD = 5V (MX646), f CL =.7MHz, external clock, f MPLE = 94.4ksps, single-ended, unipolar, T = +25 C, unless otherwise noted.) DNL (LB) UPPLY CURRENT (μ) DIFFERENTIL NONLINERITY vs. DIGITL OUTPUT CODE DIGITL OUTPUT CODE UPPLY CURRENT vs. TEMPERTURE INTERNL REFERENCE ETUP BYTE EXT REF: 00 INT REF: 00 INTERNL REFERENCE EXTERNL REFERENCE EXTERNL REFERENCE MX646 MX647 MX646 MX TEMPERTURE ( C) MX646 toc0 MX646 toc04 INL (LB) IDD (μ) INTEGRL NONLINERITY vs. DIGITL OUTPUT CODE DIGITL OUTPUT CODE HUTDOWN UPPLY CURRENT vs. UPPLY VOLTGE D = CL = V DD UPPLY VOLTGE (V) MX646 toc02 MX646 toc05 MPLITUDE (dbc) UPPLY CURRENT (μ) FFT PLOT 0 0k 20k 30k 40k 50k FREQUENCY (Hz) f MPLE = 94.4ksps f IN = 0kHz HUTDOWN UPPLY CURRENT vs. TEMPERTURE MX646 MX TEMPERTURE ( C) MX646 toc03 MX646 toc06 VERGE IDD (μ) VERGE UPPLY CURRENT vs. CONVERION RTE (EXTERNL CLOCK) ) INTERNL REFERENCE LWY ON B) EXTERNL REFERENCE CONVERION RTE (ksps) B MX646 toc07 VREF NORMLIZED INTERNL REFERENCE VOLTGE vs. TEMPERTURE NORMLIZED TO REFERENCE VLUE T = +25 C MX646 MX TEMPERTURE ( C) MX646 toc0 6

7 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package Typical Operating Characteristics (continued) (V DD = 3.3V (MX647), V DD = 5V (MX646), f CL =.7MHz, external clock, f MPLE = 94.4ksps, single-ended, unipolar, T = +25 C, unless otherwise noted.) VREF NORMLIZED OFFET ERROR (LB) NORMLIZED REFERENCE VOLTGE vs. UPPLY VOLTGE MX647, NORMLIZED TO REFERENCE VLUE T V DD = 3.3V MX646, NORMLIZED TO REFERENCE VLUE T V DD = 5V V DD (V) OFFET ERROR vs. UPPLY VOLTGE V DD (V) MX646 toc09 MX646 toc OFFET ERROR (LB) GIN ERROR (LB) OFFET ERROR vs. TEMPERTURE TEMPERTURE ( C) GIN ERROR vs. TEMPERTURE TEMPERTURE ( C) MX646 toc0 MX646 toc2 MX646/MX647 GIN ERROR (LB) GIN ERROR vs. UPPLY VOLTGE V DD (V) MX646 toc3 7

8 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package MX646/MX647 TOP VIEW IN0 IN 2 N.C. 3 REF 4 + MX646 MX647 µmx V DD GND D CL TOP VIEW (BUMP ON BOTTOM) MX647 IN0 IN GND REF B GND GND GND GND C V DD GND D CL WLP Pin Configuration Pin Description μmx PIN WLP NME,2, 2 IN0, IN nalog Inputs FUNCTION 3 N.C. No connection. Not internally connected. 4 4 REF Reference Input/Output. elected in the setup register (see Tables and 6). 5 C4 CL Clock Input 6 C3 D Data Input/Output 7 3, B B4, C2 GND Ground C V DD Positive upply. Bypass to GND with a 0.μF capacitor.

9 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package. F/-MODE 2-WIRE ERIL-INTERFCE TIMING D t U:DT t HD:DT thd:t t LOW t U:T CL t HD:T t HIGH t R t F r B. H-MODE 2-WIRE ERIL-INTERFCE TIMING D t LOW t U:DT t HD:DT t U:T t HD:T CL t U:TO t U:TO t RD t R P t BUF t BUF t F t t FD MX646/MX647 t HD:T t HIGH t RCL t FCL t RCL r P H MODE F/ MODE Figure. 2-Wire erial-interface Timing 9

10 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package MX646/MX647 D CL V DD GND IN0 IN REF INPUT HIFT REGITER NLOG INPUT MUX ETUP REGITER CONFIGURTION REGITER T/H REF REFERENCE 4.096V (MX646) 2.04V (MX647) CONTROL LOGIC 0-BIT DC INTERNL OCILLTOR MX646 MX647 OUTPUT HIFT REGITER ND RM Figure 2. Functional Diagram D Figure 3. Load Circuit V DD Detailed Description The MX646/MX647 DCs use successiveapproximation conversion techniques and fully differential input T/H circuitry to capture and convert an analog signal to a serial 0-bit digital output. The MX646/MX647 measure either two singleended inputs or one differential input. These devices feature a high-speed, 2-wire serial interface supporting data rates up to.7mhz. Figure 2 shows the simplified internal structure for the MX646/MX647. I OL I OH V OUT 400pF Power upply The MX646/MX647 operate from a single supply and consume 670µ (typ) at sampling rates up to 94.4ksps. The MX647 features a 2.04V internal reference and the MX646 features a 4.096V internal reference. These devices can be configured for use with an external reference from V to V DD. nalog Input and Track/Hold The MX646/MX647 analog input architecture contains an analog input multiplexer (mux), a fully differential T/H capacitor, T/H switches, a comparator, and a fully differential switched capacitive digital-toanalog converter (DC) (Figure 4). In single-ended mode, the analog-input multiplexer connects C T/H between the analog input selected by C0 (see the Configuration/etup Bytes (Write Cycle) section) and GND (Table 3). In differential mode, the analog input multiplexer connects C T/H to the + and - analog inputs selected by C0 (Table 4). During the acquisition interval, the T/H switches are in the track position and C T/H charges to the analog input signal. t the end of the acquisition interval, the T/H switches move to the hold position retaining the charge on C T/H as a stable sample of the input signal. 0

11 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package During the conversion interval, the switched capacitive DC adjusts to restore the comparator input voltage to 0V within the limits of 0-bit resolution. This action requires 0 conversion clock cycles and is equivalent to transferring a charge of pf (V IN+ - V IN- ) from C T/H to the binary-weighted capacitive DC, forming a digital representation of the analog input signal. ufficiently low source impedance is required to ensure an accurate sample. source impedance of up to.5kω does not significantly degrade sampling accuracy. To minimize sampling errors with higher source impedances, connect a 00pF capacitor from the analog input to GND. This input capacitor forms an RC filter with the source impedance limiting the analog-input bandwidth. For larger source impedances, use a buffer amplifier to maintain analog-input signal integrity and bandwidth. When operating in internal clock mode, the T/H circuitry enters its tracking mode on the eighth rising clock edge of the address byte (see the lave ddress section). The T/H circuitry enters hold mode on the falling clock edge of the acknowledge bit of the address byte (the ninth clock pulse). conversion or a series of conversions is then internally clocked and the MX646/MX647 hold CL low. With external clock mode, the T/H circuitry enters track mode after a valid address on the rising edge of the clock during the read (R/W = ) bit. Hold mode is then entered on the rising edge of the second clock pulse during the shifting out of the first byte of the result. The conversion is performed during the next 0 clock cycles. The time required for the T/H circuitry to acquire an input signal is a function of the input sample capacitance. If the analog input source impedance is high, the acquisition time constant lengthens and more time must be allowed between conversions. The acquisition time (t CQ ) is the minimum time needed for the signal to be acquired. It is calculated by: t CQ 9 (R OURCE + R IN ) C IN where R OURCE is the analog input source impedance, R IN = 2.5kΩ, and C IN = 22pF. t CQ is.5/f CL for internal clock mode and t CQ = 2/fCL for external clock mode. nalog Input Bandwidth The MX646/MX647 feature input-tracking circuitry with a 5MHz small-signal bandwidth. The 5MHz input bandwidth makes it possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the DC s sampling rate by using under sampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. nalog Input Range and Protection Internal protection diodes clamp the analog input to V DD and GND. These diodes allow the analog inputs to swing from (V GND - 0.3V) to (V DD + 0.3V) without causing damage to the device. For accurate conversions the inputs must not go more than 50mV below GND or above V DD. MX646/MX647 NLOG INPUT MUX HOLD REF C T/H IN0 TRCK HOLD TRCK CPCITIVE DC IN TRCK HOLD V DD /2 GND TRCK HOLD TRCK CPCITIVE DC C T/H HOLD REF MX646 MX647 Figure 4. Equivalent Input Circuit

12 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package MX646/MX647 ingle-ended/differential Input The GL/DIF of the configuration byte configures the MX646/MX647 analog input circuitry for singleended or differential inputs (Table 2). In single-ended mode (GL/DIF = ), the digital conversion results are the difference between the analog input selected by C0 and GND (Table 3). In differential mode (GL/ DIF = 0), the digital conversion results are the difference between the + and the - analog inputs selected by C0 (Table 4). Unipolar/Bipolar When operating in differential mode, the BIP/UNI bit of the setup byte (Table ) selects unipolar or bipolar operation. Unipolar mode sets the differential input range from 0 to V REF. negative differential analog input in unipolar mode causes the digital output code to be zero. electing bipolar mode sets the differential input range to ±V REF /2. The digital output code is binary in unipolar mode and two s complement in bipolar mode. ee the Transfer Functions section. In single-ended mode, the MX646/MX647 always operate in unipolar mode irrespective of BIP/UNI. The analog inputs are internally referenced to GND with a full-scale input range from 0 to V REF. 2-Wire Digital Interface The MX646/MX647 feature a 2-wire interface consisting of a serial-data line (D) and serial-clock line (CL). D and CL facilitate bidirectional communication between the MX646/MX647 and the master at rates up to.7mhz. The MX646/MX647 are slaves that transfer and receive data. The master (typically a microcontroller) initiates data transfer on the bus and generates the CL signal to permit that transfer. D and CL must be pulled high. This is typically done with pullup resistors (750Ω or greater) (see the Typical Operating Circuit). eries resistors (R ) are optional. They protect the input architecture of the MX646/ MX647 from high voltage spikes on the bus lines, minimize crosstalk, and undershoot of the bus signals. Bit Transfer One data bit is transferred during each CL clock cycle. minimum of clock cycles are required to transfer the data in or out of the MX646/ MX647. The data on D must remain stable during the high period of the CL clock pulse. Changes in D while CL is stable are considered control signals (see the TRT and TOP Conditions section). Both D and CL remain high when the bus is not busy. TRT and TOP Conditions The master initiates a transmission with a TRT condition (), a high-to-low transition on D while CL is high. The master terminates a transmission with a TOP condition (P), a low-to-high transition on D while CL is high (Figure 5). repeated TRT condition (r) can be used in place of a TOP condition to leave the bus active and the mode unchanged (see the H Mode section). cknowledge Bits Data transfers are acknowledged with an acknowledge bit () or a not-acknowledge bit (). Both the master and the MX646/MX647 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull D low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (Figure 6). To generate a not-acknowledge, the receiver allows D to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves D high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. n unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. D CL Figure 5. TRT and TOP Conditions D CL Figure 6. cknowledge Bits r P NOT CKNOWLEDGE CKNOWLEDGE 2 9 2

13 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package D CL DEVICE MX646/MX647 Figure 7. lave ddress Byte LVE DDRE 000 LVE DDRE R/W lave ddress bus master initiates communication with a slave device by issuing a TRT condition followed by a slave address. When idle, the MX646/MX647 continuously wait for a TRT condition followed by their slave address. When the MX646/MX647 recognize their slave address, they are ready to accept or send data. The slave address has been factory programmed and is always 000 for the MX646/MX647 (Figure 7). The least significant bit (LB) of the address byte (R/W) determines whether the master is writing to or reading from the MX646/MX647 (R/W = 0 selects a write condition, R/W = selects a read condition). fter receiving the address, the MX646/MX647 (slave) issue an acknowledge by pulling D low for one clock cycle. Bus Timing t power-up, the MX646/MX647 bus timing is set for fast mode (F/ mode), allowing conversion rates up to 22.2ksps. The MX646/MX647 must operate in high-speed mode (H mode) to achieve conversion rates up to 94.4ksps. Figure shows the bus timing for the MX646/MX647 s 2-wire interface. H Mode t power-up, the MX646/MX647 bus timing is set for F/ mode. The bus master selects H mode by addressing all devices on the bus with the H-mode master code 0000 XXX (X = don t care). fter successfully receiving the H-mode master code, the MX646/MX647 issue a not-acknowledge, allowing D to be pulled high for one clock cycle (Figure ). fter the not-acknowledge, the MX646/ MX647 are in H mode. The bus master must then send a repeated TRT followed by a slave address to initiate H-mode communication. If the master generates a TOP condition the MX646/MX647 return to F/ mode. MX646/MX647 H-MODE MTER CODE X X X r D CL F/ MODE H MODE Figure. F/-Mode to H-Mode Transfer 3

14 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package MX646/MX647 MTER TO LVE LVE TO MTER. -BYTE WRITE CYCLE 7 LVE DDRE W ETUP OR CONFIGURTION BYTE MB DETERMINE WHETHER ETUP OR CONFIGURTION BYTE Configuration/etup Bytes (Write Cycle) write cycle begins with the bus master issuing a TRT condition followed by 7 address bits (Figure 7) and a write bit (R/W = 0). If the address byte is successfully received, the MX646/MX647 (slave) issue an acknowledge. The master then writes to the slave. The slave recognizes the received byte as the setup byte (Table ) if the most significant bit (MB) is. If the MB is 0, the slave recognizes that byte as the configuration byte (Table 2). The master can write either or 2 bytes to the slave in any order (setup byte then configuration byte, configuration byte then setup byte, setup byte or configuration byte only; see Figure 9). If the slave receives a byte successfully, it issues an acknowledge. The master ends the write cycle by issuing a TOP condition or a repeated TRT condition. When operating in H mode, a TOP condition returns the bus into F/ mode (see the H Mode section). P or r NUMBER OF BIT B. 2-BYTE WRITE CYCLE 7 NUMBER OF BIT LVE DDRE W ETUP OR CONFIGURTION BYTE ETUP OR CONFIGURTION BYTE P or r MB DETERMINE WHETHER ETUP OR CONFIGURTION BYTE Figure 9. Write Cycle Table. etup Byte Format BIT 7 (MB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT REG EL2 EL EL0 CLK BIP/UNI RT X BIT 0 (LB) BIT NME DECRIPTION 7 REG Register bit. = setup byte, 0 = configuration byte (see Table 2). 6 EL2 5 EL Three bits select the reference voltage (Table 6). Default to 000 at power-up. 4 EL0 3 CLK = external clock, 0 = internal clock. Defaulted to 0 at power-up. 2 BIP/UNI = bipolar, 0 = unipolar. Defaulted to 0 at power-up (see the Unipolar/Bipolar section). RT = no action, 0 = resets the configuration register to default. etup register remains unchanged. 0 X Don t-care bit. This bit can be set to or 0. 4

15 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package Table 2. Configuration Byte Format BIT 7 (MB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT BIT 0 (LB) REG CN CN0 X X X C0 GL/DIF BIT NME DECRIPTION 7 REG Register bit. = setup byte (see Table ), 0 = configuration byte. 6 CN 5 CN0 4 X 3 X 2 X C0 0 GL/DIF X = Don t care. Table 3. Channel election in ingle- Ended Mode (GL/DIF = ) C0 IN0 IN GND X = Don t care. can-select bits. Two bits select the scanning configuration (Table 5). Defaults to 00 at power-up. Channel-select bit. C0 selects which analog input channels are to be used for conversion (Tables 3 and 4). Defaults to 0000 at power-up. = single-ended, 0 = differential (Tables 3 and 4). Defaults to at power-up. ee the ingle- Ended/Differential Input section. Table 4. Channel election in Differential Mode (GL/DIF = 0) X = Don t care. C0 IN0 IN MX646/MX647 Data Byte (Read Cycle) read cycle must be initiated to obtain conversion results. Read cycles begin with the bus master issuing a TRT condition followed by 7 address bits and a read bit (R/W = ). If the address byte is successfully received, the MX646/MX647 (slave) issue an acknowledge. The master then reads from the slave. The result is transmitted in 2 bytes; first 6 bits of the first byte are high, then MB through LB are consecutively clocked out. fter the master has received the byte(s), it can issue an acknowledge if it wants to continue reading or a not-acknowledge if it no longer wishes to read. If the MX646/MX647 receive a notacknowledge, they release D, allowing the master to generate a TOP or a repeated TRT condition. ee the Clock Modes and can Mode sections for detailed information on how data is obtained and converted. Clock Modes The clock mode determines the conversion clock and the data acquisition and conversion time. The clock mode also affects the scan mode. The state of the setup byte s CLK bit determines the clock mode (Table ). t power-up, the MX646/MX647 are defaulted to internal clock mode (CLK = 0). 5

16 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package MX646/MX647 Internal Clock When configured for internal clock mode (CLK = 0), the MX646/MX647 use their internal oscillator as the conversion clock. In internal clock mode, the MX646/MX647 begin tracking the analog input after a valid address on the eighth rising edge of the clock. On the falling edge of the ninth clock, the analog signal is acquired and the conversion begins. While converting the analog input signal, the MX646/ MX647 hold CL low (clock stretching). fter the conversion completes, the results are stored in internal memory. If the scan mode is set for multiple conversions, they all happen in succession with each additional result stored in memory. The MX646/ MX647 contain two 0-bit blocks of memory. Once all conversions are complete, the MX646/MX647 release CL, allowing it to be pulled high. The master can now clock the results out of the memory in the same order the scan conversion has been done at a clock rate of up to.7mhz. CL is stretched for a maximum of 7.6µs per channel (see Figure 0). The device memory contains all of the conversion results when the MX646/MX647 release CL. The converted results are read back in a first-in/first-out (FIFO) sequence. The memory contents can be read continuously. If reading continues past the result stored in memory, the pointer wraps around and point to the first result. Note that only the current conversion results are read from memory. The device must be addressed with a read command to obtain new conversion results. The internal clock mode s clock stretching quiets the CL bus signal, reducing the system noise during conversion. Using the internal clock also frees the bus master (typically a microcontroller) from the burden of running the conversion clock, allowing it to perform other tasks that do not need to use the bus. MTER TO LVE LVE TO MTER. INGLE CONVERION WITH INTERNL CLOCK 7 NUMBER OF BIT LVE DDRE R CLOCK TRETCH REULT 2 MBs REULT LBs P or r t CQ t CONV B. CN MODE CONVERION WITH INTERNL CLOCK 7 NUMBER OF BIT LVE DDRE R CLOCK TRETCH CLOCK TRETCH REULT ( 2MBs) REULT ( LBs) REULT N (MBs) REULT N (LBs) P or r t CQ t CONV t CQ2 t CONV2 t CQN t CONVN Figure 0. Internal Clock Mode Read Cycles 6

17 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package External Clock When configured for external clock mode (CLK = ), the MX646/MX647 use the CL as the conversion clock. In external clock mode, the MX646/ MX647 begin tracking the analog input on the ninth rising clock edge of a valid slave address byte. Two CL clock cycles later the analog signal is acquired and the conversion begins. Unlike internal clock mode, converted data is available immediately after the first four empty high bits. The device continuously converts input channels dictated by the scan mode until given a not acknowledge. There is no need to re-address the device with a read command to obtain new conversion results (see Figure ). The conversion must complete in ms or droop on the track-and-hold capacitor degrades conversion results. Use internal clock mode if the CL clock period exceeds 60µs. MTER TO LVE LVE TO MTER The MX646/MX647 must operate in external clock mode for conversion rates from 40ksps to 94.4ksps. Below 40ksps internal clock mode is recommended due to much smaller power consumption. can Mode CN0 and CN of the configuration byte set the scan mode configuration. Table 5 shows the scanning configurations. The scanned results are written to memory in the same order as the conversion. Read the results from memory in the order they were converted. Each result needs a 2-byte transmission, the first byte begins with six empty bits during which D is left high. Each byte has to be acknowledged by the master or the memory transmission is terminated. It is not possible to read the memory independently of conversion. MX646/MX647. INGLE CONVERION WITH EXTERNL CLOCK 7 NUMBER OF BIT LVE DDRE R REULT (2 MBs) REULT ( LBs) P OR r t CQ t CONV B. CN MODE CONVERION WITH EXTERNL CLOCK 7 NUMBER OF BIT LVE DDRE R REULT (2 MBs) REULT 2 ( LBs) REULT N (2 MBs) REULT N ( LBs) P OR r t CQ t CQ2 t CQN t CONV t CONVN Figure. External Clock Mode Read Cycle Table 5. canning Configuration CN CN0 CNNING CONFIGURTION 0 0 cans up from IN0 to the input selected by C0. 0 Converts the input selected by C0 eight times (see Tables 3 and 4).* 0 Reserved. Do not use. Converts input selected by C0.* *When operating in external clock mode, there is no difference between CN[:0] = 0 and CN[:0] =, and converting occurs perpetually until not acknowledge occurs. 7

18 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package MX646/MX647 pplications Information Power-On Reset The configuration and setup registers (Tables and 2) default to a single-ended, unipolar, single-channel conversion on IN0 using the internal clock with V DD as the reference. The memory contents are unknown after power-up. utomatic hutdown utomatic shutdown occurs between conversions when the MX646/MX647 are idle. ll analog circuits participate in automatic shutdown except the internal reference due to its prohibitively long wake-up time. When operating in external clock mode, a TOP, notacknowledge, or repeated TRT condition must be issued to place the devices in idle mode and benefit from automatic shutdown. TOP condition is not necessary in internal clock mode to benefit from automatic shutdown because power-down occurs once all conversion results are written to memory (Figure 0). When using an external reference or V DD as a reference, all analog circuitry is inactive in shutdown and supply current is less than 0.5µ (typ). The digital conversion results obtained in internal clock mode are maintained in memory during shutdown and are available for access through the serial interface at any time prior to a TOP or a repeated TRT condition. When idle, the MX646/MX647 continuously wait for a TRT condition followed by their slave address (see the lave ddress section). Upon reading a valid address byte the MX646/MX647 power up. The internal reference requires 0ms to wake up, so when using the internal reference it should be powered up 0ms prior to conversion or powered continuously. Wake-up is invisible when using an external reference or V DD as the reference. utomatic shutdown results in dramatic power savings, particularly at slow conversion rates and with internal clock. For example, at a conversion rate of 0ksps, the average supply current for the MX647 is 60µ (typ) and drops to 6µ (typ) at ksps. t 0.ksps the average supply current is just µ, or a minuscule 3µW of power consumption (see verage upply Current vs. Conversion Rate (External Clock) in the Typical Operating Characteristics). Reference Voltage EL[2:0] of the setup byte (Table ) control the reference and the REF configuration (Table 6). Internal Reference The internal reference is 4.096V for the MX646 and 2.04V for the MX647. When REF is configured to be an internal reference output (EL[2:] = ), decouple REF to GND with a 0.µF capacitor and a 2kΩ series resistor (see the Typical Operating Circuit). Once powered up, the reference always remains on until reconfigured. The internal reference requires 0ms to wake up and is accessed using EL0 (Table 6). When in shutdown, the internal reference output is in a high-impedance state. The reference should not be used to supply current for external circuitry. The internal reference does not require an external bypass capacitor and works best when left unconnected (EL = 0). External Reference The external reference can range from V to V DD. For maximum conversion accuracy, the reference must be able to deliver up to 40µ and have an output impedance of 500Ω or less. If the reference has a higher output impedance or is noisy, bypass it to GND as close as possible to REF with a 0.µF capacitor. Table 6. Reference Voltage and REF Format EL2 EL EL0 REFERENCE VOLTGE REF INTERNL REFERENCE TTE 0 0 X V DD Not connected lways off 0 X External reference Reference input lways off 0 0 Internal reference Not connected* lways off 0 Internal reference Not connected* lways on 0 Internal reference Reference output lways off Internal reference Reference output lways on X = Don t care. *Preferred configuration for internal reference.

19 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package Transfer Functions Output data coding for the MX646/MX647 is binary in unipolar mode and two s complement in bipolar mode with LB = (V REF /2 N ) where N is the number of bits (0). Code transitions occur halfway between successive-integer LB values. Figures 2 and 3 show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively OUTPUT CODE FULL-CLE TRNITION F INPUT VOLTGE (LB) Figure 2. Unipolar Transfer Function MX646 MX647 F - 3/2 LB F = V REF Z = GND LB = V REF 024 Layout, Grounding, and Bypassing Only use PCBs. Wire-wrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. Do not run analog and digital lines parallel to each other, and do not lay out digital signal paths underneath the DC package. Use separate analog and digital PCB ground sections with only one star point (Figure 4) connecting the two ground systems (analog and digital). For lowest noise operation, ensure the ground return to the star ground s power supply is low impedance and as short as possible. Route digital signals far away from sensitive analog and reference inputs. High-frequency noise in the power supply (V DD ) could influence the proper operation of the DC s fast comparator. Bypass V DD to the star ground with a network of two parallel capacitors, 0.µF and 4.7µF, located as close as possible to the MX646/MX647 powersupply pin. Minimize capacitor lead length for best supply noise rejection, and add an attenuation resistor (5Ω) in series with the power supply if it is extremely noisy. Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The MX646/ MX647 s INL is measured using the endpoint. MX646/MX OUTPUT CODE F = V REF 2 Z = 0 -F = -V REF 2 LB = V REF 024 MX646 MX647 3V OR 5V R* = 5Ω 4.7μF UPPLIE V LOGIC = 3V/5V GND μF V DD GND 3V/5V DGND F 0 +F - LB MX646 MX647 DIGITL CIRCUITRY INPUT VOLTGE (LB) *V COM V REF /2 *V IN = (IN+) - (IN-) *OPTIONL Figure 3. Bipolar Transfer Function Figure 4. Power-upply Grounding Connection 9

20 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package MX646/MX647 Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of LB. DNL error specification of less than LB guarantees no missing codes and a monotonic transfer function. perture Jitter perture jitter (t J ) is the sample-to-sample variation in the time between the samples. perture Delay perture delay (t D ) is the time between the falling edge of the sampling clock and the instant when an actual sample is taken. ignal-to-noise Ratio For a waveform perfectly reconstructed from digital samples, the theoretical maximum NR is the ratio of the fullscale analog input (RM value) to the RM quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the DC s resolution (N Bits): NR MX[dB] = 6.02 db N +.76 db In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. NR is computed by taking the ratio of the RM signal to the RM noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. ignal-to-noise Plus Distortion ignal-to-noise plus distortion (IND) is the ratio of the fundamental input frequency s RM amplitude to RM equivalent of all other DC output signals. IND (db) = 20 log (ignalrm/noiserm) Effective Number of Bits Effective number of bits (ENOB) indicates the global accuracy of an DC at a specific input frequency and sampling rate. n ideal DC s error consists of quantization noise only. With an input range equal to the DC s full-scale range, calculate the ENOB as follows: ignalrm IND( db) = 20 log NoiseRM + THDRM ENOB = (IND -.76)/6.02 Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RM sum of the input signal s first five harmonics to the fundamental itself. This is expressed as: THD = 20 log V + V + V + V V where V is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd through 5th order harmonics. purious-free Dynamic Range purious-free dynamic range (FDR) is the ratio of RM amplitude of the fundamental (maximum signal component) to the RM value of the next largest distortion component. 20

21 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package RC NETWORK* C REF 0.μF *OPTIONL 0.μF NLOG INPUT Typical Operating Circuit 2kΩ IN0 IN REF 3.3V or 5V V DD MX646 MX647 GND 5V μc D CL 5V D CL R * R * R P R P PRT MX646 MX647 INPUT CHNNEL 2 ingle- Ended/ Differential 2 ingle- Ended/ Differential PROCE: BiCMO INTERNL REFERENCE (V) elector Guide UPPLY VOLTGE (V) INL (LB) to 5.5 ± to 3.6 ± Chip Information Package Information For the latest package outline information and land patterns, go to Note that a +, #, or - in the package code indicates RoH status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoH status. PCKGE TYPE PCKGE CODE OUTLINE NO. LND PTTERN NO. µmx UCN MX646/MX647 2 WLP W2C Refer to pplication Note 9 2

22 MX646/MX647 Low-Power, -/2-Channel, I 2 C, 0-Bit DCs in Ultra-Tiny.9mm x 2.2mm Package REVIION NUMBER REVIION DTE DECRIPTION Revision History PGE CHNGED 0 /0 Initial release 9/0 dded the WLP package to the Ordering Information, bsolute Maximum Ratings, Pin Configuration, Pin Description, and Package Information sections, 2,, 20 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 22 Maxim Integrated Products, 20 an Gabriel Drive, unnyvale, C Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.