2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel 2-Wire Serial 8-Bit ADCs

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1 9-4554; Rev 2; 3/0 EVLUTION KIT VILBLE 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/-/2-Channel 2-Wire Serial -Bit DCs General Description The MX600 MX605 low-power, -bit, multichannel, analog-to-digital converters (DCs) feature internal track/hold (T/H), voltage reference, clock, and an I 2 C-compatible 2-wire serial interface. These devices operate from a single supply and require only 350µ at the maximum sampling rate of ksps. uto- Shutdown powers down the devices between conversions, reducing supply current to less than µ at low throughput rates. The MX600/MX60 provide 4 analog input channels each, the MX602/MX603 provide analog input channels each while the MX604/MX605 provide 2 analog input channels. The analog inputs are software configurable for unipolar or bipolar and single-ended or pseudo-differential operation. The full-scale analog input range is determined by the internal reference or by an externally applied reference voltage ranging from V to V DD. The MX60/ MX603/MX605 feature a 2.04V internal reference and the MX600/MX602/MX604 feature a 4.096V internal reference. The MX600/MX60 are available in -pin SOT23 packages. The MX602 MX605 are available in 6-pin QSOP packages. The MX600 MX605 are guaranteed over the extended industrial temperature range (-40 C to +5 C). Refer to the MX606 MX6 for 0-bit devices and to the MX62 MX67 for 2-bit devices. pplications Handheld Portable pplications Medical Instruments Battery-Powered Test Equipment Solar-Powered Remote Systems Received-Signal-Strength Indicators System Supervision Features High-Speed I 2 C-Compatible Serial Interface 400kHz Fast Mode.7MHz High-Speed Mode Single Supply 2.7V to 3.6V (MX60/MX603/MX605) 4.5V to 5.5V (MX600/MX602/MX604) Internal Reference 2.04V (MX60/MX603/MX605) 4.096V (MX600/MX602/MX604) External Reference: V to V DD Internal Clock 4-Channel Single-Ended or 2-Channel Pseudo- Differential (MX600/MX60) -Channel Single-Ended or 4-Channel Pseudo- Differential (MX602/MX603) 2-Channel Single-Ended or 6-Channel Pseudo- Differential (MX604/MX605) Internal FIFO with Channel-Scan Mode Low Power 350µ at ksps 0µ at 75ksps µ at 0ksps µ in Power-Down Mode Software Configurable Unipolar/Bipolar Small Packages -Pin SOT23 (MX600/MX60) 6-Pin QSOP (MX602 MX605) Pin Configurations and Typical Operating Circuit appear at end of data sheet. Ordering Information/Selector Guide MX600 MX605 PRT TEMP RNGE PIN-PCKGE TUE (LSB) INPUT CHNNELS INTERNL REFERENCE (V) TOP MRK MX600EK+ -40 C to +5 C SOT23 ± EQH MX60EK+ -40 C to +5 C SOT23 ± EQI MX602EEE+ -40 C to +5 C 6 QSOP ± MX603EEE+ -40 C to +5 C 6 QSOP ± 2.04 MX604EEE+ -40 C to +5 C 6 QSOP ± MX605EEE+ -40 C to +5 C 6 QSOP ± Denotes a lead(pb)-free/rohs-compliant package. utoshutdown is a trademark of Maxim Integrated Products, Inc. Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim's website at

2 4-/-/2-Channel 2-Wire Serial -Bit DCs MX600 MX605 BSOLUTE MXIMUM RTINGS V DD to GND V to +6V IN0 IN, REF to GND V to the lower of (V DD + 0.3V) and +6V SD, SCL to GND V to +6V Maximum Current into ny Pin...±50m Continuous Power Dissipation (T = +70 C) -Pin SOT23 (derate 7.mW/ C above +70 C)...567mW 6-Pin QSOP (derate.3mw/ C above +70 C) mW Stresses beyond those listed under bsolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICL CHRCTERISTICS Operating Temperature Range C to +5 C Junction Temperature C Storage Temperature Range C to +50 C Lead Temperature (soldering, 0s) C Soldering Temperature (reflow) C (V DD = 2.7V to 3.6V (MX60/MX603/MX605), V DD = 4.5V to 5.5V (MX600/MX602/MX604). External reference, V REF = 2.04V (MX60/MX603/MX605), V REF = 4.096V (MX600/MX602/MX604). External clock, f SCL =.7MHz, T = T MIN to T MX, unless otherwise noted. Typical values are at T = +25 C.) PRMETER SYMBOL CONDITIONS MIN TYP MX UNITS DC CCURCY (Note ) Resolution Bits Relative ccuracy INL (Note 2) ± LSB Differential Nonlinearity DNL No missing codes over temperature ± LSB Offset Error ±.5 LSB Offset-Error Temperature Coefficient 3 ppm/ C Gain Error (Note 3) ± LSB Gain Temperature Coefficient ± ppm/ C Total Unadjusted Error Channel-to-Channel Offset Matching TUE MX600/MX60 ±0.5 ±2 MX602/MX603 ±0.5 ± MX604/MX605 ±0.5 ± LSB ±0. LSB Channel-to-Channel Gain Matching Input Common-Mode Rejection Ratio ±0.5 LSB CMRR Pseudo-differential input mode 75 db DYNMIC PERFORMNCE (f IN (sine wave) = 25kHz, V IN = V REF(P-P), f SMPLE = ksps, R IN = 00Ω) Signal-to-Noise Plus Distortion SIND 49 db Total Harmonic Distortion THD Up to the 5th harmonic -69 db Spurious-Free Dynamic Range SFDR 69 db Channel-to-Channel Crosstalk (Note 4) 75 db Full-Power Bandwidth -3dB point 2.0 MHz Full-Linear Bandwidth SIND > 49dB 200 khz CONVERSION RTE Internal clock 6. Conversion Time (Note 5) t CONV External clock 4.7 µs 2

3 4-/-/2-Channel 2-Wire Serial -Bit DCs ELECTRICL CHRCTERISTICS (continued) (V DD = 2.7V to 3.6V (MX60/MX603/MX605), V DD = 4.5V to 5.5V (MX600/MX602/MX604). External reference, V REF = 2.04V (MX60/MX603/MX605), V REF = 4.096V (MX600/MX602/MX604). External clock, f SCL =.7MHz, T = T MIN to T MX, unless otherwise noted. Typical values are at T = +25 C.) Throughput Rate PRMETER SYMBOL CONDITIONS MIN TYP MX UNITS f SMPLE Internal clock, SCN[:0] = 0 (MX600/MX60) SCN[:0] = 00 CS[3:0] = 0 (MX602/MX603) Internal clock, SCN[:0] = 00 CS[3:0] = 0 (MX604/MX605) External clock Track/Hold cquisition Time 5 ns Internal Clock Frequency 2.25 MHz External clock, fast mode 45 perture Delay t D External clock, high-speed mode 30 NLOG INPUT (IN0 IN) Input Voltage Range, Single Unipolar 0 V REF Ended and Differential (Note 6) Bipolar ±V REF / ksps ns V MX600 MX605 Input Multiplexer Leakage Current On/off-leakage current, V IN _ = 0 or V DD, no clock, f SCL = 0 ±0.0 ± µ Input Capacitance C IN pf INTERNL REFERENCE (Note 7) M X60/M X 603/MX Reference Voltage V REF T = +25 C M X600/M X 602/MX V Reference Temperature Coefficient TC REF 20 ppm/ C Reference Short-Circuit Current 0 m Reference Source Impedance (Note ) 675 Ω EXTERNL REFERENCE Reference Input Voltage Range V REF (Note 9).0 V DD V REF Input Current I REF f SMPLE = ksps 4 30 µ DIGITL INPUTS/OUTPUTS (SCL, SD) Input High Voltage V IH 0.7 x V DD V Input Low Voltage V IL 0.3 x V DD V Input Hysteresis V HYST 0. x V DD V Input Current I IN V IN = 0 to V DD ±0 µ Input Capacitance C IN 5 pf Output Low Voltage V OL I SINK = 3m 0.4 V 3

4 4-/-/2-Channel 2-Wire Serial -Bit DCs MX600 MX605 ELECTRICL CHRCTERISTICS (continued) (V DD = 2.7V to 3.6V (MX60/MX603/MX605), V DD = 4.5V to 5.5V (MX600/MX602/MX604). External reference, V REF = 2.04V (MX60/MX603/MX605), V REF = 4.096V (MX600/MX602/MX604). External clock, f SCL =.7MHz, T = T MIN to T MX, unless otherwise noted. Typical values are at T = +25 C.) PRMETER SYMBOL CONDITIONS MIN TYP MX UNITS POWER REQUIREMENTS MX60/MX603/MX Supply Voltage (Note 0) V DD MX600/MX602/MX Supply Current I DD f SMPLE = Internal REF, external clock ksps External REF, external clock 250 f SMPLE = External REF, external clock 0 75ksps External REF, internal clock 50 f SMPLE = External REF, external clock 0ksps External REF, internal clock 0 f SMPLE = External REF, external clock 2 ksps External REF, internal clock 2.5 Power-down 0 Power-Supply Rejection Ratio PSRR (Note ) ±0.25 ± LSB/V TIMING CHRCTERISTICS FOR 2-WIRE FST MODE (Figures a and 2) Serial-Clock Frequency f SCL 400 khz Bus Fr ee Ti m e Betw een a S TO P ( P ) and a S TRT ( S ) C ond i ti on t BUF.3 µs Hold Time for STRT Condition t HD.ST 0.6 µs Low Period of the SCL Clock t LOW.3 µs High Period of the SCL Clock t HIGH 0.6 µs Setup Time for a Repeated STRT Condition (Sr) t SU.ST 0.6 µs Data Hold Time t HD.DT (Note 2) 0 50 ns Data Setup Time t SU.DT 00 ns Rise Time of Both SD and SCL Signals, Receiving t R (Note 3) C B 300 ns Fall Time of SD Transmitting t F (Note 3) C B 300 ns Setup Time for STOP Condition t SU.STO 0.6 µs Capacitive Load for Each Bus Line C B 400 pf Pulse Width of Spike Suppressed t SP 50 ns TIMING CHRCTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figures b and 2) Serial-Clock Frequency f SCLH (Note 4).7 MHz Hold Time (Repeated) STRT Condition t HD.ST 60 ns Low Period of the SCL Clock t LOW 320 ns High Period of the SCL Clock t HIGH 20 ns Setup Time for a Repeated STRT Condition (Sr) t SU. ST 60 ns V µ 4

5 4-/-/2-Channel 2-Wire Serial -Bit DCs ELECTRICL CHRCTERISTICS (continued) (V DD = 2.7V to 3.6V (MX60/MX603/MX605), V DD = 4.5V to 5.5V (MX600/MX602/MX604). External reference, V REF = 2.04V (MX60/MX603/MX605), V REF = 4.096V (MX600/MX602/MX604). External clock, f SCL =.7MHz, T = T MIN to T MX, unless otherwise noted. Typical values are at T = +25 C.) PRMETER SYMBOL CONDITIONS MIN TYP MX UNITS Data Hold Time t HD. DT (Note 2) 0 50 ns Data Setup Time t SU. DT 0 ns Rise Time of SCL Signal (Current Source Enabled) Rise Time of SCL Signal fter cknowledge Bit t RCL (Note 3) 20 0 ns t RCL (Note 3) ns Fall Time of SCL Signal t FCL (Note 3) 20 0 ns Rise Time of SD Signal t RD (Note 3) ns Fall Time of SD Signal t FD (Note 3) ns Setup Time for STOP Condition t SU, STO 60 ns Capacitive Load for Each Bus Line C B 400 pf Pulse Width of Spike Suppressed t SP 0 0 ns Note : The MX600/MX602/MX604 are tested at V DD = 5V and the MX60/MX603/MX605 are tested at V DD = 3V. ll devices are configured for unipolar, single-ended inputs. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offsets have been calibrated. Note 3: Offset nulled. Note 4: Ground on channel; sine wave applied to all off channels. Note 5: Conversion time is defined as the number of clock cycles (eight) multiplied by the clock period. Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode. Note 6: The absolute voltage range for the analog inputs (IN0 IN) is from GND to V DD. Note 7: When IN_/REF (MX600/MX60/MX604/MX605) or REF (MX602/MX603) is configured to be an internal reference (SEL[2:] = ), decouple IN_/REF or REF to GND with a 0.0µF capacitor. Note : The switch connecting the reference buffer to IN_/REF or REF has a typical on-resistance of 675Ω. Note 9: DC performance is limited by the converter s noise floor, typically.4mv P-P. Note 0: Electrical characteristics are guaranteed from V DD(MIN) to V DD(MX). For operation beyond this range, see the Typical Operating Characteristics. Note : Power-supply rejection ratio is measured as: MX600 MX605 N 2 [ VFS( 33. V) VFS( 27. V) ] VREF 33. V 27. V, for the MX60/MX603/MX605, where N is the number of bits. Power-supply rejection ratio is measured as: N 2 [ VFS( 55. V) VFS( 45. V) ] VREF 55. V 45. V, for the MX600/MX602/MX604, where N is the number of bits. Note 2: master device must provide a data hold time for SD (referred to V IL of SCL) to bridge the undefined region of SCL s falling edge (Figure ). Note 3: C B = total capacitance of one bus line in pf. t R, t FD, and t F measured between 0.3V DD and 0.7V DD. The minimum value is specified at T = +25 C with C B = 400pF. Note 4: f SCLH must meet the minimum clock low time plus the rise/fall times. 5

6 4-/-/2-Channel 2-Wire Serial -Bit DCs MX600 MX605 Typical Operating Characteristics (V DD = 3.3V (MX60/MX603/MX605), V DD = 5V (MX600/MX602/MX604), f SCL =.7MHz, external clock (33% duty cycle), f SMPLE = ksps, single ended, unipolar, T = +25 C, unless otherwise noted.) IDD (µ) IDD (µ) SUPPLY CURRENT vs. VOLTGE ) INTERNL 4.096V REF B) INTERNL 2.04V REF C) EXTERNL 4.096V REF D) EXTERNL 2.04V REF V DD (V) SHUTDOWN SUPPLY CURRENT vs. TEMPERTURE SD = SCL = V DD V DD = 5V V DD = 3.3V TEMPERTURE ( C) B C D MX600 toc0 MX600 toc04 IDD (µ) VERGE IDD (µ) SUPPLY CURRENT vs. TEMPERTURE INTERNL 4.096V REF INTERNL 2.04V REF EXTERNL 4.096V REF EXTERNL 2.04V REF TEMPERTURE ( C) VERGE SUPPLY CURRENT vs. CONVERSION RTE (INTERNL CLOCK) ) INTERNL REF LWYS ON B) INTERNL REF UTOSHUTDOWN C) EXTERNL REF CONVERSION RTE (ksps) B C INTERNL CLOCK MODE f SCL =.7MHz MX600 toc02 MX600 toc05 IDD (µ) VERGE IDD (µ) SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTGE SD = SCL = V DD V DD (V) VERGE SUPPLY CURRENT VS. CONVERSION RTE (EXTERNL CLOCK) ) INTERNL REF LWYS ON B) INTERNL REF UTOSHUTDOWN C) EXTERNL REF CONVERSION RTE (ksps) B C EXTERNL CLOCK MODE f SCL =.7MHz MX600 toc03 MX600 toc06 NORMLIZED 4.096V REFERENCE VOLTGE vs. SUPPLY VOLTGE MX600 toc INTERNL 4.096V REFERENCE VOLTGE vs. TEMPERTURE MX600 toc INTERNL 2.04V REFERENCE VOLTGE vs. SUPPLY VOLTGE MX600 toc09 VREF NORMLIZED VREF NORMLIZED VREF NORMLIZED V DD (V) TEMPERTURE ( C) V DD (V) 6

7 4-/-/2-Channel 2-Wire Serial -Bit DCs Typical Operating Characteristics (continued) (V DD = 3.3V (MX60/MX603/MX605), V DD = 5V (MX600/MX602/MX604), f SCL =.7MHz, external clock (33% duty cycle), f SMPLE = ksps, single ended, unipolar, T = +25 C, unless otherwise noted.) VREF NORMLIZED INTERNL 2.04V REFERENCE VOLTGE vs. TEMPERTURE TEMPERTURE ( C) MPLITUDE (dbc) MX600 toc0 DNL (LSB) FFT PLOT k 40k 60k 0k 00k FREQUENCY (Hz) DIFFERENTIL NONLINERITY vs. DIGITL CODE DIGITL OUTPUT CODE f SMPLE = ksps f IN = 25kHz MX600 toc3 OFFSET ERROR (LSB) MX600 toc INL (LSB) OFFSET ERROR vs. SUPPLY VOLTGE V REF = 2.04V V DD (V) INTEGRL NONLINERITY vs. DIGITL CODE DIGITL OUTPUT CODE MX600 toc4 MX600 toc2 MX600 MX605 OFFSET ERROR (LSB) OFFSET ERROR vs. TEMPERTURE V DD = 3.3V V REF = 2.04V TEMPERTURE ( C) MX600 toc5 GIN ERROR (LSB) GIN ERROR vs. SUPPLY VOLTGE V REF = 2.04V V DD (V) MX600 toc6 7

8 4-/-/2-Channel 2-Wire Serial -Bit DCs MX600 MX605 MX600 MX60 PIN MX602 MX603 MX604 MX605 NME, 2, 3 2,, 0 2,, 0 IN 0, IN, IN IN3 IN7 4, 3, 2 IN IN0 4 IN3/REF REF nalog Inputs FUNCTION Pin Description nalog Input 3/Reference Input/Output. Selected in the setup register (see Tables and 6). Reference Input/Output. Selected in the setup register (see Tables and 6). IN/REF nalog Input /Reference Input/Output. Selected in the setup register (see Tables and 6) SCL Clock Input SD Data Input/Output GND Ground 6 6 V DD Positive Supply. Bypass to GND with a 0.µF capacitor. 2, 3, 4 N.C. No Connection Detailed Description The MX600 MX605 DCs use successiveapproximation conversion techniques and input T/H circuitry to capture and convert an analog signal to a serial -bit digital output. The MX600/MX60 are 4-channel DCs, the MX602/MX603 are -channel DCs and the MX604/MX605 are 2-channel DCs. These devices feature a high-speed 2-wire serial interface supporting data rates up to.7mhz. Figure 3 shows the simplified functional diagram for the MX604/MX605. Power Supply The MX600 MX605 operate from a single supply and consume 350µ at sampling rates up to ksps. The MX60/MX603/MX605 feature a 2.04V internal reference and the MX600/MX602/ MX604 feature a 4.096V internal reference. ll devices can be configured for use with an external reference from V to V DD. nalog Input and Track/Hold The MX600 MX605 analog input architecture contains an analog input multiplexer (MUX), a T/H capacitor, T/H switches, a comparator, and a switched capacitor digital-to-analog converter (DC) (Figure 4). In single-ended mode, the analog input multiplexer connects C T/H to the analog input selected by CS[3:0] (see the Configuration/Setup Bytes (Write Cycle) section). The charge on C T/H is referenced to GND when converted. In pseudo-differential mode, the analog input multiplexer connects C T/H to the positive analog input selected by CS[3:0]. The charge on C T/H is referenced to the negative analog input when converted. The MX600 MX605 input configuration is pseudo-differential in that only the signal at the positive analog input is sampled with the T/H circuitry. The negative analog input signal must remain stable within ±0.5 LSB (±0. LSB for best results) with respect to GND during a conversion. To accomplish this, connect a 0.µF capacitor from the negative analog input to GND. See the Single-Ended/Pseudo-Differential Input section. During the acquisition interval, the T/H switches are in the track position and C T/H charges to the analog input signal. t the end of the acquisition interval, the T/H switches move to the hold position retaining the charge on C T/H as a sample of the input signal. During the conversion interval, the switched capacitive DC adjusts to restore the comparator input voltage to zero within the limits of -bit resolution. This action requires eight conversion clock cycles and is equivalent to transferring a charge of pf (V IN + - V IN -) from C T/H to the binary weighted capacitive DC, forming a digital representation of the analog input signal. Sufficiently low source impedance is required to ensure an accurate sample. source impedance below.5kω does not significantly degrade sampling accuracy. To

9 4-/-/2-Channel 2-Wire Serial -Bit DCs a) F/S-MODE I 2 C SERIL-INTERFCE TIMING SD t SU.DT t HD.DT thd.st t LOW t SU.ST SCL t HD.ST t HIGH t R t F S Sr b) HS-MODE I 2 C SERIL-INTERFCE TIMING SD t LOW t SU.DT t HD.DT t SU.ST t HD.ST SCL t HD.ST t HIGH t RCL t FCL t SU.STO t RD t SU.STO t RCL t R P t BUF t BUF t F t S t FD MX600 MX605 S Sr S HS MODE F/S MODE Figure. I 2 C Serial-Interface Timing minimize sampling errors with higher source impedances, connect a 00pF capacitor from the analog input to GND. This input capacitor forms an RC filter with the source impedance limiting the analog input bandwidth. For larger source impedances, use a buffer amplifier to maintain analog input signal integrity. When operating in internal clock mode, the T/H circuitry enters its tracking mode on the ninth falling clock edge of the address byte (see the Slave ddress section). The T/H circuitry enters hold mode two internal clock cycles later. conversion or a series of conversions is then internally clocked (eight clock cycles per conversion) and the MX600 MX605 hold SCL low. When operating in external clock mode, the T/H circuitry enters track mode on the seventh falling edge of a valid slave address byte. Hold mode is then entered on the falling edge of the eighth clock cycle. The conversion is performed during the next eight clock cycles. The time required for the T/H circuitry to acquire an input signal is a function of input capacitance. If the analog input source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. The acquisition time (t CQ ) is the minimum time needed for the signal to be acquired. It is calculated by: SD Figure 2. Load Circuit V DD I OL = 3m I OH = 0m V OUT 400pF t CQ 6.25 (R SOURCE + R IN ) C IN where R SOURCE is the analog input source impedance, R IN = 2.5kΩ, and C IN = pf. t CQ is /f SCL for external clock mode. For internal clock mode, the acquisition time is two internal clock cycles. To select R SOURCE, allow 625ns for t CQ in internal clock mode to account for clock frequency variations. 9

10 4-/-/2-Channel 2-Wire Serial -Bit DCs MX600 MX605 SD SCL V DD GND IN0 IN IN2 IN3 IN4 IN5 IN6 IN7 IN IN9 IN0 IN/REF INPUT SHIFT REGISTER NLOG INPUT MUX SETUP REGISTER CONFIGURTION REGISTER T/H REF -BIT DC REFERENCE 4.096V (MX604) 2.04V (MX605) CONTROL LOGIC INTERNL OSCILLTOR OUTPUT SHIFT REGISTER ND 2-BYTE RM MX604 MX605 THE MX600/MX60/MX604/MX605 USE THE SME PIN FOR IN_ ND REF, WHILE THE MX602/MX603 USE DIFFERENT PINS. SEE THE PIN DESCRIPTION SECTION. Figure 3. MX604/MX605 Simplified Functional Diagram NLOG INPUT MUX REF C T/H IN0 IN TRCK TRCK HOLD HOLD CPCITIVE DC IN2 IN3/REF DIFFERENTIL SINGLE ENDED GND MX600 MX60 Figure 4. Equivalent Input Circuit nalog Input Bandwidth The MX600 MX605 feature input tracking circuitry with a 2MHz small signal bandwidth. The 2MHz input bandwidth makes it possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the DC s sampling rate by using undersampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. nalog Input Range and Protection Internal protection diodes clamp the analog input to V DD and GND. These diodes allow the analog inputs to swing from (GND - 0.3V) to (V DD + 0.3V) without causing damage to the device. For accurate conversions, the inputs must not go more than 50mV below GND or above V DD. If the analog input exceeds V DD by more than 50mV, the input current should be limited to 2m. 0

11 4-/-/2-Channel 2-Wire Serial -Bit DCs Table. Setup Byte Format BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT REG SEL2 SEL SEL0 CLK BIP/UNI RST X BIT NME DESCRIPTION 7 REG Register bit. = setup byte, 0 = configuration byte (Table 2). 6 SEL2 Three bits select the reference voltage and the state of IN_/REF 5 SEL (MX600/MX60/MX604/MX605) or REF (MX602/MX603) (Table 6). 4 SEL0 Default to 000 at power-up. 3 CLK = external clock, 0 = internal clock. Defaulted to zero at power-up. 2 BIP/UNI = bipolar, 0 = unipolar. Defaulted to zero at power-up (see the Unipolar/Bipolar section). Single-Ended/Pseudo-Differential Input The SGL/DIF bit of the configuration byte configures the MX600 MX605 analog input circuitry for singleended or pseudo-differential inputs (Table 2). In singleended mode (SGL/DIF = ), the digital conversion results are the difference between the analog input selected by CS[3:0] and GND (Table 3). In pseudo-differential mode (SGL/DIF = 0), the digital conversion results are the difference between the positive and the negative analog inputs selected by CS[3:0] (Table 4). The negative analog input signal must remain stable within ±0.5 LSB (±0. LSB for best results) with respect to GND during a conversion. Unipolar/Bipolar When operating in pseudo-differential mode, the BIP/ UNI bit of the setup byte (Table ) selects unipolar or bipolar operation. Unipolar mode sets the differential analog input range from zero to V REF. negative differential analog input in unipolar mode causes the digital output code to be zero. Selecting bipolar mode sets the differential input range to ±V REF /2, with respect to the negative input. The digital output code is binary in unipolar mode and two s complement binary in bipolar mode (see the Transfer Functions section). In single-ended mode, the MX600 MX605 always operate in unipolar mode regardless of the BIP/UNI setting, and the analog inputs are internally referenced to GND with a full-scale input range from zero to V REF. BIT 0 (LSB) RST = no action, 0 = resets the configuration register to default. Setup register remains unchanged. 0 X Don t care; can be set to or 0. Digital Interface The MX600 MX605 feature a 2-wire interface consisting of a serial-data line (SD) and a serial-clock line (SCL). SD and SCL facilitate bidirectional communication between the MX600 MX605 and the master at rates up to.7mhz. The MX600 MX605 are slaves that transmit and receive data. The master (typically a microcontroller) initiates data transfer on the bus and generates SCL to permit that transfer. SD and SCL must be pulled high. This is typically done with pullup resistors (500Ω or greater) (see Typical Operating Circuit). Series resistors (R S ) are optional. They protect the input architecture of the MX600 MX605 from high-voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL clock cycle. Nine clock cycles are required to transfer the data in or out of the MX600 MX605. The data on SD must remain stable during the high period of the SCL clock pulse. Changes in SD while SCL is high are control signals (see the STRT and STOP Conditions section). Both SD and SCL idle high when the bus is not busy. STRT and STOP Conditions The master initiates a transmission with a STRT condition (S), a high-to-low transition on SD with SCL high. The master terminates a transmission with a STOP condition (P), a low-to-high transition on SD, while MX600 MX605

12 4-/-/2-Channel 2-Wire Serial -Bit DCs MX600 MX605 SCL is high (Figure 5). repeated STRT condition (Sr) can be used in place of a STOP condition to leave the bus active and in its current timing mode (see the HS Mode section). cknowledge Bits Successful data transfers are acknowledged with an acknowledge bit () or a not-acknowledge bit (). Both the master and the MX600 MX605 (slave) generate acknowledge bits. To generate an acknowledge bit, the receiving device must pull SD low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (Figure 6). To generate a not acknowledge bit, the receiver allows SD to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves it high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. n unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. Slave ddress bus master initiates communication with a slave device by issuing a STRT condition followed by a slave address. When idle, the MX600 MX605 continuously wait for a STRT condition followed by their slave address. When the MX600 MX605 recognize their slave address, they are ready to accept or send data. The slave address has been factory programmed and is always 0000 for the MX600/ MX60, 00 for MX602/MX603, and 000 for MX604/MX605 (Figure 7). The least significant bit (LSB) of the address byte (R/W) determines whether the master is writing to or reading from the MX600 MX605 (R/W = zero selects a write condition. R/W = selects a read condition). fter receiving the address, the MX600 MX605 (slave) issue an acknowledge by pulling SD low for one clock cycle. Bus Timing t power-up, the MX600 MX605 bus timing defaults to fast mode (F/S mode), allowing conversion rates up to 44ksps. The MX600 MX605 must operate in high-speed mode (HS mode) to achieve conversion rates up to ksps. Figure shows the bus timing for the MX600 MX605 2-wire interface. HS Mode t power-up, the MX600 MX605 bus timing is set for F/S mode. The master selects HS mode by SD SCL S Figure 5. STRT and STOP Conditions SD SCL S Figure 6. cknowledge Bits Sr NOT CKNOWLEDGE CKNOWLEDGE 2 9 addressing all devices on the bus with the HS mode master code 0000 XXX (X = don t care). fter successfully receiving the HS-mode master code, the MX600 MX605 issues a not acknowledge, allowing SD to be pulled high for one clock cycle (Figure ). fter the not acknowledge, the MX600 MX605 are in HS mode. The master must then send a repeated STRT followed by a slave address to initiate HS mode communication. If the master generates a STOP condition, the MX600 MX605 return to F/S mode. Configuration/Setup Bytes (Write Cycle) Write cycles begin with the master issuing a STRT condition followed by 7 address bits (Figure 7) and write bit (R/W = zero). If the address byte is successfully received, the MX600 MX605 (slave) issue an acknowledge. The master then writes to the slave. The slave recognizes the received byte as the setup byte (Table ) if the most significant bit (MSB) is. If the MSB is zero, the slave recognizes that byte as the configuration byte (Table 2). The master can write either or 2 bytes to the slave in any order (setup byte then configuration byte; configuration byte then setup byte; setup byte only; configuration byte only; Figure 9). If the slave receives bytes successfully, it issues an acknowledge. The master ends the write cycle by issuing a STOP condition or a repeated STRT condition. When operating in HS mode, a STOP condition returns the bus to F/S mode (see the HS Mode section). P 2

13 4-/-/2-Channel 2-Wire Serial -Bit DCs SD SCL S DEVICE MX600/MX60 MX602/MX603 MX604/MX605 Figure 7. Slave ddress Byte S SLVE DDRESS SLVE DDRESS R/W HS MODE MSTER CODE X X X Sr MX600 MX605 SD SCL F/S MODE HS MODE Figure. F/S Mode to HS Mode Transfer Data Byte (Read Cycle) read cycle must be initiated to obtain conversion results. Read cycles begin with the bus master issuing a STRT condition followed by 7 address bits and a read bit (R/W = ). If the address byte is successfully received, the MX600 MX605 (slave) issue an acknowledge. The master then reads from the slave. fter the master has received the results, it can issue an acknowledge if it wants to continue reading or a not acknowledge if it no longer wishes to read. If the MX600 MX605 receive a not acknowledge, they release SD, allowing the master to generate a STOP or repeated STRT. See the Clock Mode and Scan Mode sections for detailed information on how data is obtained and converted. Clock Mode The clock mode determines the conversion clock, the acquisition time, and the conversion time. The clock mode also affects the scan mode. The state of the setup byte s CLK bit determines the clock mode (Table ). t power-up, the MX600 MX605 default to internal clock mode (CLK = zero). Internal Clock When configured for internal clock mode (CLK = zero), the MX600 MX605 use their internal oscillator as the conversion clock. In internal clock mode, the MX600 MX605 begin tracking analog input on the ninth falling clock edge of a valid slave address byte. Two internal clock cycles later, the analog signal is acquired and the conversion begins. While tracking and converting the analog input signal, the MX600 MX605 hold SCL low (clock stretching). fter the conversion completes, the results are stored in 3

14 4-/-/2-Channel 2-Wire Serial -Bit DCs MX600 MX605 Figure 9. Write Cycle S MSTER TO SLVE SLVE TO MSTER. -BYTE WRITE CYCLE 7 SLVE DDRESS W SETUP OR CONFIGURTION BYTE MSB DETERMINES WHETHER SETUP OR CONFIGURTION BYTE B. 2-BYTE WRITE CYCLE 7 SETUP OR S SLVE DDRESS W CONFIGURTION BYTE MSB DETERMINES WHETHER SETUP OR CONFIGURTION BYTE P OR Sr SETUP OR CONFIGURTION BYTE NUMBER OF BITS P OR Sr NUMBER OF BITS random access memory (RM). If the scan mode is set for multiple conversions, they all happen in succession with each additional result being stored in RM. The MX600/MX60 contain bytes of RM, the MX602/MX603 contain bytes of RM, and the MX604/MX605 contain 2 bytes of RM. Once all conversions are complete, the MX600 MX605 release SCL, allowing it to be pulled high. The master can now clock the results out of the output shift register at a clock rate of up to.7mhz. SCL is stretched for a maximum acquisition and conversion time of 7.6µs per channel (Figure 0). The device RM contains all of the conversion results when the MX600 MX605 release SCL. The converted results are read back in a first-in-first-out (FIFO) sequence. If IN_/REF is set to be a reference input or output (SEL =, Table 6), IN_/REF is excluded from a multichannel scan. This does not apply to the MX602/MX603 as each provides separate pins for IN7 and REF. RM contents can be read continuously. If reading continues past the last result stored in RM, the pointer wraps around and points to the first result. Note that only the current conversion results are read from memory. The device must be addressed with a read command to obtain new conversion results. The internal clock mode s clock stretching quiets the SCL bus signal, reducing the system noise during conversion. Using the internal clock also frees the master (typically a microcontroller) from the burden of running the conversion clock. External Clock When configured for external clock mode (CLK = ), the MX600 MX605 use SCL as the conversion clock. In external clock mode, the MX600 MX605 begin tracking the analog input on the seventh falling clock edge of a valid slave address byte. One SCL clock cycle later, the analog signal is acquired and the conversion begins. Unlike internal clock mode, converted data is available immediately after the slave-address acknowledge bit. The device continuously converts input channels dictated by the scan mode until given a not acknowledge. There is no need to re-address the device with a read command to obtain new conversion results (Figure ). The conversion must complete in 9ms or droop on the T/H capacitor degrades conversion results. Use internal clock mode if the SCL clock period exceeds ms. The MX600 MX605 must operate in external clock mode for conversion rates up to ksps. Scan Mode SCN0 and SCN of the configuration byte set the scan-mode configuration. Table 5 shows the scanning configurations. If IN_/REF is set to be a reference input or output (SEL =, Table 6), IN_/REF is excluded from a multichannel scan. This does not apply to the MX602/MX603 as each provides separate pins for IN7 and REF. 4

15 4-/-/2-Channel 2-Wire Serial -Bit DCs Table 2. Configuration Byte Format BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT pplications Information Power-On Reset The configuration and setup registers (Tables and 2) default to a single-ended, unipolar, single-channel conversion on IN0 using the internal clock with V DD as the reference and IN_/REF (MX600/MX60/ MX604/MX605) configured as an analog input. For the MX602/MX603, the REF pin is floating after power-up. The RM contents are unknown after power-up. utomatic Shutdown SEL[2:0] of the setup byte (Tables and 6) controls the state of the reference and IN_/REF (MX600/ MX60/MX604/MX605) or REF (MX602/ MX603). If automatic shutdown is selected (SEL[2:0] = 00), shutdown occurs between conversions when the MX600 MX605 are idle. When operating in external clock mode, a STOP condition must be issued to place the devices in idle mode and benefit from automatic shutdown. STOP condition is not necessary in internal clock mode to benefit from automatic shutdown because powerdown occurs once all contents are written to memory (Figure 0). ll analog circuitry is inactive in shutdown and supply current is less than µ. The digital conversion results are maintained in RM during shutdown and are available for access through the serial interface at any time prior to a STOP or repeated STRT condition. When idle, the MX600 MX605 wait for a STRT condition followed by their slave address (see the Slave ddress section). Upon reading a valid address byte, the MX600 MX605 power up. The analog circuits do not require any wakeup time from shutdown, whether using external or internal reference. BIT 0 (LSB) REG SCN SCN0 CS3 CS2 CS CS0 SGL/DIF BIT NME DESCRIPTION 7 REG Register bit. = setup byte (Table ), 0 = configuration byte. 6 SCN 5 SCN0 4 CS3 3 CS2 2 CS CS0 0 SGL/DIF Scan select bits. Two bits select the scanning configuration (Table 5). Default to 00 at power-up. Channel select bits. Four bits select which analog input channels are to be used for conversion (Tables 3 and 4). Default to 0000 at power-up. For the MX600/MX60, CS3 and CS2 are internally set to 0. For the MX602/MX603, CS3 is internally set to zero. = single-ended, 0 = pseudo-differential (Tables 3 and 4). Default to at power-up (see the Single-Ended/Pseudo-Differential Input section). utomatic shutdown results in dramatic power savings, particularly at slow conversion rates. For example, at a conversion rate of 0ksps, the average supply current for the MX036 is µ and drops to 2µ at ksps. t 0.ksps the average supply current is just µ (see verage Supply Current vs. Conversion Rate in the Typical Operating Characteristics section). Reference Voltage SEL[2:0] of the setup byte (Table ) controls the reference and the IN_/REF (MX600/MX60/ MX604/MX605) or REF (MX602/MX603) configuration (Table 6). When IN_/REF (MX600/ MX60/MX604/MX605) is configured to be a reference input or reference output (SEL = ), conversions on IN_/REF appear as if IN_/REF is connected to GND (see note 2 of Tables 3 and 4). Internal Reference The internal reference is 4.096V for the MX600/ MX602/MX604 and 2.04V for the MX60/ MX603/MX605. SEL of the setup byte controls whether IN_/REF (MX600/MX60/MX604/ MX605) is used for an analog input or a reference (Table 6). When IN_/REF (MX600/MX60/ MX604/MX605) or REF (MX602/MX603) is configured to be an internal reference output (SEL[2:] = ), decouple IN_/REF (MX600/MX60/ MX604/MX605) or REF (MX602/MX603) to GND with a 0.0µF capacitor. Due to the decoupling capacitor and the 675Ω reference source impedance, allow 0µs for the reference to stabilize during initial power-up. Once powered up, the reference always remains on until reconfigured. The reference should not be used to supply current for external circuitry. When the MX602/MX603 is in shutdown, the internal reference output is in a high-impedance state. 5 MX600 MX605

16 4-/-/2-Channel 2-Wire Serial -Bit DCs MX600 MX605. SINGLE CONVERSION WITH INTERNL CLOCK S 7 SLVE DDRESS R CLOCK STRETCH B. SCN MODE CONVERSIONS WITH INTERNL CLOCK S MSTER TO SLVE SLVE TO MSTER t CQ 7 SLVE DDRESS t CQ R t CONV CLOCK STRETCH t CONV RESULT t CQ2 t CONV2 P or Sr CLOCK STRETCH t CQN t CONVN NUMBER OF BITS RESULT RESULT 2 RESULT N P OR Sr NUMBER OF BITS NOTE: t CQ + t CONV 7.6µs PER CHNNEL. Figure 0. Internal Clock Mode Read Cycles MSTER TO SLVE SLVE TO MSTER. SINGLE CONVERSION WITH EXTERNL CLOCK 7 NUMBER OF BITS S SLVE DDRESS R RESULT P OR Sr t CQ t CONV B. SCN MODE CONVERSIONS WITH EXTERNL CLOCK 7 NUMBER OF BITS S SLVE DDRESS R RESULT RESULT 2 RESULT N P OR Sr t CQ t CONV t CQ2 t CONV2 t CQN t CONVN Figure. External Clock Mode Read Cycles 6

17 4-/-/2-Channel 2-Wire Serial -Bit DCs Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = ) CS3 CS2 CS CS0 IN0 IN IN2 IN3 2 IN4 IN5 IN6 IN7 IN IN9 IN0 IN 2 GN D Reserved 0 Reserved 0 Reserved Reserved For the MX600/MX60, CS3 and CS2 are internally set to zero. For the MX602/MX603, CS3 is internally set to zero. 2 When SEL =, a single-ended read of IN3/REF (MX600/MX60) or IN/REF (MX604/MX605) returns GND. This does not apply to the MX602/MX603 as each provides separate pins for IN7 and REF. MX600 MX605 7

18 4-/-/2-Channel 2-Wire Serial -Bit DCs MX600 MX605 Table 4. Channel Selection in Pseudo-Differential Mode (SGL/DIF = 0) CS3 2 CS2 2 CS CS0 IN0 IN IN2 IN3 2 IN4 IN5 IN6 IN7 IN IN9 IN0 IN Reserved 0 Reserved 0 Reserved Reserved When scanning multiple channels (SCN0 = 0), CS0 = 0 causes the even-numbered channel-select bits to be scanned, while CS0 = causes the odd-numbered channel-select bits to be scanned. For example, if the MX604/MX605 SCN[:0] = 00 and CS[3:0] = 00, a pseudo-differential read returns IN0 IN, IN2 IN3, IN4 IN5, IN6 IN7, IN IN9, and IN0 IN. If the MX604/MX605 SCN[:0] = 00 and CS[3:0] = 0, a pseudo-differential read returns IN IN0, IN3 IN2, IN5 IN4, IN7 IN6, IN9 IN, and IN IN0. 2 For the MX600/MX60, CS3 and CS2 are internally set to zero. For the MX602/MX603, CS3 is internally set to zero. 3 When SEL =, a pseudo-differential read between IN2 and IN3/REF (MX600/MX60) or IN0 and IN/REF (MX604/MX605) returns the difference between GND and IN2 or IN0, respectively. For example, a pseudo-differential read of 0 returns the negative difference between IN0 and GND. This does not apply to the MX602/MX603 as each provides separate pins for IN7 and REF.

19 4-/-/2-Channel 2-Wire Serial -Bit DCs Table 5. Scanning Configuration SCN SCN0 SCNNING CONFIGURTION 0 0 Scans up from IN0 to the input selected by CS3 CS0 (default setting). 0 Converts the input selected by CS3 CS0 eight times.* 0 MX600/MX60: Scans upper half of channels. Scans up from IN2 to the input selected by CS and CS0. When CS and CS0 are set for IN0, IN, and IN2, the scanning stops at IN2 (MX600/MX60). MX602/MX603: Scans upper quartile of channels. Scans up from IN6 to the input selected by CS3 CS0. When CS3 CS0 is set for IN0 IN6, the scanning stops at IN6 (MX602/MX603). MX604/MX605: Scans upper half of channels. Scans up from IN6 to the input selected by CS3 CS0. When CS3 CS0 is set for IN0 IN6, the scanning stops at IN6 (MX604/MX605). Converts the channel selected by CS3 CS0.* *When operating in external clock mode, there is no difference between SCN[:0] = 0 and SCN[:0] = and converting continues until a not acknowledge occurs. Table 6. Reference Voltage, IN_/REF, and REF Format MX600 MX605 SEL2 SEL SEL0 REFERENCE VOLTGE IN_/REF (MX600/ MX60/ MX604/ MX605) REF (MX602/ MX603) INTERNL REFERENCE STTE 0 0 X V DD nalog input Not connected lways off 0 X External reference Reference input Reference input lways off 0 0 Internal reference nalog input Not connected utoshutdown 0 Internal reference nalog input Not connected lways on X Internal reference Reference output Reference output lways on X = Don t care. External Reference The external reference can range from.0v to V DD. For maximum conversion accuracy, the reference must be able to deliver up to 30µ and have an output impedance of kω or less. If the reference has a higher output impedance or is noisy, bypass it to GND as close as possible to IN_/REF (MX600/MX60/MX604/MX605) or REF (MX602/MX603) with a 0.µF capacitor. Transfer Functions Output data coding for the MX600 MX605 is binary in unipolar mode and two s complement binary in bipolar mode with LSB = V REF /2 N where N is the number of bits (). Code transitions occur halfway between successive-integer LSB values. Figures 2 and 3 show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively. 9

20 4-/-/2-Channel 2-Wire Serial -Bit DCs MX600 MX605 OUTPUT CODE REF INPUT VOLTGE (LSB) V REF LSB = OUTPUT CODE (TWO'S COMPLEMENT) REF NEGTIVE INPUT INPUT VOLTGE (LSB) V REF LSB = 256 Figure 2. Unipolar Transfer Function Figure 3. Bipolar Transfer Function R* = 5Ω 3V/5V V LOGIC = 3V/5V GND V DD *OPTIONL 0.µF GND MX600 MX605 SUPPLIES 3V/5V DGND DIGITL CIRCUITRY Figure 4. Power-Supply and Grounding Connections Layout, Grounding, and Bypassing For best performance, use PC boards. Wire-wrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. Do not run analog and digital lines parallel to each other, and do not lay out digital signal paths underneath the DC package. Use separate analog and digital PCB ground sections with only one star point (Figure 4) connecting the two ground systems (analog and digital). For lowest noise operation, ensure the ground return to the star ground s power supply is low impedance and as short as possible. Route digital signals far away from sensitive analog and reference inputs. High-frequency noise in the power supply (V DD ) could influence the proper operation of the DC s fast comparator. Bypass VDD to the star ground with a 0.µF capacitor located as close as possible to the MX600 MX605 power-supply pin. Minimize capacitor lead length for best supply-noise rejection, and add an attenuation resistor (5Ω) if the power supply is extremely noisy. 20

21 4-/-/2-Channel 2-Wire Serial -Bit DCs Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The INL is measured using the end point method. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of LSB. DNL error specification of less than LSB guarantees no missing codes and a monotonic transfer function. perture Jitter perture jitter (t J ) is the sample-to-sample variation in the time between the samples. perture Delay perture delay (td) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analogto-digital noise is caused by quantization error only and results directly from the DC s resolution (N bits): SNR = (6.02 N +.76)dB In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SIND) is the ratio of the fundamental input frequency s RMS amplitude to RMS equivalent of all other DC output signals. SIND (db) = 20 log (SignalRMS/NoiseRMS) Effective Number of Bits Effective number of bits (ENOB) indicates the global accuracy of an DC at a specific input frequency and sampling rate. n ideal DC s error consists of quantization noise only. With an input range equal to the DC s full-scale range, calculate the ENOB as follows: ENOB = (SIND -.76)/6.02 Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the input signal s first five harmonics to the fundamental itself. This is expressed as: THD= V + V + V + V 20 log / V where V is the fundamental amplitude, and V 2 through V 5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component. PROCESS: BiCMOS Chip Information MX600 MX605 2

22 4-/-/2-Channel 2-Wire Serial -Bit DCs MX600 MX605 TOP VIEW IN0 IN IN2 IN3/REF (REF) IN/REF (N.C.) IN0 (N.C.) IN9 (N.C.) IN IN Pin Configurations MX600 MX60 SOT23 MX602 MX V DD GND SD SCL V DD 5 GND 4 SD 3 SCL 2 IN0 NLOG INPUTS *OPTIONL Typical Operating Circuit IN0 IN IN2 IN3/REF 5V V DD MX600 MX605 GND 5V µc SD SCL SD SCL 5V *R S *R S R P R P IN6 6 IN IN5 IN4 7 QSOP 0 9 IN2 IN3 Package Information For the latest package outline information and land patterns, go to ( ) INDICTES PINS ON THE MX602/MX603. PCKGE TYPE PCKGE CODE DOCUMENT NO. SOT23 KCN QSOP E

23 4-/-/2-Channel 2-Wire Serial -Bit DCs REVISION NUMBER REVISION DTE DESCRIPTION Revision History PGES CHNGED 0 4/09 Introduction of the MX600/MX60/MX603 7/09 Introduction of the MX602/MX604/MX /0 Changed top mark on the MX600/MX60 MX600 MX605 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 20 San Gabriel Drive, Sunnyvale, C Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.