A Gb/s Gb/s Low-Power Receiver for MIPI-DigRF M-PHY with a Fast Settling Fully Digital Frequency Detection Loop in 0.

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1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.5, NO.4, AUGUST, 25 ISSN(Print) ISSN(Online) A.248 Gb/s 2.98 Gb/s Low-Power Receiver for MIPI-DigRF M-PHY with a Fast Settling Fully Digital Frequency Detection Loop in. μm CMOS Sang-Yun Kim, Juri Lee, Hyung-Gu Park, Young Gun Pu, Jae Yong Lee, and Kang-Yoon Lee Abstract This paper presents a.248 Gb/s 2.98 Gb/s low-power receiver MIPI-DigRF M-PHY with a fully digital frequency detection loop. MIPI-DigRF M-PHY should be operated in a very short training time which is. μs the for HS-G2B mode. Because of this short SYNC pattern, clock and data recovery (CDR) should have extremely fast locking time. Thus, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement a fast phase tracking loop. Also, a low power CDR architecture, deserializer and voltage controlled oscillator (VCO) are proposed to meet the low power requirement of MIPI-DigRF M-PHY. This chip is fabricated using a. μm CMOS process, and the die area is 6 μm x 25 μm. The power consumption of the receiver is 6 mw from the supply voltage of. V. The measured lock time of the CDR is less than 2 ns. The measured rms and peak jitter are ps p-p and 4.25 ps rms respectively for HS-G2 mode. Index Terms MIPI-DigRF M-PHY, low-power, clock and data recovery (CDR), fully digital frequency detection loop, fast phase tracking loop, bandwidth switching I. INTRODUCTION As the demand for next generation mobile devices and Manuscript received May. 29, 25; accepted Aug. 4, 25 College of Information and Communication Engineering, Sungkyunkwan University klee@skku.edu their design complexity increases, many mobile applications are adopting the common physical layer (PHY). This makes it possible to meet the requirements of complicated next generation mobile systems. Since various high-speed interfaces [-3] are required for camera and video applications, the design requirements can be relaxed and the use of the common high-speed interface can reduce the development time for complicated mobile systems. MIPI-DigRF M-PHY is the one of the most popular common high-speed interface standards for many applications in the mobile area. M-PHY serial links have been developed for a broad range of applications such as in displays, cameras and mobiles. In this case, the system to be introduced is targeted at mobile applications. The data rate of M-PHY for mobile is up to 5.8 Gb/s (.45/2.9/5.8 Gb/s). The MIPI-DigRF M-PHY can provide high bandwidth with low power consumption using only a small number of pins making it ideal for many mobile applications. Common high-speed interfaces, such as MIPI-DigRF M- PHY need to provide interoperability at the interface level between different integrated circuits. Also, it can support many variables at the system design level and can be expanded to other systems efficiently. MIPI- DigRF M-PHY is composed of a digital controller block and analog block. The digital controller controls the overall operation of the M-PHY communicating with the protocol layer. At the analog receiver side, serial data from the other M-PHYs is deserialized to be transferred to the protocol layer. Low power consumption is one of the key features of MIPI-DigRF M-PHY since it operates using battery power.

2 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.5, NO.4, AUGUST, Table. Specification of MIPI-DigRF M-PHY Interface Mode Mnemonic Reference Frequency (MHz) Interface Rate (Mbps) Low Speed LS Mode (SYS-BURST) 26 / 38.4 / / 38.4 / 52 High Speed x High Speed 2x Length of SYNC Pattern Time for Gear/Rate Change HS-Gx (HS-BURST) HS-G2x (HS-BURST2) HS-GA 26 / 38.4 / HS-GB 26 / HS-G2A 26 / 38.4 / HS-G2B to 5 SI (default length of 3 SI) ( SI (Symbol Interval) = UI (Unit Interval)) μs 26 / REF_CLK Protocol Side 8 RX_Symbol Rx_ SymbolClk Rx Control & Interface Rx FSM FSM State Comma Detector HS Deserializer LS Deserializer _ST CDR LS_P LS_N HS P HS N INPUT BUFFER Rx_DP Rx_DN Line Side Receiver Fig.. Top block diagram of the receiver for MIPI-DigRF M-PHY. Table summarizes the specification of MIPI-DigRF M-PHY. The MIPI-DigRF M-PHY supports three different interface modes: low speed mode and high speed mode. It should support different interface data rates according to the interface mode and clocks of 26 MHz, 38.4 MHz and 52 MHz. The MIPI-DigRF M-PHY should be operated in 3 symbol interval (SI) training time which is very short compared with other interfaces such as display port [4-7]. The length of the SYNC pattern is 3 SI (= 3 UI (unit intervals)), which is. μs in HS-G2B mode. Due to this short SYNC pattern, clock and data recovery (CDR) in the receiver should have an extremely fast locking time [8, 9]. This paper presents, a low-power receiver for MIPI- DigRF M-PHY with a wide data rate of.248 Gb/s 2.98 Gb/s. Section II describes the receiver architecture. Section III discusses the building blocks of the receiver. Section IV shows the experimental results while Section V summarizes the paper. II. MIPI-DIGRF M-PHY RECEIVER ARCHITECTURE Fig. shows the block diagram of the low-power receiver for MIPI-DigRF M-PHY. The receiver transfer the data between the protocol side and line side. The MIPI-DigRF M-PHY communicates 8-bit data with the protocol layer in different gears and rates based on the control signals (HSGEAR<:> and HSRATE<:>) from the protocol layer. The MIPI-DigRF M-PHY has two gear modes, G/G2 and two rate modes, A/B, leading to four operating modes. The receiver is composed of the Rx control & data interface, comma detector, HS deserializer, LS deserializer, CDR, and input buffer. It recovers the clock and data based on serial data from the line side. The recovered data from the CDR is deserialized into -bit parallel data. A comma detector should detect comma data, or SYNC patterns, from the data which is the output from the deserializer [, ]. The first real data from the transmitter cannot be identified from the output of the

3 58 SANG-YUN KIM et al : A.248 GB/S 2.98 GB/S LOW-POWER RECEIVER FOR MIPI-DIGRF M-PHY WITH A FAST SETTLING RX_DP/DN DIF_N PREPARE SYNC Control Bits DATA Control Bits TOB Rx_Burst Rx_SymbolClk Rx_Symbol<7:> ST Control Bits DATA Control Bits Fig. 2. Timing diagram of receiver for MIPI-DigRF M-PHY. deserializer. Therefore, it is necessary to detect the SYNC patterns at the comma detector, in this way -bit real data can be recovered correctly according to the detected SYNC pattern. -bit parallel data is decoded to 8-bit parallel data by the Rx control and data interface and transferred to the protocol layer. Fig. 2 is the timing diagram of the receiver for MIPI- DigRF M-PHY. The data from the protocol layer includes real data and control bits as well as control information for states of the finite state machine (FSM). The DIF_N signal is the initial value of RX_DP/DN. PREPARE and SYNC are transferred before the control bits and real data, these are used to initialize the analog blocks of MIPI-DigRF M-PHY. The SYNC pattern is used for clock recovery before data transmission. After the SYNC pattern, the start (ST) signal of the symbols from the transmitter is received. Then, control bits and real data are transferred. On the receiver side, control signals and real data sent from the transmitter are received through the transmission line. The internal symbol clock (Rx_SymbolClk) is generated and the Rx_Burst signal becomes high when the SYNC patterns are sent from the transmitter. Control signals and real data are sent from the transmitter and are recovered by the CDR. The recovered control signals and real data are used by the RX_FSM in the receiver to provide 8-bit data, Rx_Symbol<7:>, to the protocol side. III. BUILDING BLOCKS. Clock and Recovery The CDR circuit is an important block for optical and electrical communications [2]. It is used to recover and retime the required clock from data. However, it is still a very challenging task to design high speed and low power CDRs. The phase detector (PD) is a critical block in the unit as it limits the performance of the CDR s speed. The speed performance of the CMOS is limited when compared to other high-speed technologies such as SiGe. Lowering the clock frequency relaxes the speed limit imposed by the CMOS. In this work, a quarter-rate PD is used to mitigate the operating speed of the PD in the CDR circuit. The main disadvantage of a lower-rate linear PD is that its complexity increases when the rate decreases. This will involve additional circuits such as a clock tree to compensate for the delay time and result in higher power consumption. Also, a large number of outputs would require more charge pump (CP) blocks, which may lead to severe current mismatches in the CP circuits. As the circuit structure of the quarter-rate PD is still very complex, this paper focuses on minimizing the complexity and output signals of the linear PD in the quarter-rate design without compromising good performance and low power consumption. Fig. 3 shows the block diagram of the proposed CDR circuit. It employs a dual-loop CDR architecture with a frequency detection loop and a phase tracking loop which help to prevent false locking. The phase tracking loop is composed of a quarter-rate PD, four CPs, a second order loop filter, bandwidth (BW) switching control block, a quadrature voltage controlled oscillator (VCO) and data recovery circuit. The SYNC pattern time of the MIPI-DigRF M-PHY is 3 SI, which is very short compared with other interfaces. Therefore, CDR has to lock the frequency and phase very quickly in a 3 SI SYNC pattern. When the loop bandwidth of the CDR is increased, the locking time is reduced. Unfortunately, the wide bandwidth allows noise sources to be translated into output jitter. It is important that the CDR has good output jitter performance after locking. To meet the jitter specification and locking time of the CDR, a CDR using a bandwidth switching method is

4 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.5, NO.4, AUGUST, /4 rate PD R_ <3:> UP CP DN UP CP DN UP2 CP DN2 UP3 CP DN3 BW_SW SW C2 C DATA_ST BW Switching Control Block BW_SW, BW_SWB BW_ SWB SW3 R VCTRL RZ BW_ SW R2 SW2 Deserializer ~ 4-Phase Recovered clock Table 2. Loop Parameters of the CDR Parameters BW =5 MHz BW = MHz Units I CP. ma C P pf R Z ohm C Z pf Frequency Detection Block REF_CLK 2nd order Loop Filter CP 4-Phase Recovered clock (CK - CK3) C3 C4 FCONT<M:>, CAP_CON<K:> CZ REF_CLK VCO_DIVK EN_CNT COM_CLK DEN_CLK RST_CNT Frequency Detection Loop Phase Tracking Loop Fig. 3. Quarter-Rate CDR architecture with full digital frequency detection. FCONT<M:>... CAP_CON<K:>... FREQ_LOCK DATA PREPARE SYNC(3SI) _ST proposed. The bandwidth switching method is to widen the loop bandwidth during the locking operation of the CDR, and to narrow the loop bandwidth after the locking operation. Initially, the bandwidth of CDR circuit is set to be wide for the fast phase locking time. After the SYNC pattern, the bandwidth is switched to have a narrow value for the stable phase locking operation by changing the charge pump current, capacitor values and resistor values in the loop filter. The bandwidth of the CDR with a second order loop filter can be written as follows: ICP KVCO Rz Cz w c = 2p N C + C The ω C, K VCO, N, and I CP are bandwidth of CDR, VCO gain, division ratio, and CP current, respectively. Also, R Z, C Z and C P are the resistors and capacitors of the second order loop filter. In Eq. (), the bandwidth is determined by the parameters of the second order loop filter. In Fig. 3, SW, SW 2, and SW 3 are turned on when the control signal (BW_SW or BW_SWB) is VDD, which is high. On the other hand, they are turned off when the control signal (BW_SW or BW_SWB) is GND, which is low. The BW_SWB signal has an inverse relationship with the BW_SW signal. When the BW_SW is low, SW and SW 2 are turned off. Simultaneously, SW 3 is turned on because BW_SWB is high. Then, C P, C Z and R Z of the second order loop filter become C, C 3 and R, respectively. This is the high bandwidth mode. On the z p () BW_SW BW_SWB Fig. 4. Timing diagram of the frequency detection loop and phase tracking loop. other hand, when the BW_SW signal is high, SW and SW 2 are turned on and SW 3 is turned off. Therefore, the values of C P, C Z and R Z are changed to C +C 2, C 3 +C 4, and R + R 2. This is the low bandwidth mode. Initially the BW_SW signal is low, and it becomes high after a 3 SI training pattern. If only the capacitor and the resistor are changed for the bandwidth switching, there will be a stability problem. In this paper, the CP current, I CP, is also controlled when the bandwidth is switched. As a result, size variation of the capacitor and resistor can be reduced. In this paper, the CDR locks the frequency and phase at a bandwidth of 5 MHz in the high bandwidth mode. Subsequently, the bandwidth is switched to MHz, which is the low bandwidth mode. The loop parameters of each bandwidth mode are summarized in Table 2. Fig. 4 shows the timing diagram of the frequency detection loop and phase tracking loop. Firstly, in the frequency detection loop, the CDR detects the target frequency that needs to be recovered before the SYNC pattern data is applied. The frequency detection loop is a digital block. It detects the target frequency by controlling FCONT<M:> and CAP_CON<K:>. The FREQ_LOCK signal becomes high when the frequency detection loop process is finished. Subsequently, the phase tracking loop detects the phase using the SYNC pattern input. The phase tracking loop is composed of the PD, CP and loop filter. In order to

5 5 SANG-YUN KIM et al : A.248 GB/S 2.98 GB/S LOW-POWER RECEIVER FOR MIPI-DIGRF M-PHY WITH A FAST SETTLING overcome the disadvantages of a conventional linear PD, a quarter-rate PD is adopted. The operating speed of each PD can be reduced by a factor of four. After the SYNC pattern is applied, the Rx controller creates a _ST signal which starts the real data being transmitted. When the _ST signal becomes high, the CDR bandwidth is switched and BW_SW becomes high Fig. 5(a) shows the block diagram of the frequency detection loop. The frequency detection loop works with the reference clock signal (REF_CLK) to generate RST_CNT, EN_CNT, DEN_CLK, and COM_CLK signals. In the fully digital frequency detection loop, the N-bit counter is used to estimate the period of the VCO frequency which results in VCO_CNT<N:>. Then VCO_CNT<N:> is compared to the reference counting value, COMP_REF<N:> which is generated from the mapping table. At each stage, the frequency control signal (FCONT<M:>, CAP_CON<K:>) is determined digitally based on the comparison result. After frequency calibration, the control voltage of VCO is adjusted to fine-tune the phase of the VCO. Fig. 5(b) shows the timing diagram of the frequency detection loop. The N-bit counter is periodically reset by the RST_CNT signal. This counting operation is masked by the EN_CNT signal. The N-bit counter is enabled only when EN_CNT is high. When the output of the counter is smaller than the reference counting value, COMP_REF<N:>, the UP signal is asserted at the rising edge of COM_CLK to increase the frequency of the VCO. The UP/DOWN signals are used to decide the frequency control signals in the frequency detection loop. The tuning controller in the frequency detection loop determines the current FCONT<M:>, and the capacitances, CAP_CON<K:>. FCONT<M:> is the MSB control bits of VCO and is the VCO frequency coarse control signal. After FCONT<M:> controls the VCO frequency coarsely, the VCO frequency is controlled finely by CAP_CONT<K:> signals. Fig. 6(a) shows the block diagram of a quarter-rate phase detector. It consists of four latches, two AND gates and two exclusive-or (XOR) gates. The data is latched by four phase clocks (CK-CK3) and each latch output D, D, Q and Q, respectively. D /D and Q /Q pass through the XOR gate and AND gate and give UP and DN, respectively. At this time, UP and DN are Coarse_Lock REF_CLK EN_CNT VCO_DIVK COM_CLK DEN_CLK RST_CNT Voltage Generator VCTRL ~ VCO REF_CLK REF_SEL<:> VCO_OUT VCO_OUTB FCONT<M:> generated with CK 2 and CK. To compensate for the demerits of conventional linear and nonlinear phase /2 Reference Divider EXT_COMP_EN (a) FCONT<M:>, CAP_CONT<K:> RST_CNT VCO/2 MSK_CNT N-bit Counter Digital COM_CLK Comparator DEN_CLK EXT_REF<N:> MUX VCO-CNT<N:> UP/DN COMP_REF<N:> Mapping Table REF_DIV<N:> INT_REF<N:> Tuning Controller CAP_CON<K:> (b) Freq_Sel Fig. 5. (a) Block diagram of fully digital frequency detection, (b) Timing diagram of frequency detection loop. D Q D Latch CK2 CLK QB D Q D Latch CK3 CLK QB CK CK CK2 CK3 Q Q CK CLK CK D Q D Latch QB UP D Q D Latch CK CLK QB (a) D D CK2 8 9 Q Q UP D 3 7 D DN (b) 4 8 Fig. 6. (a) Block diagram of quarter-rate phase detector, (b) timing diagram of the phase tracking loop. DN

6 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.5, NO.4, AUGUST, 25 5 detectors, a quarter-rate phase detector is used for linear output and a wide output signal width at high frequency. Since this can also reduce the burden of designing a phase tracking loop, the quarter-rate phase detector offers highly reliable operation at high frequencies. Fig. 6(b) shows the timing diagram of the phase tracking loop. UP and DN signals are generated based on the four phase clocks, CK CK 3. Q and Q are outputs of the latches which are latched by CK 2 and CK 3, respectively. These two signals pass through the XOR gate and AND gate with CK. Therefore, the UP signal becomes high when Q and Q are different from each other while CK is high. As shown in Fig. 6(b), when the phase is locked, the UP signal becomes high for three quarters of the pulse width of CK. If the VCO frequency is faster than the data rate, the time when Q and Q are different decreases while CK is high which leads the duration where UP is high is decreased. On the other hand, when the VCO frequency is slower than the data rate, the time when Q and Q are different increases while CK is high, so the time when UP is high increases. D and D signals pass through an XOR gate and the outputs of the XOR gate and CK 2 pass through an AND gate which leads to the output DN. Therefore, the DN signal is high when the D signal is different from D while CK 2 is high. D and D are the latch outputs latched by CK, CK, respectively, using Q and Q that are latched by CK 2, CK 3, respectively. As a result, D and D signals are always different from the other. Consequently, when CK 2 is high, the DN signal is always high regardless of the phase difference between the VCO clock and the input data. As mentioned above, the time when UP is high can be changed according to the phase difference between the data rate and the VCO frequency, while the DN signal is fixed. The PD is operated by the variation of the high duration of the UP signal. For example, when the VCO frequency is faster than the data rate, the high time of the UP signal decreases. Then, the UP current, which is generated by the charge pump is decreased and V CTRL is also decreased through the loop filter. As a result, the VCO frequency decreases. On the other hand, the VCO frequency is increased when the high time of UP increases. When the phase locking process of the CDR is complete, the pulse width ratio of the UP and DN is determined to be.5:2. If the charging and discharging current ratio of the charge pump is 2:.5, the net charge from the charge pump will be zero. 2. Voltage Controlled Oscillator Generally, the VCO gain of ring-type VCOs [3, 4] is designed to be large since its frequency is very sensitive to process, voltage and, temperature (PVT) variations. However, if the VCO gain is too large, the jitter specification cannot be satisfied. As shown in Fig. 7(a), if the VCO gain is large, it is possible to cover the overall frequency range using the K+ capacitors. However, As shown in Fig. 7(b), if the VCO gain is small to reduce jitter performance, it is impossible to cover the overall frequency range using the same K+ capacitors. Therefore, to cover the overall frequency range with a small VCO gain, a great number of VCO curves should be implemented using current arrays and capacitor arrays. Also, the resolution of the frequency detection loop Frequency Fmax Fmin Overall Frequency Range Slope=KVCO=2*A MHz/V CAP_CONT<N:>=All CAP_CONT<N:>=All VDD/2 VDD Frequency Fmax Fmin Overall Frequency Range K+ Cap Frequency Range (a) Slope=KVCO=A MHz/V FCONT<M:>=All CAP_CONT<N:>=All CAP_CONT<N:>=All FCONT<M:>=All VDD/2 VDD (b) V_CTRL V_CTRL Fig. 7. The tuning curve of (a) high gain VCO, (b) low gain VCO.

7 52 SANG-YUN KIM et al : A.248 GB/S 2.98 GB/S LOW-POWER RECEIVER FOR MIPI-DIGRF M-PHY WITH A FAST SETTLING needs to be as small as possible since the nominal duration of the SYNC pattern during the phase tracking is 3 SI. As the accuracy of the frequency detection loop is increased, the time for phase tracking will be reduced. In this paper, the VCO frequency is controlled by the current control signal (FCONT<M:>) and capacitor control signal (CAP_CON<N:>). In this way, the VCO can compensate for PVT variation even if the VCO has low gain. The jitter performance of the VCO is also improved due to the low VCO gain. The ring-type VCO shown in Fig. 8(a) is composed of four differential delay cells with dual inputs. Fig. 8(b) shows the delay cell of the VCO. The frequency control VIN2 VIN VINB VIN2B OUTB OUT CAP_CON<K:> 2nd order Loop Filter VCTRL VIN2B VIN2 VIN VINB VIN2B OUTB VIN st Coarse Tuning (Wide-Frequency Range Tuning) FCONT is determined. 2nd Coarse Tuning (Fine-Frequency Range Tuning) CAP_CON<K:> is determined. CK OUTB OUT CK2 MODE_SEL M3 M M7 M5 (a) VDD VCTRL (b) VIN2 VIN VINB VIN2B M8 M6 Frequency Frequency (c) CAP_CON <K:> OUTB OUT Frequency Detection Block VIN2 VIN VINB VIN2B FCONT<M:> M4 OUT M2 VIN2 VINB FCONT FCONT <M:> CK OUTB OUT CK3 Center Frequency CAP_CON<K:> Wide-Tuning Range FCONT<M:> CAP_CON<N:> Fine-Tuning Range Fig. 8. (a) Voltage controlled oscillator, (b) delay cell, (c) the tuning curve of the VCO. signals, FCONT<N:> and CAP_CON<N:>, are used to calibrate the frequency. The tuning controller in the frequency detection loop determines a current according to the FCONT<N:>, and a capacitance according to the CAP_CON<N:>. FCONT<N:> and CAP_CON<N:> are controlled by the frequency detection loop. FCONT<N:> as the MSB controls the frequency coarsely. When using the capacitor to control frequency coarsely, its size becomes extremely large due to the large capacitor size. To prevent this problem, a current control technique is proposed to control the frequency. By controlling current with the control signal FCONT<N:> to change the frequency, the size due to the large capacitors can be reduced. After detecting the frequency coarsely with FCONT<N:>, fine tuning with CAP_CON<N:> can be performed to detect the frequency accurately. Dual mode VCO is implemented to support the HS-G and HS-G2 mode by just controlling the tail current tuning bit, MODE_SEL, as shown in Fig. 8(b). When MODE_SEL is, the output frequency of the VCO corresponds to the HS-G mode. On the other hand, the output frequency of the VCO corresponds to the HS-G2 mode with a larger tail current compared to the HS-G mode. The area and power consumption can be minimized with the dual mode VCO. Fig. 8(c) shows the tuning curve of the VCO. Capacitor arrays are used to implement the dual mode wide tuning range which makes the overall frequency tuning range 2.6 GHz. The VCO gain (K VCO ) is MHz/V. 3. Deserializer Fig. 9(a) shows the block diagram of the deserializer. Since the MIPI-DigRF LINK layer takes parallel data from the MIPI-DigRF M-PHY in -bit unit, the 4-bit recovered data (R_DATA<3:>) from the quarter-rate CDR need to be converted to -bits by the deserializer. The D flip-flop arrays in the deserializer synchronize the R_DATA<3:> by the phase detectors in the quarterrate CDR with the recovered clock (R_CLK). The -bit deserialized data is transferred to the Rx control and Interface. Fig. 9(b) shows the timing diagram of the deserializer. The serial data from the phase detectors are stored in the

8 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.5, NO.4, AUGUST, Save Recovered Deserializing [8:9] CDB9 Reg MODE CLK_M R_DATA<> Q Q4 Q8 D Q D Q D Q Q8 DOUT<> MUX Q D Q MODE 9 [9:] CDB CDB Reg Reg sel[9:] R_DATA<> Q Q5 Q9 D Q D Q D Q Q9 Q MUX D Q DOUT<> OR Trigger R_DATA<2> Q2 Q6 Q D Q D Q D Q MODE Q DOUT<2> MUX Q4 D Q (a) R_DATA<3> R_CLK DATA Q3 Q7 Q D Q D Q D Q (a) Q Q3 MODE MUX D Q DOUT<9> d d d6 [9:] sel[5] d[9:] Comma Detecting sel[9:] sel Word Allign Block OUT R_DATA<> R_DATA<> R_DATA<2> d d d5 d6 OUT d[5:6] R_DATA<3> R_CLK (b) Q Q Q Fig.. (a) Comma detector circuit, (b) comma detection block. Q3 Q4 Q5 Q6 Q Receiver Rx FSM Comma Detector HS Deserializer Q Q µm Q Q CLK_M MODE (b) Rx Control & Interface LS Deserializer 6 µm CDR INPUT BUFFER Fig. 9. (a) Block diagram, (b) timing diagram of deserializer. 2 D flip-flops (Q Q ) as 2-bit parallel data, which is converted into final -bit parallel data at the following MUX and D flip-flops by sampling them with CLK_M. 4. Comma Detector Fig. (a) shows the block diagram of the comma detector. It is composed of two -bit registers, comma detect blocks (CDBs), a -register and -input OR gate. As mentioned above, the comma detector is used to recover -bit real data correctly according to the detected SYNC pattern. The comma detector detects word boundaries from the -bit parallel data converted by the deserializer. Aligned data from this word boundary is connected to the B/8B decoder input. Fig. (b) shows the detailed block diagram of the CDB. The -bit parallel data from the deserializer is Fig.. The chip layout. saved in two -bit registers and that saved 2-bit piece of data becomes the input to the comma detection block. The CDB searches the -bit data that includes comma signals, then determines the word boundary, and sends the information about any word boundaries to the word align block (WAB). The WAB generates the final parallel pieces of data based on the information from the CDB. IV. EXPERIMENTAL RESULTS This chip was made with in a. mm CMOS process. Fig. shows the chip layout of the analog front end of the receiver. The die area is.5 mm 2. Fig. 2 shows the simulation results when the CDR

9 54 SANG-YUN KIM et al : A.248 GB/S 2.98 GB/S LOW-POWER RECEIVER FOR MIPI-DIGRF M-PHY WITH A FAST SETTLING D.5 Sync Pattern(3SI) CDR BW Switching Bandwidth Switching SERIALIZER OUT.. BW_SW DATA Gbps DOUT<9:> Voltage (V) Voltage (V)...9 VCTRL.6.3 VCTRL..6 CDR_CLK / PLL_CLK.5.4 2n 3n 4n 5n Time (s) 5n 2n 5n n Time (s) b COMMA DETECTOR OUT Fig. 2. Simulation result of clock and data recovery for HSG2A mode. SYNC PREPARE MK B3 FF C4 FF E2 DATA 8b_RX_Symbol PREPARE SYNC DATA 5E Fig. 3. Simulation result of RX Top for HS-G2A mode. using a switched loop bandwidth for the HS-G2A modes. Before the SYNC pattern is applied, a full digital frequency detection loop detects the clock frequency to recover the data rate which is faster than ms. After frequency detection, when the SYNC pattern is applied, a phase tracking loop locks the phase using 5 MHz high bandwidth, then lowers the BW to MHz which enhances the stability of the CDR phase tracking loop. The data rate is Gb/s using a 4-phase clock of 624 MHz. When the 3 SI SYNC pattern is applied, the wide BW allows a fast locking time with BW switching, and the BW becomes narrower for high stability. Rx full operation is determined by the FSM state of the Rx controller. Before the data is applied, all blocks in the Rx are in a STALL state that is the standby status for the HS mode, and then when the prepare signal is applied from transmitter, the blocks are changed to the HS-burst state for the transmission of the control signal and data. By using serial data from the transmitter, the CDR recovers the clock and data. The recovered data is converted to parallel data by the deserializer, and then transmitted to the protocol side through the digital controller. Fig. 3 shows the simulation results of the recovering process as mentioned above. Fig. 4 shows the test board for the MIPI-DigRF MPHY receiver chip measurement. The test board was made to apply control signals from external ports to verify the performance of the digital controller and analog block. Fig. 5 shows the measured frequency settling transients of the CDR for the HS-G2A mode. When the FD loop is completed, the frequency of the VCO will be within the range of the specified frequency. The CDR HSSI Receiver RX_DP RX_DN Fig. 4. MIPI-DigRF M-PHY test board. fout [MHz] SI SYNC Frequency Detection Loop MHz 62 Lock Time = 2ns (3SI) time[ ] Fig. 5. The measured frequency settling transients of the CDR for HS-G2A mode. starts from the tuned frequency set by the FD Loop and locks to the target frequency when the SYNC pattern is applied. After the FD loop and 3 SI of SYNC pattern is applied, the frequency locks to 624 MHz. The lock time of the CDR is less than 2 ns. Fig. 6 shows the measured data eye diagram of the

10 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.5, NO.4, AUGUST, Table 3. Performance comparison with previous research Eye Opening =.96 UI Fig. 6. The measured data eye diagram of recovered data for HS-G2A mode. RX_Symbol<7> = '' RX_Symbol<6> = '' RX_Symbol<5> = '' RX_Symbol<4> = '' RX_Symbol<3> = '' RX_Symbol<2> = '' RX_Symbol<> = '' RX_Symbol<7:> = "" rate Process PD type Supply Voltage Power CDR Lock Time Jitter Chip Area [4] [5] [6] This work 2.7 Gb/s.62 Gb/s CMOS.8 mm Half-rate Linear-PD 2.7 Gb/s.62 Gb/s CMOS.3 mm /5-rate Linear-PD 2.7 Gb/s.62 Gb/s CMOS.3 mm Weighted 2.98 Gb/s.248 Gb/s CMOS. mm Quarter-rate Linear-PD.8V.2 V.2 V. V Gb/s (Rx) Gb/s (Rx) Gb/s (Rx).4 ms N.A..96 ms 37 ps p-p N.A. 54 ps p-p 29 ps rms.4- mm 2 (Rx) 23 ps p-p 3.28 ps rms.7 mm 2 (Rx) Rx 2 mw (HS-GA) 6 mw (HS-G2A).48ms (HS-GA).2 ms (HS-G2A) ps p-p 4.25 ps rms.32 mm 2 (Rx) RX_Symbol<> = '' Fig. 7. The measured output of receiver transmitted data. recovered data for the HS-G2A mode. Eye opening is 78 ps (.96 UI), the peak-to peak jitter is ps, and RMS jitter is 4.25 ps. Fig. 7 shows the loopback measurement results. The transmitted data of the receiver is while applying a pattern to Tx_symbol<7:>. In Rx, the input data is recovered by the CDR and converted to parallel data by the deserializer and transmitted as 8-bit data using the Rx_symbol<7:> to the protocol side through the decoder from the Rx digital controller. As shown in Fig. 7, it shows the output recovered data of Rx_symbol<7:> as. Table 3 shows the circuit performance summary of the proposed receiver. The data rate of this work is.248 Gb/s 2.98 Gb/s. The power consumption of the receiver is 6 mw. The performance reported for similar chips in references [4-6] does not include the power consumption of the transmitter. If the power consumption of the transmitter is included, the total power consumption of the references will be much higher than that of this research. Moreover, the Rx power consumption is much lower compared to previous research even though the data rate is much higher and the CDR lock time is much shorter. The proposed CDR is a dual-loop type with a fully digital frequency detection loop and it adopts a quarter-rate linear phase detector. The table shows that the HS-G and HS-G2 CDR locking time of this work is.48 ms and.2 ms, respectively. This performance is the fastest compared to other. In this work, to satisfy the 3 SI locking time of the CDR, a bandwidth switching method was proposed. The results show that, the CDR can be operated in such a short time, such as a 3 SI of SYNC pattern. The data rate of this work is.248 Gb/s 2.98 Gb/s. The measured peak-to-peak jitter and rms jitter in HS- GA mode are 38.6 ps p-p and 2.97 ps rms, respectively. Also, the peak-to-peak jitter in HS-G2A mode is ps p-p, and RMS jitter is 4.25 ps. V. CONCLUSIONS This paper presents a.248 Gb/s 2.95 Gb/s low-power receiver for MIPI-DigRF M-PHY with a fully digital frequency detection loop. In the receiver, the quarter rate CDR with a fully digital frequency detection loop is proposed to implement the fast phase tracking loop. This chip is fabricated using a. μm CMOS process, and the die area is 6 μm x 25 μm. The power consumption of the receiver is 6 mw from.v supply for the HS-G2A mode. The measured rms and peak jitter are ps p-p and 4.25 ps rms respectively for the HS-G2 mode

11 56 SANG-YUN KIM et al : A.248 GB/S 2.98 GB/S LOW-POWER RECEIVER FOR MIPI-DIGRF M-PHY WITH A FAST SETTLING ACKNOWLEDGMENTS This work was supported by the ICT R&D program of MSIP/IITP. [4545, Development of tracking the location of continuous moving objects in wide-area]. REFERENCES [] K. Hu et al., A.6 mw/gb/s, Gb/s Serial Link Receiver Using Local Injection-locked Ring Oscillators in 9 nm CMOS, IEEE J. Solid-State Circuits, vol. 45, no. 4, pp , Apr. 2. [2] J.-K. Kim, J. Kim, G. Kim, and D.-K. Jeong, A Fully Integrated.3-mm CMOS 4-Gb/s Serial Link Transceiver, IEEE J. Solid-State Circuits, vol. 44, no. 5, pp. 5 52, May. 29. [3] K.-L. J. Wong, H. Hatamkhani, M. Mansuri, and C.-K. K. Yang, A 27-mW 3.6-Gb/s I/O Transceiver, IEEE J. Solid-State Circuits, vol. 39, no. 4, pp , Apr. 24. [4] S. Lee et al., A 2.7 Gbps &.62 Gbps Dual-mode Clock and Recovery for DisplayPort in.8 CMOS, in Proc. IEEE Int. SOC Conf., 29, pp [5] K. Min, and C. Yoo, A.62/2.7Gbps Clock and Recovery with Pattern Based Frequency Detector for DisplayPort, IEEE Transaction on Consumer Electronics, vol. 56, no. 4, pp , Nov. 2. [6] J. Song, I. Jung, M. Song, Y.-H. Kwak, S. Hwang, and C. Kim, A.62 Gb/s 2.7 Gb/s Referenceless Transceiverfor DisplayPort v.a With Weighted Phase and Frequency Detection, IEEE Transactions on Circuits and Systems, vol. 6, no. 2, pp , Feb. 23. [7] M. Hossain et al., A 7.4 Gb/s 6.8 mw source synchronous receiver in 65 nm CMOS, IEEE J. Solid-State Circuits, vol. 45, no. 4, pp , Apr. 2. [8] M. Hwang et al., A 8-Mb/s to 3.2 Gb/s, Continuous-rate, Fast-locking CDR without Using External Reference Clock, in Proc. IEEE Asian Solid-State Circuits Conf., 27, pp [9] J.-K. Woo, H. Lee, W.-Y Shin, H. Song, D.-K Jeong, and S. Kim, A Fast-Locking CDR Circuit with an Autonomously Reconfigurable Charge Pump and Loop Filter, IEEE ASSCC 26, pp. 4 44, Nov. 26. [] W.-H Zhao, Z.-G. Wang, and E. Zhu, A Gb/s CMOS Word Alignment Demultiplexer for Serial Communications, in Proc. IEEE European Solid-State Circuits Conf., 23, pp [] Y. Zhen, and H. Qing-sheng, A Comma Detection and Word Alignment Circuit for High-speed SerDes, IEEE WiCOM 2, pp. -4. [2] R. Inti et al., A.5-to-2.5 Gb/s Reference-less Half-rate Digital CDR with Unlimited Frequency Acquisition Range and Improved Input Dutycycle Error Tolerance, IEEE J. Solid-State Circuits, vol. 46, no. 2, pp , Dec. 2. [3] L. Hai Qi et al., A Low-noise Multi-GHz CMOS Multiloop Ring Oscillator with Coarse and Fine Frequency Tuning, IEEE Trans. Very Large Scale Integr. Syst., vol. 7, pp , 29. [4] S. Zhinian et al., A 2.4-GHz Ring-oscillator-based CMOS Frequency Synthesizer with a Fractional Divider Dual-PLL Architecture, IEEE J. Solid- State Circuits, vol. 39, pp , 24. Sang-Yun Kim received his B.S. degree from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 23. He is currently working towards a combined Ph.D. & M.S. at the School of Information and Communication Engineering at, Sungkyunkwan University. His research interests include high-speed interface ICs and CMOS RF transceivers. Juri Lee received her B.S. degree from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 23, where she is currently working toward a combined Ph.D. & M.S degree at the School of Information and Communication Engineering, Sungkyunkwan University. Her research interests include VCSEL drivers and CMOS RF transceivers.

12 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.5, NO.4, AUGUST, Hyung-Gu Park was born in Seoul, Korea. He received his B.S. degree from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 2, where he is currently working toward a Ph.D. degree through the School of Information and Communication Engineering, Sungkyunkwan University. His research interests include highspeed interface IC and CMOS RF transceiver. Young Gun Pu received his B.S., M.S. and Ph.D. degrees from the Department of Electronic Engineering at Konkuk University, Seoul, Korea, in 26, 28 and 22, respectively. His research interest is focused on CMOS fully integrated frequency synthesizers and oscillators and on transceivers for lowpower mobile communication. Kang-Yoon Lee received his B.S., M.S. and Ph.D. degrees from the School of Electrical Engineering at Seoul National University, Seoul, Korea, in 996, 998, and 23, respectively. From 23 to 25, he was with GCT Semiconductor Inc., San Jose, CA, where he was a Manager of the Analog Division and worked on the design of the CMOS frequency synthesizer for CDMA/PCS/PDC and singlechip CMOS RF chip sets for W-CDMA, WLAN, and PHS. From 25 to 2, he was an Associate Professor at the Department of Electronics Engineering, Konkuk University. Since 22, he has been an Associate Professor at the College of Information and Communication Engineering, Sungkyunkwan University. His research interests include the implementation of power integrated circuits, CMOS RF transceivers, analog integrated circuits, and analog/digital mixed-mode VLSI system design. Jae Yong Lee was born in Seoul, Korea. He received the Bachelor of Industrial Engineering from the Hankuk University of Foreign Studies, Seoul, Korea, in 998. He carried out Telematics and LBS service business at SK networks, RealTelecom and Hubilon for more than a decade. He is currently CEO at Hubilon CO.,LTD which is a leading company in the field of indoor positioning service in Korea. His research interests cover the design and analysis of RTLS and indoor location services with over patents.