Wide-Bandwidth OPERATIONAL AMPLIFIER

Transcription

1 Wide-Bandwidth OPERATIONAL AMPLIFIER FEATURES LARGE SIGNAL BANDWIDTH: 1MHz (AP), MHz (AU) (Voltage-Feedback) HIGH OUTPUT CURRENT: ±7mA SLEW RATE: 1V/µs (AP), 17V/µs (AU) DIFFERENTIAL GAIN:.1% DIFFERENTIAL PHASE:. EXCELLENT BANDWIDTH/SUPPLY CURRENT RATIO: MHz/mA LOW INPUT BIAS CURRENT: 1.µA DESCRIPTION The is a monolithic amplifier component designed for precision wide-bandwidth systems including high-resolution video, RF and IF circuitry, and communications equipment. It includes a monolithic integrated current-feedback operational amplifier block and a voltage buffer block, which, when combined, form a voltage-feedback operational amplifier. When combined as a current-feedback amplifier, it provides a MHz large-signal bandwidth at ±.V output level and a 17V/µs slew rate. The output buffer stage can deliver ±7mA output current. The high output current capability allows the to drive two Ω or 7Ω lines with ±V output swing, making it ideal along with the low differential gain/phase errors for RF, IF, and video applications. APPLICATIONS BROADCAST/HDTV EQUIPMENT COMMUNICATIONS PULSE/RF AMPLIFIERS ACTIVE FILTER HIGH SPEED ANALOG SIGNAL PROCESSING MULTIPLIER OUTPUT AMP DIFFERENTIATOR FOR DIGITIZED VIDEO SIGNALS The feedback buffer stage provides 7MHz bandwidth, a very high slew rate, and a very short signal delay time. It is designed primarily for interstage buffering and not for driving long cables. When combined with the current-feedback amplifier section, the can be interconnected as a voltage-feedback amplifier with two identical high-impedance inputs. In this configuration, it features a low common-mode gain, low input offset, and, due to the delay time of the additional feedback buffer, a decrease in frequency bandwidth compared with the current-feedback configuration. Unlike classical operational amplifiers, the achieves a nearly constant bandwidth over a wide gain and output voltage range. The external setting of the open-loop gain with R OG avoids a large compensation capacitor, improves the slew rate, and allows a frequency response adaption to various gains and load conditions. VOLTAGE-FEEDBACK CURRENT-FEEDBACK V IN Ω R IN In +In C OTA 1 VFA BUF 1 BUF+ Ω V IN Ω R IN 1 BUF+ +In CFA C OTA 1 1Ω Ω R OG I Q Adjust R Q V I Q Adjust R Q V International Airport Industrial Park Mailing Address: PO Box 11 Tucson, AZ 7 Street Address: 7 S. Tucson Blvd. Tucson, AZ 7 Tel: () Twx: Cable: BBRCORP Telex: -1 FAX: () -11 Immediate Product Info: () Burr-Brown Corporation PDS-111E Printed in U.S.A. March, 1

2 SPECIFICATIONS DC-SPECIFICATION VOLTAGE-FEEDBACK AMPLIFIER (Figure ) At V CC = ±V, I Q = ±ma, G CL = +V/V, R LOAD = 1Ω, R SOURCE = Ω, R Q = Ω, R OG = 1Ω and T A = + C, unless otherwise specified. AP, AU PARAMETER CONDITIONS MIN TYP MAX UNITS CLOSED-LOOP OUTPUT OFFSET VOLTAGE Initial 1 ±1 mv vs Temperature 1 µv/ C vs Supply (tracking) V CC = ±.V to ±.V db vs Supply (non-tracking) V CC = +.V to +.V db vs Supply (non-tracking) V CC =.V to.v 1 db INPUT BIAS CURRENT Initial 1. ± µa vs Temperature 7 na/ C vs Supply (tracking) V CC = ±.V to ±.V na/v vs Supply (non-tracking) V CC = +.V to +.V 17 na/v vs Supply (non-tracking) V CC =.V to.v na/v OFFSET CURRENT Input Offset Current V CM = V.1 µa INPUT IMPEDANCE Differential Mode. 1 MΩ pf INPUT NOISE Voltage Noise Density f = 1kHz to 1MHz 11 nv/ MHz Signal-to-Noise Ratio S/N = log.7/(v N MHz) db INPUT VOLTAGE RANGE Common-Mode Input Range ±. V Common-Mode Rejection V I = +.V, V O = V 7 db RATED OUTPUT G CL = +1 Voltage Output ± ±. V Closed-Loop Output Impedance. Ω Current Output 7 ma POWER SUPPLY Rated Voltage ± V Derated Performance ±. ±. V Quiescent Current R Q = Ω, I O = ma ±. ± ±. ma Quiescent Current (programmable) Useful Range, I O = ma to ma TEMPERATURE Operating Ambient Temperature C Storage Ambient Temperature 1 C ABSOLUTE MAXIMUM RATINGS Power Supply Voltage... ±V Input Voltage (1)... ±V CC to ±.7V Operating Temperature... C to + C Storage Temperature... C to +1 C Junction Temperature C Lead Temperature (soldering, 1s)... + C NOTE: (1) Inputs are internally diode-clamped to ±V CC. PACKAGE INFORMATION PACKAGE DRAWING MODEL DESCRIPTION NUMBER (1) AP 1-Pin Plastic DIP 1 AU SO-1 Surface-Mount ORDERING INFORMATION MODEL DESCRIPTION TEMPERATURE RANGE AP 1-Pin Plastic DIP C to + C AU SO-1 Surface-Mount C to + C USA OEM PRICES MODEL AP $1. $. $7. AU NOTE:(1) For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

3 AC-SPECIFICATION VOLTAGE-FEEDBACK AMPLIFIER (Figure ) At V CC = ±V, I Q = ±ma, G CL = +V/V, R LOAD = 1Ω, R SOURCE = Ω, R Q = Ω, R OG = 1Ω and T A = + C, unless otherwise specified. AP AU PARAMETER CONDITIONS TYP TYP UNITS FREQUENCY DOMAIN LARGE SIGNAL V O =.Vp-p, Gain = +1V/V MHz Closed-Loop Bandwidth ( db) V O =.Vp-p, Gain = +V/V MHz V O =.Vp-p, Gain = +V/V 17 MHz V O =.Vp-p, Gain = +1V/V MHz V O =.Vp-p, Gain = 1V/V 1 MHz V O =.Vp-p, Gain = V/V 1 MHz V O =.Vp-p, Gain = +V/V 1 MHz SMALL SIGNAL BANDWIDTH V O =.Vp-p, Gain = +V/V 1 17 MHz GROUP DELAY TIME ns DIFFERENTIAL GAIN f =.MHz, R LOAD = 1Ω V O =.7V, Gain = +1V/V.1.1 % V O = +1.V, Gain = +V/V.1.1 % DIFFERENTIAL PHASE f =.MHz, R LOAD = 1Ω V O =.7V, Gain = +1V/V.. Degrees V O = +1.V, Gain = +V/V.. Degrees HARMONIC DISTORTION Gain = +V/V Second Harmonic f f = 1MHz, V O =.Vp-p 7 7 dbc Third Harmonic f dbc Second Harmonic f f = MHz, V O =.Vp-p dbc Third Harmonic f dbc Second Harmonic f f = MHz, V O =.Vp-p dbc Third Harmonic f dbc GAIN FLATNESS PEAKING Gain = +V/V V O =.Vp-p, DC to MHz.1.1 db V O =.Vp-p, DC to 1MHz.. db TIME DOMAIN Rise Time Gain = +V/V, 1% to %..7 ns V O = Vp-p, C L = pf Fall Time Gain = +V/V, 1% to %.. ns V O = Vp-p, C L = pf SLEW RATE Gain = +V/V, Rise Time = ns V O =.Vp-p Positive 1 17 V/µs Negative 1 1 Vµs SETTLING TIME Gain = +V/V, Rise Time = ns V O = Vp-p,.1% ns

4 DICE INFORMATION PAD FUNCTION 1 Quiescent Current Adjustment Inverting Analog Input Non-Inverting Analog Input NC NC V Supply 7 V Supply, Output Inverting Buffer Output Analog Output 1 Analog OTA Output 11 +V Supply, Output 1 +V Supply 1 Non-Inverting Buffer Output Substrate Bias: Negative Supply NC: No Connection Wire Bonding: Gold wire bonding is recommended. MECHANICAL INFORMATION AD DIE TOPOGRAPHY MILS (.1") MILLIMETERS Die Size 7 x ± 1. x 1.7 ±.1 Die Thickness 1 ±1. ±. Min. Pad Size x.1 x.1 Backing: Titanium.+.,..+.1,. Gold. ±..7 ±.1 PIN CONFIGURATION FUNCTIONAL DESCRIPTION Top View NC I Q Adjust In +In V CC OTA 11 OB FB SO/DIP 1 NC 1 BUF+ 1 +V CC 11 +V CC OUT 1 OTA PIN NO. DESCRIPTION FUNCTION 1 NC No Connection I Q Adjust Quiescent Current Adjustment; typical -ma In Inverting Analog Input +In Noninverting Analog Input V CC Negative Supply Voltage; typical VDC V CC OUT Negative Supply Voltage Output Buffer; typical VDC BUF Analog Output Feedback Buffer Analog Output 1 OTA Analog Output OTA 11 +V CC OUT Positive Supply Voltage Output Buffer; typical +VDC 1 +V CC Positive Supply Voltage; typical +VDC 1 BUF+ Analog Output/Input 1 NC No Connection V CC OUT Biasing 1 NC 7 BUF ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr- Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications.

5 TYPICAL PERFORMANCE CURVES VOLTAGE-FEEDBACK AMPLIFIER (Figure ) At V CC = ±V, I Q = ±ma, G CL = +V/V, R LOAD = 1Ω, R SOURCE = Ω, R Q = Ω, R OG = 1Ω and T A = + C, unless otherwise specified. INPUT BIAS CURRENT vs TEMPERATURE 1 CLOSED-LOOP OUTPUT OFFSET VOLTAGE vs TEMPERATURE Input Bias Current (µa) Input Bias Offset Current Positive Input Bias Current Negative Input Bias Current Offset Voltage (mv) 1 1 G CL = +V/V 1. 1 Temperature ( C) 1 1 Temperature ( C) V OS (% final value) INPUT OFFSET VOLTAGE vs TIME 1 DIP 7 SO Time (minutes) Offset Voltage Drift (mv) INPUT STAGE OFFSET VOLTAGE vs TEMPERATURE. Input Offset Voltage. 1 Negative Input Voltage Positive Input Voltage 1. 1 Temperature ( C) Quiescent Current (ma) QUIESCENT CURRENT vs R Q RESISTANCE R Q (Ω) Quiescent Current (ma) QUIESCENT CURRENT vs TEMPERATURE Temperature ( C)

6 TYPICAL PERFORMANCE CURVES (CONT) VOLTAGE-FEEDBACK AMPLIFIER (Figure ) At V CC = ±V, I Q = ±ma, G CL = +V/V, R LOAD = 1Ω, R SOURCE = Ω, R Q = Ω, R OG = 1Ω and T A = + C, unless otherwise specified. COMMON-MODE REJECTION vs COMMON-MODE INPUT VOLTAGE 1 SPECTRAL NOISE VOLTAGE DENSITY Common-Mode Rejection (db) 7 7 Voltage Noise nv/ Hz Common-Mode Input Voltage (V) 1 1 1k 1k 1k 1M 1M 1M INPUT IMPEDANCE vs FREQUENCY 1 OUTPUT IMPEDANCE vs FREQUENCY Input Impedance (Ω) 1M 1k 1k 1k Output Impedance (Ω) 1 1 G CL = k 1k 1k 1M 1M 1M 1G 1m 1k 1k 1M 1M 1M 1G Common-Mode Rejection (db) COMMON-MODE REJECTION vs FREQUENCY 1 7 1k 1k 1M 1M 1M 1G Input Voltage (V) OVERLOAD RECOVERY CHARACTERISTICS. V IN G CL = +V/V, V IN =.7Vp-p, t RISE = t FALL = 1ns (Generator) Time (ns) Output Voltage (V)

7 TYPICAL PERFORMANCE CURVES (CONT) VOLTAGE-FEEDBACK AMPLIFIER (Figure ) At V CC = ±V, I Q = ±ma, G CL = +V/V, R LOAD = 1Ω, R SOURCE = Ω, R Q = Ω, R OG = 1Ω and T A = + C, unless otherwise specified. 1 SMALL SIGNAL PULSE RESPONSE 1 SMALL SIGNAL PULSE RESPONSE 1 1 Output Voltage (mv) Output Voltage (mv) 1 1 G CL = +1V/V, =.Vp-p, t RISE = t FALL = 1ns (Generator) 1 1 G CL = +1V/V, =.Vp-p, t RISE = t FALL = 1ns (Generator) Time (ns) Time (ns) LARGE SIGNAL PULSE RESPONSE LARGE SIGNAL PULSE RESPONSE.. Input/Output Voltage (V) V IN Output Voltage (V). G = +1V/V, V OUT = Vp-p, t RISE = t FALL = 1ns (Generator) Time (ns). G CL = +1V/V, = Vp-p, t RISE = t FALL = 1ns (Generator) Time (ns) 1 BANDWIDTH vs OUTPUT VOLTAGE Vp-p 1 BANDWIDTH vs OUTPUT VOLTAGE Vp-p 1.Vp-p 1.Vp-p Output Voltage (Vp-p) Vp-p.Vp-p.Vp-p Output Voltage (Vp-p) Vp-p.Vp-p.Vp-p G CL = +1V/V G CL = +V/V db k 1M 1M 1M 1G G db k 1M 1M 1M 1G 7

8 TYPICAL PERFORMANCE CURVES (CONT) VOLTAGE-FEEDBACK AMPLIFIER (Figure ) At V CC = ±V, I Q = ±ma, G CL = +V/V, R LOAD = 1Ω, R SOURCE = Ω, R Q = Ω, R OG = 1Ω and T A = + C, unless otherwise specified. 1 1 BANDWIDTH vs OUTPUT VOLTAGE Vp-p.Vp-p 1 1 BANDWIDTH vs OUTPUT VOLTAGE Vp-p.Vp-p Output Voltage (Vp-p) 1 1 db k 1.Vp-p.Vp-p.Vp-p G CL = +1V/V 1M 1M 1M 1G Output Voltage (Vp-p) 1 1 db k 1.Vp-p.Vp-p.Vp-p G CL = 1V/V 1M 1M 1M 1G 1 1 BANDWIDTH vs OUTPUT VOLTAGE Vp-p.Vp-p GAIN FLATNESS Output Voltage (Vp-p) 1 1 db 1k 1.Vp-p.Vp-p.Vp-p G CL = V/V 1M 1M 1M 1G Gain (db) 1 1 k G CL = +V/V, =.Vp-p 1M 1M 1M 1G Gain (db/div) FREQUENCY RESPONSE vs C LOAD 7pF pf 1pF C LOAD R OG C OTA 1p 1Ω.p p Ω.p G CL = +V/V, =.Vp-p 7p 1Ω.p 1k 1M 1M 1M 1G Gain (db) db BANDWIDTH vs R LOAD Ω Ω 1Ω Ω G = +V, =.Vp-p for all load resistances 1k 1M 1M 1M 1G

9 TYPICAL PERFORMANCE CURVES (CONT) VOLTAGE-FEEDBACK AMPLIFIER (Figure ) At V CC = ±V, I Q = ±ma, G CL = +V/V, R LOAD = 1Ω, R SOURCE = Ω, R Q = Ω, R OG = 1Ω and T A = + C, unless otherwise specified. HARMONIC DISTORTION vs FREQUENCY G CL = +V/V, =.Vp-p, R LOAD = 1Ω 1 GROUP DELAY TIME vs FREQUENCY Harmonic Distortion (dbc) f f Group Delay Time (ns) V IN Group Delay Time 1Ω Ω DUT 7 G CL = +V/V 1k 1M 1M 1M k 1M 1M 1M 1G TRANSFER FUNCTION OUTPUT BIAS CURRENT vs TEMP Output Voltage (V) 1 1 Output Bias Current (µa) 1 1 Input Voltage (V) 1 1 Temperaure ( C) GAIN ERROR vs INPUT VOLTAGE Gain Error (%) Input Voltage (V)

10 INPUT PROTECTION The need for protection from static damage has long been recognized for MOSFET devices, but all semiconductor devices deserve protection from this potentially damaging source. The incorporates on-chip ESD protection diodes as shown in Figure 1. These diodes eliminate the need for external protection diodes, which can add capacitance and degrade AC performance. External Pin +V CC V CC FIGURE 1. Internal ESD Protection. ESD Protection diodes internally connected to all pins. Internal Circuitry As shown, all input pins of the are protected from ESD internally by a pair of back-to-back reverse-biased diodes to either power supply. These diodes begin to conduct when the input voltage exceeds either power supply by about.7v. This situation can occur when the amplifier loses its power supplies while a signal source is still present. The diodes can typically withstand a continuous current of ma without destruction. To ensure long-term reliability, however, the diode current should be limited externally to approximately 1mA whenever possible. The internal protection diodes are designed to withstand.kv (using the Human Body Model) and will provide adequate ESD protection for most normal handling procedures. However, static damage can cause subtle changes in the amplifier input characteristics without necessarily destroying the device. In precision amplifiers, such changes may degrade offset and drift noticeably. For this reason, static protection is strongly recommended when handling the. DISCUSSION OF PERFORMANCE The provides full-power bandwidth previously unattainable in monolithic devices. In addition, the amplifier operates with reduced quiescent. The flexibility of the design provides the speed advantages of a currentfeedback amplifier or the precision advantages of a voltagefeedback amplifier. The programmable quiescent current feature also helps to adapt the amplifier to the particular design requirements. Figure shows the simplified circuit diagram of the. It contains four major sections: the bias circuitry, the OTA, the output buffer, and the feedback buffer. BIAS CIRCUITRY The bias circuitry controls the quiescent current of the signal processing stages, allows external quiescent current setting using the resistor R Q connected from Pin to V CC, sets the amplifier s transconductance, and, with its temperature characteristics, maintains a constant transconductance over temperature. The quiescent current controls the small-signal bandwidth and AC behavior. The is specified with a quiescent current of ±ma with R Q = Ω. The recommended range is ±ma to ±ma. +V CC V CC OUT OTA FB OB Bias Circuitry R +In OG 1 In OTA 1 + BUF 1 1Ω I Q Adjust R Q (ext.) V CC V CC OUT FIGURE. Simplified Circuit Diagram. 1

11 Application circuits generally do not show the resistor R Q, but it is required for proper operation. With a fixed R Q, the quiescent current increases with temperature (see Typical Performance Curves.) This variation of the quiescent current with temperature keeps the bandwidth and AC behavior relatively constant with temperature. It is also possible to vary the quiescent current by an external control signal or circuitry. Figure shows a circuit to disable the with TTL-compatible logic levels. V/V logic levels are converted into a 1mA/mA current connected to Pin. The current flowing in R Q increases the voltage at Pin to approximately 1V above the V CC rail, thus reducing I Q to near zero and disabling the. /V Logic In V: On I C +V.7kΩ N7 Internal Current Source Circuitry 1Ω 1kΩ OTA AND OUTPUT BUFFER SECTIONS An Operational Transconductance Amplifier (OTA) and an output buffer are the basic building blocks of a currentfeedback amplifier. The current-feedback configuration of the is illustrated in Figure. The OTA consists of a complementary emitter follower and a subsequent complementary current mirror. The voltage at the high-impedance +In terminal is transferred to the BUF+ input/output terminal at a low impedance. If a current flows into or out of the BUF+ terminal, the complementary mirror reflects the current to the OTA terminal. The current flow at the highimpedance OTA terminal is determined by the product of the voltage between the +In and BUF+ terminals and the transconductance. The output buffer section is an open-loop buffer consisting of complementary emitter followers. It is designed to drive cables or low-impedance loads. The buffer output is not current-limited or -protected. As can be seen in Figure, the feedback network for a current-feedback amplifier is applied between the and BUF+ terminals. Figure illustrates the bandwidth for various output voltages of the current feedback configuration. I C = : On I C = 1mA: Off R Q Ω V FIGURE. Logic-Controlled Disable Circuit. FEEDBACK BUFFER SECTION This section of the is a complementary emitter follower identical to the input buffer of the OTA section. It is designed for interstage buffering, not for driving long cables or low-impedance loads. A minimum load resistance of Ω is recommended when using the feedback buffer as a stand-alone device. The feedback buffer output is not current-limited or -protected. The bandwidth of the feedback buffer is shown in Figure 7. +V CC 1 OTA + V CC OUT 11 C OTA 1 OB +In 1 BUF+ V CC OUT V CC FIGURE. Current-Feedback Amplifier. 11

12 CONFIGURATIONS VOLTAGE-FEEDBACK AMPLIFIER The s internal design differs from a classical operational amplifier structure, but it can nevertheless be used in all traditional operational amplifier applications. As with conventional op amps, the feedback network connected to the inverting input controls closed-loop gain (G CL ). But with the, the resistor R OG is simultaneously adapted to the closed-loop gain, optimizing the frequency response and stability. The classical differential input stage consists of two identical transistors with an emitter degeneration resistor, two current sources, and an active load diode. However, the classical configuration limits the current through the gain transistor to that supplied by the current sources. In the new design, a complementary push-pull buffer (emitter follower) replaces one side of the differential stage without the.7v offset. The feedback buffer as a second complementary emitter follower and the open-loop gain resistor R OG connected between the outputs recreate the differential stage without the disadvantages of the classical design. The current charging the parasitic capacitance at the base of the gain transistor is no longer limited to the fixed current of the current sources and is proportional to the input signal. This improvement results in an approximately 1-times better slew rate. The amplified current through the gain transistor of one of the buffers is mirrored and becomes the output current. The high-impedance output of the OTA is now buffered by the high current output stage, which is designed to drive long cables or low-impedance loads at full power. The identical input buffers reduce the input offset to typically less than ±7µV. Closed-loop output offset is typically due to mismatch of the NPN and PNP transistors in the OTA mirror ±1µV after the output bias current is trimmed. Figure illustrates the circuit configuration of the voltagefeedback op amp in a complementary circuit design. The feedback buffer and the OTA input buffer form the differential input. Inserting the feedback buffer section transforms the current feedback shown in Figure into the voltage feedback shown in Figure. The resistor R OG sets the open-loop gain and corresponds to the emitter degeneration resistor in a classical differential stage. Because the R OG resistor can be varied externally, a flat frequency response can be achieved over a wide range of applications without the need to compensate the amplifier with a capacitor. In contrast to a current-feedback amplifier, it is possible to adjust the closed-loop gain using the feedback resistors and to adjust the open-loop gain independently using R OG to optimize the frequency response. Unlike classical operational amplifier structures, the configuration makes it possible to attain a nearly constant bandwidth for varying closed-loop gains, as well as improved frequency response and large-signal behavior. In addition and also unlike current-feedback op amps it provides two identical high-impedance inputs, lower input offset values, and improved CMRR. CURRENT-FEEDBACK AMPLIFIER Figure shows the current-feedback configuration. The feedback loop is closed from the output to the BUF+ terminal of the OTA section. The shorter feedback loop + V CC 1 + V CC OUT +In OTA 1 R OG FB In 1 C OTA 11 OB G CL = 1 + V CC OUT V CC C OTA : Sets the first open-loop pole R OG : Sets the open-loop gain FIGURE. Voltage-Feedback Amplifier. 1

13 without the feedback buffer produces the wider bandwidth of the current-feedback concept. The additional signal delay time through the feedback buffer determines the difference in AC performance between voltage and current feedback. The specifications for offset voltage, CMMR, and settling times are the compromise for higher speed. The open-loop gain for the current-feedback amplifier varies directly with the closed-loop gain and can be adjusted by changing the size of. For gains of less than 1V/V, the open-loop gain can be adjusted to achieve bandwidth independent of gain, but the effects of this adjustment become limited when second-order effects start to dominate. Figure gives an overview of the inverting and non-inverting amplifier configurations and shows the equations for the closed-loop gains. OPTIMAL FREQUENCY RESPONSE ADJUSTMENT Conventional voltage-feedback op amps use a compensation capacitor for stable unity-gain operation. During transitions, the quiescent current charges and discharges this capacitor, and both parameters determine the slew rate according to: I SR = = t C This method is not appropriate for wide-band op amps. The slew rate and thus the large-signal behavior are significantly reduced, and the bandwidth decreases with increasing closedloop gains according to the gain-bandwidth product. Amplifiers with an external compensation capacitor allow optimal frequency adjustment versus closed-loop gain, but nevertheless do not significantly improve large-signal behavior. The most effective solution is to make the open-loop gain (G OL ) externally adjustable. The widely-used current-feedback op amp type designed with real complementary circuit techniques overcomes the internal compensation capacitor and allows the feedback network to set the open-loop gain. The ratio of the feedback resistors determines the low-frequency closed-loop gain, and the parallel impedance defines the amplifier s open-loop gain for stable operation and flat frequency response. A nearly constant bandwidth can be achieved over a wide range of closed-loop gains. However, current-feedback op amps suffer from nonidentical inputs and poor input offset and CMRR. The voltage-feedback op amp with its complementary topology features two identical high-impedance inputs, lower input offset values, and improved CMRR. The ratio of the feedback resistors determines the lowfrequency closed-loop gain, and the external resistor R OG sets the open-loop gain to achieve a flat frequency response over a wide range of closed-loop gains. Since R OG can be selected, optimized pulse responses are possible even with larger load capacitances. The combines the slew rate enhancements of a complementary amplifier design with the precision of a voltage-feedback system. The hybrid model shown in Figure describes the AC behavior of a noncompensated wide-band differential op amp. The open-loop frequency response, which is illustrated in Figure 1 for various R OG values, is determined by two OTA +V IN Non-inverting OB Voltage-Feedback OTA Inverting OB R OG R OG FB FB G CL = 1 + R1 G CL = V IN Current-Feedback Non-inverting Inverting OTA V OTA OUT OB OB +V IN FB FB V IN G CL = 1 + R1 G CL = FIGURE. Op Amp Configurations for. 1

14 time constants. The elements R and C OTA between the current source output and the output buffer form the first open-loop pole T C. The signal delay time, T D, modelled in the output buffer, combines several small phase-shifting time constants and delay times. They are distributed throughout the amplifier and are also present in the feedback loop. As shown in Figure 1, an increasing R OG leads to a decreasing open-loop gain. The ratio of the two time constants, T C and T D, of the open-loop frequency response also determines the product G OL G CL for optimal closed-loop frequency response. G OL = G + CL T C and T D are fixed by the op amp design. The purpose of R OG now is to vary G OL versus G CL to keep the product G OL G CL constant, which is the theoretical condition for optimal and gain-independent frequency response. Figure 11 summarizes some optimal flat closed-loop responses and indicates the R OG values. It should be noted that the bandwidth remains relatively constant and R OG has its highest value (low open-loop T C T D gain) at low closed-loop gains. Harmonic distortion is also improved with increased open-loop gain. Figure 1 shows the frequency response at G CL = +V/V and variable R OG to demonstrate its influence on a flat frequency response. Slight variation of R OG might be necessary to compensate for load capacitance. It is possible to achieve optimal pulse response over a wide range of load capacitances without overshooting and ringing. As an example, Figure 1 shows a selection curve for the optimal R OG value versus the load capacitance at a gain (G CLO ) of +V/V. THERMAL CONSIDERATIONS The does not require a heat sink for operation in most environments. A heat sink will, however, reduce the internal thermal rise, resulting in cooler, more reliable operation. At extreme temperatures and under full load conditions, a heat sink is necessary. The internal power dissipation is given by the equation P D = P DQ + P DL, (P DQ is the quiescent power dissipation and P DL is the power dissipation in the output stage due to the load). Although the P DQ is very low (mw at V CC = ±V), care should be taken Output Voltage (Vp-p) Vp-p 1.Vp-p.Vp-p.Vp-p 1Ω +1 1k +In R T C T T V D OUT 1 1 g m g m R In OG 1 db 1M 1M 1M 1G G Frequency (HZ) FIGURE. Hybrid Model of a Wideband Op Amp. FIGURE 7. Bandwidth vs Output Voltage (Feedback Buffer ). R OG = Ω 7Ω 1Ω Ω Output Voltage (Vp-p) db.vp-p.vp-p 1.Vp-p.Vp-p.Vp-p.pF 1Ω Ω 1Ω 1Ω G CL = +V/V 1M 1M 1M 1G G Gain (db) 1 1 1k 1k 1M 1M 1M 1G FIGURE 1. Open-Loop Gain vs R OG. Frequency (HZ) FIGURE. Bandwidth vs Output Voltage (Current-Feedback Amplifier). 1

15 when a signal is applied. For high-speed op amps, a more precise approach to determine power consumption is to measure the average total quiescent current for several typical load conditions. The power consumption of the is influenced by the signal type and frequency, the output voltage and load resistor, and the repetition rate of the signal transitions. Figure 1 shows the total average supply current versus the frequency of an applied sine wave for various output voltages. Figure 1 illustrates the total quiescent current versus the repetition frequency of an applied square wave signal. CIRCUIT LAYOUT The high-frequency performance of the can be greatly affected by the physical layout of the printed circuit board. The following tips are offered as suggestions, not as absolute musts. Oscillations, ringing, poor bandwidth and settling, and peaking are all typical problems that plague high-speed components when they are used incorrectly. Bypass power supplies very close to the device pins. Use tantalum chip capacitors (approximately.µf) and a parallel 7pF ceramic chip capacitor. Surface-mount types are recommended because of their low lead inductance. PC board traces for power lines should be wide to reduce impedance. Make short, low-inductance traces. The entire physical circuit should be as small as possible. Use a low-impedance ground plane on the component side to ensure that low-impedance ground is available throughout the layout. Place the R OG resistor as close as possible to the package and use the shortest possible trace length. Do not extend the ground plane over high-impedance nodes sensitive to stray capacitances such as the amplifier s input and R OG terminals. Sockets are not recommended, because they add significant inductance and parasitic capacitance. If sockets are required, use zero-profile solderless sockets. Use low-inductance, surface-mount components for best AC performance. A resistor (Ω to Ω) in series with the high-impedance inputs is strictly recommended for stable operation. Plug-in prototype boards and wire-wrap boards will not function well. A clean layout using RF techniques is essential. Gain (db/div) k G CL = +1 G CL = + G CL = +1 G CL = 1 G CL = R OG = 1Ω R OG = 1Ω R OG = Ω R OG = Ω R OG = 1Ω AP V O = 1.Vp-p, Refer to Table I for recommended component values. 1M 1M 1M 1G Gain (db/div) 7pF pf 1pF C LOAD R OG C OTA 1p 1Ω.p G CL = +V/V, V O =.Vp-p p Ω.p 7p 1Ω.p 1M 1M 1M 1G FIGURE 11. Optimum Response vs Closed-Loop Gains. FIGURE 1. Bandwidth vs C LOAD. Amplitude (db) 1 R OG = Ω R OG = 1Ω 1 R OG = Ω 1 G CL = +V/V 1k 1M 1M 1M 1G FIGURE 1. Closed-Loop Gain vs R OG. Average Supply Current (ma) Vp-p.Vp-p 1 1.Vp-p.Vp-p G = +V/V, R LOAD = 1Ω k 1M 1M 1M 1G FIGURE 1. Average Supply Current vs Frequency (Sine Wave). 1

16 Average Supply Current (ma) 1 x 1 x Vp-p.Vp-p x 1.Vp-p.Vp-p x x x x x x G CL = +V/V, R LOAD = 1Ω 1k 1k 1k 1M 1M 1M 1G FIGURE 1. Average Supply Current vs Frequency (Square Wave). V CC +V CC 1 1pF +V CC OUT C OTA 1 11 R QC R Ω NC (1) V CC Biasing R L Ω Out Z O = Ω OB Z O = Ω InPOS R LR 1Ω OTA R IN Ω R SOURCE = Ω R L 1Ω R L1 1Ω R ING NC (1) FB Ω R Ω R OG 1Ω 1 V CC OUT Z O = Ω In NEG R NC (1) Ω NC (1) R SOURCE = Ω R NC (1) 1 11 R 1Ω +V C 1 C C Component values shown are for GCL = +. See Table I for recommended values for other closed-loop gains. 7pF 1nF.µF Gnd C C C 7pF 1nF.µF V NOTE: (1) NC = Not connected on Demo Board. R 1Ω FIGURE 1. Test Circuit Schematic. 1

17 RECOMMENDED COMPONENTS VALUES Table I summarizes recommended component values for optimum flat frequency response. The recommended values were determined with a 1Ω load resistance and a pf load capacitance. Some adjustment of circuit values may be required, especially with higher load capacitance. According to the behavior shown in Figure 1, the frequency response will show a peaking when the R OG is decreased and will roll off more gradually when R OG is increased. The C OTA capacitor is responsible for the first open-loop pole and a small external capacitor for the gains +1V/V and +V/V is required for stable operation. The package pins, the internal lead frame, and bond wires form a resonant circuit. A resistor in the range of 1Ω to Ω in series with all high impedance inputs will damp the package related resonant circuit. Also, the feedback resistor is in series with the inverting high impedance inputs. Ω is recommended for the DIP package and 1Ω is recommended for the SO-package. AP, I Q = ma, R QC = Ω PLASTIC DIP AU, I Q = ma, R QC = Ω SURFACE-MOUNT G CL G CL Component UNITS Component UNITS 1 7 Ω 1 7 Ω 1 1 Ω 1 1 Ω R Ω R Ω R OG Ω R OG Ω C OTA pf C OTA pf R IL Ω R L Ω R Ω R 1 Ω R Ω R Ω Ring 1 1 Ω Ring 1 1 Ω Bandwidth Bandwidth =.Vp-p MHz =.Vp-p MHz =.Vp-p MHz =.Vp-p 1 MHz TABLE I. Recommended Components Values for Optimum Frequency Performance. FIGURE 17. Silkscreen and Test Circuit Board Layouts. 17

18 Ω Ω Video Input 7Ω 1Ω AP 1 R OG 1Ω 7Ω 7Ω Transmission Line 7Ω 7Ω Bandwidth, (Vp-p) = 1MHz (AP) MHz (AU) 7Ω 7Ω High output current drive capability (Vp-p into Ω) allows three back-terminated 7Ω transmission lines to be simultaneously driven. 7Ω FIGURE 1. Video Distribution Amplifier. +V 1Ω +V V IN1 V IN Ω 1µF X X 1 +V W 1 Wideband Multiplier Y 1 Y V W 1µF Ω 1Ω 1Ω 1Ω 1Ω 1Ω Ω Ω 1µF Ω 1Ω 1Ω V V FIGURE 1. Wideband Multiplier Output Amplifier. V V + IN R IN 1Ω R QC Ω CFA 1pF C OTA = G CL (V + IN - V IN ) + V IN 1Ω R IN 1Ω V IN OB R N 1Ω /R N sets the closed-loop gain; C OTA sets the first open-loop pole; R N sets the open-loop gain. +G CL = 1 + = +V/V R N FIGURE. Current-Feedback Amplifier with Two Equal and High Impedance Inputs. 1

19 PACKAGE DRAWINGS 1