Design Methodologies. Design Trade-offs. System Design to Hardware. Design Gap. Speed (throughput and clock frequency) Area and

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1 Design Trade-offs Design Methodologies Viktor Öwall Dept. of Electrical and Infomation Technology Lund University Parts of this material was adapted from the instructor material to Jan M. Rabaey, Digital Integrated Circuits: A Design Perspective, Prentice Hall International Editions Speed (throughput and clock frequency) Power Consumption Area and Design time (time to market) Price Do not design for maximum performance, design for required performance! Design Gap System Design to Hardware Lo ogic Trans sistors pe er Chip (K K) 10,000, ,000, ,000 10,000 1, Potential ti Design Complexity and Designer Productivity it Complexity growth rate 58%/year Design Gap Productivity growth rate 21%/year (Source: sematech97) Compilation Standard Proc. Threshold Arrhythmia Class. Other sensors Hand Coding Combine Architectural Design System Design MATLAB SystemC CatapultC ASIC Synthesis

2 System Design to Hardware Threshold Arrhythmia Class. Other sensors Combine System Design MATLAB SystemC CatapultC Standard Proc. Design GAP! ASIC Early Design Methodology? Evolution Next, i.e. now: Design Reuse, IP Reuse, Platform based design etc Design Analysis, Specification and Verification Accounts for Largest fraction of Design time (or at least should) More effective on higher levels of abstraction Most design failures due to error in spec. Design Methodology Three abstractions: Behavioral, structural and geometrical

3 Design Methodology, contnd. Moving betwen the domains Amount of Automatization increase Standard Design Flow of Today Standard Processors vs. Special Purpose Software or Hardware? Standard Processor Programmable Low Design cost Standard Interface Good supply of tools Algorithm Processor Cores Domain Specific Processors etc. Special Purpose Flexible Architecture High Calculation Capacity Low Power User defined Interface Variable Wordlength Low Price at Volume Flexibility Performance Requirements Power Consumption Throughputh Cost Volume Know how Time to Market

4 Energy efficiency (MIPS/mW) Energy Efficiencyi 100? High Flexibility Pentium StrongARM TI-DSP Dedicated 4 orders of magnitude Low Flexibility Acknowledgement: Viktor Öwall, Bob Dept. Brodersen of Electrical and Information Technology, Lund University, Sweden- ies ea Efficienci rgy and Are Ene Energy/Area efficiency i Energy Efficiency (MOPS/mW) Microprocessors Area Efficiency (MOPS/mm2) General Purpose DSP s Dedicated d Designs Chip Number (see Table II) Courtesy: Professor Bob Brodersen, UC Berkeley Results in fully parallel solutions Reducing supply voltage saves energy: E = CV 2 Energy Area 64-point FFT Energy per Transform (nj) 16-State Viterbi Decoder Energy per Decoded bit (nj) 64-point FFT Transforms per second per unit area (Trans/ms/mm 2 ) 16-State Viterbi Decoder Decode rate per unit area (kb/s/mm 2 ) Direct-Mapped Hardware , ,000 FPGA Low-Power DSP High-Performance DSP (numbers taken from vendor-published benchmarks) 5000 Orders of magnitude lower efficiency even for an optimized processor architecture Courtesy Ning Zhang, Berkeley Wireless Research Center (BWRC) To reach efficient solutions algorithm/hardware codesign is crucial!

5 Scope This is an Advertisement DSP Design 6credits Period 2, Fall How to get from a signal processing algorithm to an EFFICIENT implementation using Different numbering systems Pipelining Parallelism li Strength reduction, i.e. complexity of operations. etc, etc,... in a structured way! Case studies: FFT, image filtering, acoustic echo cancellation, pacemakers,... From Algorithm to Implementation Many paths! How do we get there? x(n) h0 FIR-filter D D D Time-multiplexed architecture MUX h1 h2 h3 c From Algorithm to Implementation Many paths! How do we get there? x(n) h0 FIR-filter D D D Time-multiplexed architecture MUX h1 h2 h3 c in Signal Processing book y(n) REG in Signal Processing book y(n) REG processor x(2k+1) x(2k) D x(2k-1) D x(2k-2) x(2k+1) x(2k) D x(2k-1) D x(2k-2) b 0 b 1 b 2 b 0 b 1 b 2 y(2k) y(2k) b 0 b 1 b 2 y(2k+1) Parallel architecture b 0 b 1 b 2 ASIC y(2k+1) Parallel architecture FPGA

6 Architectural Design Allocation - determine architectural resources Assignment - binding operations to hardware Scheduling - determine execution order plus transformations pipelining, software pipelining, loop unrolling, etc... and parallelism, hierarchy, etc... Problems in DSP Design (contd) Supplying the MIPS is not the biggest problem but how to get the correct data, to the correct processing element, at the right time at Low Power Implementation Techniques Special Purpose Block RAM BAN NK 7 Virtex BANK 0 BANK 1 BAN NK 2 IOB FPGA ASIC CLB Field Programmable Gate Arrays Reconfigurable Fast Turn Around Prototyping Gate Array Application/Algorithm Specific Integrated Circuit High Calculation Capacity High Utilization Low Power Low Price at Volume Timing BANK 6 BANK 5 BANK 4 BANK 3 Routing

7 Example: Xilinx FPGAs CLB CLB Switching matrix Basic Spartan Architecture Low End FPGA Horizontal Routing Channel CLB CLB Interconnect point Configurable Logic Block Combinational logic Storage elements R Vertical Routing Channel A B/Q 1/Q 2 C/Q 1/Q 2 D A B/Q 1/Q 2 C/Q 1/Q 2 Any function of up to 4 variables Any function of up to 4 variables D in F G F G F R D Q 1 CE R D Q 2 F D G CE G E Clock CE Xilinx Virtex-II Pro Heterogeneous Programmable Platforms FPGA Fabric Embedded System IP blocks High-speed Serial Transceivers 622 Mbps to 10 Gbps PowerPC Processor 400+ MHz clock rate Embedded PowerPc Embedded memories MGT MGT LVDS Technology Hardwired multipliers MGT MGT VCCIO High-speed I/O Courtesy Xilinx 18 Bit 18 Bit 36 Bit Embedded Mult-Acc Z Z Impedance Z Control Logic Cells High Performance RAM * Pricing for 100,000 units in 2004 Courtesy: Ivo Bolsens, CTO Xilinx

8 The Cost/Volume Crossover Relative e Cost 10 ASIC Cost FPGA Cost ,000 10, ,000 1,000K Unit Volume Courtesy: Ivo Bolsens, CTO Xilinx

9 Gate Arrays the old way Fabricating with an array of n- and p-transistors and using design-specific specific metalization in routing channels. Sea-of-Gate Fabricating with an array of n- and p-transistors and using design-specific ifi metalization ti on top of primitive cells. Turn of gates to achieve Oxide-isolation Gate-isolation Before metalization After metalization Gate Array Random Logic The return of gate arrays? Structured ASICs. Structured ASICs are based on a predefined logic fabric in essence, an array of prebuilt logic cells and an arrangement of configurable memory blocks. This array can be fabricated up through the first few metal layers, as if it were a standard product, almost as a cross between an FPGA and a gate array. Then the base wafers can be warehoused, waiting for an order. Ron Wilson of EE Times, Via programmable gate array (VPGA) Via-programmable cross-point Memory section Gate Array LSI Logic (LEA300K) metal-5 metal-6 programmable via Exploits regularity of interconnect [Pileggi02]

10 Design Strategies for ASIC/DSP ASIC Synthesis Full Custom Behavioral or Structural Synthesis Fast Design Process Simplified re-design Semi Custom Design for Performance Flexible Highest Calculation Cap. Lowest Power Smallest area Highest Design Cost Cell based design Macrocell (PLAs, memories, etc ) Standard Cell Datapath compilation Compiled Cell Macros: Memories, mults,... Standard Cell Design RAM Part of Mult Provided Cell library (including macros?) Layout is generated cells of equal height placed in rows automatic placement strategies routing strategies depends on interconnect layers

11 Example of Standard Cell Layout Row ws of Cells V dd & GND Logic cell Functional Module (RAM, ROM, Mult,...) Routing Channel Feedthrough Depends on number of metal layers Datapath Compilation Approach Provided Cell library (including macros?) Bit-sliced approach hierarchical design structure is kept to minimize interconnect abutment or routing in rows routing strategies depends on interconnect layers and placement Datapath th Compilation Approach, contnd. Cell based design, Standard d Cell Die MUX REG1 REG2 MUX REG1 Routing or Abuttment REG2 ADD 1k FFT (S. He) REG3 REG3 Image convolution processor (V. Öwall) Few metal layers, bit-sliced datapaths structure clearly seen More metal layers, synthesis Cell-structure hidden under interconnect layers Part of Complex Mult (A. Berkeman)

12 Abutment vs. Routing Abutment Routing Floorplanning No Interconnect t Routing between cells Exact fit between cells Area loss Denser design Smaller cell library Large cell library Floorplan: Defines overall topology of design, relative placement of modules, and global routes of busses, supplies, and clocks Macrocell Interconnect Bus Routing Channel Example Memories Abutment Magic (Berkeley) Layout Editors Polygon Pushing TILT (LTH) Bit sliced Data Paths

13 What is dominant today? VHDL Based Design A state machine into VHDL library IEEE;use IEEE.STD_LOGIC_1164.all; entity state_machine is generic (m : integer := 2) -- Used to process bus width port (clk : in STD_LOGIC; reset : in STD_LOGIC; input : in STD_LOGIC_VECTOR(m-1 downto 0); output : out STD_LOGIC_VECTOR(m-1 downto 0); end state_machine; architecture implementation of state_machine is type state_type is (st0, st1,st2, st3); -- defines the states; signal state, next_state : state_type; signal output, next_output STD_LOGIC_VECTOR (m-1 downto 0); begin sequential : process (clk) begin if clk event and clk = 1 then if reset = 1 then state <= st0; output t <= 00 ; else state <= next_state; output <= next_output; end if; end if; end process; end architecture; -- registered outputs combinatorial : process (input,output,state,next_state) -- Combinatorial part begin next_state <= state; next_output <= output; case (state) is -- Current state and input dependent when st0 => if (input = 1 ) 1) then next_state <= st1; next_output <= 01 end if; when st1 => if (input = 0 ) then next_state <= st2; next_output t t <= 11 end if; when st2 => if (input = 1 ) then next_state <= st3; next_output <= 10 en if; when st3 => if (input = 1 ) then next_state <= st0; next_output <= 00 end if; when others => next_state <= next_state; -- Default next_output <= 00 ; end case; end process; Hugo Viktor Hedberg, Öwall, Matthias Dept. of Kamuf, Electrical Dept. and of Electroscience, Information Technology, Lund University, Lund {hhg,mkf}@es.lth.se University, Sweden- Then synthesized to ASIC or FPGA Design Flow: a simplified view HDL (VHDL/Verilog/...) Simulation Cell library Synthesis P&R Configuration Post-layout sim. Fabrication

14 Compiled Cell approach No predefined Cell library but cells are compiled according to requirements Stick Diagram to Layout Diemensionles Layout is generated Schematic Compiled layout How to get from Algorithm to Silicon? Complete Specification/Simulation Quantization wordlenghts simple coefficients Architecture (Implementation technique?) Partitioning Dataflow Hardware mapped or microcoded Memory requirements Cell library, clocking,... Netlist Layout What can/should be automated? Design Analysis and Simulation Circuit simulation (Spice, ) Switch-Level simulation (IRSIM, ) Gate-level/Functional simulation (Structural t VHDL) More in Advanced Digital IC Desing.

15 Circuit it Simulation (Spice) V DD Switch-level Simulation (IRSIM) V V dd V M IN OUT t 1 t 2 t Non-linear elements Continuous waveform Solving Differential Equations Timing i Verification - static timing analysis - Critical Path The Design Closure Problem A simulation is the result of the applied signal pattern and does not guarantee the critical path. A timing verifier traverses the network and ranks paths which is a very complex task. Iterative Removal of Timing Violations (white lines) Courtesy Synopsys