ACPL-339J Dual-Output Gate Drive Optocoupler Interface with Integrated (V CE ) DESAT Detection, FAULT and UVLO Status Feedback.

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1 ACPL-339J Dual-Output Gate Drive Optocoupler Interface with Integrated (V CE ) DESAT Detection, FAULT and UVLO Status Feedback Data Sheet Description The ACPL-339J is an advanced 1. A dual-output, easy-touse, intelligent IGBT and Power MOSFET gate drive optocoupler interface. Uniquely designed to support MOSFET buffer of various current ratings, the ACPL-339J makes it easier for system engineers to support different system power ratings using one hardware platform by interchanging the MOSFET buffers and power IGBT/MOSFET switches. These changes can be made without redesigning the critical circuit isolation and short-circuit protection. This concept maximizes gate drive design scalability for motor control and power conversion applications ranging from low to high power ratings. The ACPL-339J contains a AlGaAs LED. The LED is optically coupled to an integrated circuit with two power output stages with active timing control to prevent cross conduction at external MOSFET buffer. It is also integrated with features such as V CE detection, under voltage lockout (UVLO), soft IGBT turn-off, and isolated open collector fault feedback to provide maximum design flexibility and circuit protection. The ACPL-339J has an insulation voltage of V IORM = 1414 V peak in IEC/EN/DIN EN Functional Diagram 3 ANODE 2, 4 CATHODE V CC1 FAULT V GND1 6 7, 8 LED1 SHIELD SHIELD LED2 D RI V E R UVLO_P UVLO_N Drive Logic & Overlap Protection DESAT V CC2 V OUTP V E V OUTN V EE DESAT V GMOS Features Dual output drive for external NMOS and PMOS buffer 1. A minimum peak output current Active timing control to prevent cross conduction in MOSFET buffer IGBT desaturation detection Isolated DESAT and UVLO fault feedback Configurable Soft shutdown during fault Under Voltage Lock-Out Protection (UVLO) with Hysteresis for positive and negative power supply 3 ns maximum propagation delay over temperature range. 6. ma to 1. ma Low LED input current 2 kv/µs Minimum Common Mode Rejection (CMR) at V CM = V Wide Operating V CC Range: to 3 Volts Industrial temperature range: -4 C to C SO-16 package Safety Approval Pending UL Recognized V RMS for 1 min. CSA IEC/EN/DIN EN V IORM = 1414 V peak Applications IGBT/Power MOSFET gate drive Interface AC and brushless DC motor drives Renewable energy inverters Industrial Inverters Switching power supplies CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

2 Pin Description NC CATHODE ANODE V E DESAT V GMOS Pin Symbol Description 1 NC No connection 2 CATHODE Cathode 3 ANODE Anode CATHODE V GND1 V CC1 FAULT V GND1 V CC2 V OUTP V OUTN NC V EE CATHODE Cathode V GND1 Input ground 6 V CC1 Positive input supply voltage. (3.3 V ± %, V± %) 7 FAULT Fault output. FAULT changes from logic low to high output: a) after T BLANK (set by C BLANK and the internal current source of 2 μa), once the voltage on the DESAT pin exceeding an internal reference voltage of 8 V (reference to V E ) b) UVLO condition 8 V GND1 Input ground 9 V EE Output supply voltage. 1 NC No connection 11 V OUTN Low side voltage output 12 V OUTP High side voltage output 13 V CC2 Positive output supply voltage 14 V GMOS V GMOS will switch from V EE to V E after DESAT is activated DESAT Desaturation voltage input. When the voltage on DESAT exceeds an internal reference voltage of 8 V while the IGBT is on, FAULT and V GMOS outputs are changed from logic low to high state. 16 V E Common (IGBT emitter) output supply voltage. Ordering Information ACPL-339J is UL Recognized with Vrms for 1 minute per UL77. Part number Option RoHS Compliant Package Surface Mount Tape & Reel IEC/EN/DIN EN Quantity ACPL-339J -E SO-16 X X 4 per tube -E X X X 8 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACPL-339J-E to order product of SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN Safety Approval in RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. 2

3 Package Outline Drawings ACPL-339J 16-Lead Surface Mount Package.18 (.47) (1.27) LAND PATTERN RECOMMENDATION.2 (.64 ) A 339J YYWW.29 ±.1 (7.493 ±.24) TYPE NUMBER DATE CODE.48 (11.63) ±.1 (1.312 ±.24) ±.1 (8.986 ±.24).8 (2.16) ALL LEADS TO BE COPLANAR ±.2.18 (.47).138 ±. (3. ±.127) -8.2 MIN..48 ±.1 (1.16 ±.24).8 ±.3 (.23 ±.76) STANDOFF Dimensions in inches (millimeters) Notes: Initial and continued variation in the color of the ACPL-339J s white mold compound is normal and does note affect device performance or reliability. Floating Lead Protrusion is.2 mm (1 mils) max. Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-2 (latest revision). Non- Halide Flux should be used. Regulatory Information The ACPL-339J is pending approval by the following organizations: IEC/EN/DIN EN Maximum working insulation voltage V IORM = 1414 V PEAK UL Approval under UL 77, component recognition program up to V ISO = V RMS. File E361. CSA Approval under CSA Component Acceptance Notice #, File CA

4 Table 1. IEC/EN/DIN EN Insulation Characteristics* Description Symbol Characteristic Unit Installation classification per DIN VDE 11/39, Table 1 for rated mains voltage V rms for rated mains voltage 3 V rms for rated mains voltage 6 V rms for rated mains voltage 1 V rms I IV I IV I IV I III Climatic Classification 4//21 Pollution Degree (DIN VDE 11/39) 2 Maximum Working Insulation Voltage V IORM 1414 V peak Input to Output Test Voltage, Method b** V IORM x 1.87 = V PR, 1% Production Test with t m = 1 sec, Partial discharge < pc Input to Output Test Voltage, Method a** V IORM x 1.6 = V PR, Type and Sample Test, t m = 1 sec, Partial discharge < pc V PR 262 V peak V PR 2262 V peak Highest Allowable Overvoltage (Transient Overvoltage t ini = 6 sec) V IOTM 8 V peak Safety-limiting values maximum values allowed in the event of a failure. Case Temperature T S 17 C Input Current I S, INPUT 4 ma Output Power P S, OUTPUT 12 mw Insulation Resistance at T S, V IO = V R S >1 9 W * Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. Surface mount classification is class A in accordance with CECCOO82. ** Refer to the optocoupler section of the Isolation and Control Components Designer s Catalog, under Product Safety Regulations section IEC/EN/ DIN EN , for a detailed description of Method a and Method b partial discharge test profiles. Table 2. Insulation and Safety Related Specifications Parameter Symbol ACPL-339J Units Conditions Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) L(11) 8.3 mm Measured from input terminals to output terminals, shortest distance through air. L(12) 8.3 mm Measured from input terminals to output terminals, shortest distance path along body.. mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. CTI >17 V DIN IEC 112/VDE 33 Part 1 Isolation Group IIIa Material Group (DIN VDE 11, 1/89, Table 1) 4

5 Table 3. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature T S - 12 C Operating Temperature T A -4 C Output IC Junction Temperature T J 12 C Average Input Current I F(AVG) 2 ma 1 Peak Transient Input Current (< 1 µs pulse width, 3 pps) I F(TRAN) 1. A Reverse Input Voltage V R V High Peak Output Current I OH(PEAK). A 2 Low Peak Output Current I OL(PEAK). A 2 Positive Input Supply Voltage V CC1 7 V FAULT Output Current I FAULT 8 ma FAULT Pin Voltage V FAULT -. V CC1 V Total Output Supply Voltage (V CC2 V EE ) 3 V Negative Output Supply Voltage (V E V EE ) 17 V Positive Output Supply Voltage (V CC2 V E ) 3 (V E V EE ) V High Side Output Voltage V OUTP(PEAK) V E. V CC2 +. V Low Side Output Voltage V OUTN(PEAK) V EE. V E +. V DESAT Voltage V DESAT V E. V CC2 +. V V GMOS Voltage V GMOS V EE. V E +. V Output IC Power Dissipation P O 6 mw 3 Input LED Power Dissipation P I mw 4 Notes: 1. Derate linearly above 7 C free-air temperature at a rate of.3 ma/ C. 2. Maximum pulse width = 1 µs 3. Derate linearly above 9 C free-air temperature at a rate of 2 mw/ C. 4. Derate linearly above 9 C free-air temperature at a rate of 4 mw/ C. The maximum LED junction temperature should not exceed 12 C. Table 4. Recommended Operating Conditions Parameter Symbol Min. Max. Units Note Operating Temperature T A -4 C Positive input supply voltage V CC V Total Output Supply Voltage (V CC2 V EE ) 21 3 V Negative Output Supply Voltage (V E V EE ) 6 V Positive Output Supply Voltage (V CC2 V E ) 3 (V E V EE ) V Input Current (ON) I F(ON) 6 1 ma Input Voltage (OFF) V F(OFF) V

6 Table. Electrical Specifications (DC) Unless otherwise noted, all typical values at T A = 2 C, V CC1 = 3.3 V or V, V CC2 V E = V, V E V EE = 8 V; all Minimum/ Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note V OUTP High Level Output Current V OUTP Low Level Output Current V OUTN High Level Output Current V OUTN Low Level Output Current I OUTPH -1 A V CC2 V OUTP V 3 1 I OUTPL 1 A V OUTP V E V 4 1 I OUTNH -1 A V E V OUTN 8 V 3 1 I OUTNL 1 A V OUTN - V EE 8 V 4 1 V OUTP High Level R OUTPH 3. 7 Ω I OUTP = -1 A, V F = V 3, 1 Output R DSON V OUTP Low Level R OUTPL 1. 4 Ω I OUTP = 1 A, I F = 8 ma 4, 6 1 Output R DSON V OUTN High Level R OUTNH 3. 7 Ω I OUTN = -1 A, V F = V 3, 1 Output R DSON V OUTN Low Level R OUTNL 1. 4 Ω I OUTN = 1 A, I F = 8 ma 4, 6 1 Output R DSON V OUTP High Level Output Voltage V OUTP Low Level Output Voltage V OUTN High Level Output Voltage V OUTN Low Level Output Voltage V GMOS High Level Output Current V GMOS Low Level Output Current V OUTPH V CC2.6 V CC2.3 V I OUTP = -1 ma, V F = V 1 2, 4, V OUTPL V E +.14 V E +. V I OUTP = 1 ma, I F = 8 ma 2 V OUTNH V E.6 V E.3 V I OUTN = -1 ma, V F = V 1 3, 4, V OUTNL V EE +.12 V EE +.6 V I OUTN = 1 ma, I F = 8 ma 2 I OUTGH -8 ma V E V GMOS 8 V, I F = 8 ma, DESAT = Open I OUTGL 8 ma V GMOS V EE 8 V, V F = V, DESAT = Open V GMOS High Level R OUTGH 22 3 Ω I OUTG = -8 ma, I F = 8 ma 7 Output R DSON V GMOS Low Level R OUTGL 6 1 Ω I OUTN = 8 ma, V F = V, Output R DSON DESAT = Open V GMOS High Level Output Voltage V GMOS Low Level Output Voltage High Level Output Supply Current (V CC2 ) V OUTGH V E V I OUTG = ma, I F = 8 ma, DESAT = Open V OUTGL V EE V I OUTN = ma, V F = V, DESAT = Open I CC2H ma V F = V, No Load 9, 1 Low Level Output I CC2L ma I F = 8 ma, No Load, 9, 1 Supply Current (V CC2) High Level Output Supply Current (V EE ) Low Level Output Supply Current (V EE ) Threshold Input Current Low to High Threshold Input Voltage High to Low I EEH 8 11 ma V F = V, No Load 11, 12 I EEL 8 11 ma I F = 8 ma, No Load 11, 12 I FLH 1.3 ma No Load, V OUTP V E < V, V OUTN V EE < 1 V V FHL.8 V No Load, V OUTP V E > V, V OUTN V EE > 1 V 8 13, 14 6

7 Table. Electrical Specifications (DC) (continued) Unless otherwise noted, all typical values at T A = 2 C, V CC1 = 3.3 V or V, V CC2 V E = V, V E V EE = 8 V; all Minimum/ Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Input Forward Voltage V F V I F = 8 ma Temperature Coefficient of Input Forward Voltage Input Reverse Breakdown Voltage ΔV F /ΔT A -1.7 mv/ C I F = 8 ma BV R V I R = 1 ma Input Capacitance C IN 7 pf f = 1 MHz, V F = V UVLO_P Threshold, V UVLOP V I F = 8 ma, V OUTP V E < V 31 2,, 6 V CC2 -V E V UVLOP V I F = 8 ma, V OUTP V E > V 31 3,, 7 UVLO_P Hysteresis, V CC2 -V E V UVLOP+ 1 V - V UVLOP- UVLO_N Threshold, V UVLON V I F = 8 ma, V OUTN V EE < 1 V 31 2,, 8 V E -V EE V UVLON V I F = 8 ma, V OUTN V EE > 1 V 31 3,, 9 UVLO_N Hysteresis, V E -V EE V UVLON+.3 V - V UVLON- DESAT Threshold V DESAT V V CC2 V E > V UVLOPand V E V EE > V UVLON- Blanking Capacitor Charging Current DESAT Low Voltage when Blanking Capacitor Discharge FAULT Logic Low Output Voltage FAULT Logic High Output Voltage FAULT Logic Low Output Current FAULT Logic High Output Current I CHG ma V DESAT = 2 V 16, 1 V DSCHG V I DSCHG = 1 ma, 1 V FAULTL.1.2 V V DESAT = V, R F = 1 kω, C F = 1 nf, V CC1 = V or 3.3 V V FAULTH V CC1 V DESAT = Open, R F = 1 kω, C F = 1 nf, V CC1 = V or 3.3 V I FAULTL.2 ma V FAULT =. V, V CC1 = V or 3.3 V I FAULTH.2 1 µa V FAULT = V CC1 = V or 3.3 V Notes: 1. Output is sourced at -1. A / 1. A with a maximum pulse width = 1 μs. 2. V is the recommended minimum operating positive supply voltage (V CC2 V E ) to ensure adequate margin in excess of the maximum V UVLOP+ threshold of 13. V. For High Level Output Voltage testing, V OUTP is measured with a ms pulse load current. When driving capacitive loads, V OUTP will approach V CC as I OUTPH approaches zero units V is the recommended minimum operating positive supply voltage (V E V EE ) to ensure adequate margin in excess of the maximum V UVLON+ threshold of.6 V. For High Level Output Voltage testing, V OUTN is measured with a ms pulse load current. When driving capacitive loads, V OUTN will approach V E as I OUTNH approaches zero units. 4. Maximum pulse width = 1. ms.. Once V OUTP is allowed to go low (V CC2 V E > V UVLOP+ ) and V OUTN is allowed to go high (V E V EE > V UVLON+ ), the DESAT detection feature of the ACPL-339J will be the primary source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once V CC2 V E > V UVLOP+ and V E V EE > V UVLON+, DESAT will remain functional until V CC2 V E < V UVLOP- or V E V EE < V UVLON-,. Thus, the DESAT detection and UVLO features of the ACPL-339J work in conjunction to ensure constant IGBT protection. 6. This is the increasing (i.e. turn-on or positive going direction) of V CC2 V E. 7. This is the decreasing (i.e. turn-off or negative going direction) of V CC2 V E. 8. This is the increasing (i.e. turn-on or positive going direction) of V EE V E. 9. This is the decreasing (i.e. turn-ff or negative going direction) of V EE V E. 1. See the DESAT fault detection blanking time section in the applications notes at the end of this data sheet for further details. 7

8 Table 6. Switching Specifications (AC) Unless otherwise noted, all typical values at T A = 2 C, V CC1 = 3.3 V or V, and V CC2 V E = V, V E V EE = 8 V; all Minimum/ Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time to High Output Level Propagation Delay Time to Low Output Level t PLH ns C P = C N = 4 nf, 17, 18, 3 1 f = 2 khz, t PHL 1 3 ns Duty Cycle = %, I F = 6 ma to 1 ma 17, 18, 3 1 Pulse Width Distortion PWD 2 ns 2 Propagation Delay Difference Between Any Two Parts PDD (t PLH t PHL ) -2 2 ns 36, 37 3 LED OFF to 9% of V OUTP t DP 2 ns 17,18, 3 LED ON to 1% of V OUTN t DN 12 2 ns 17,18, 3 Non-overlap Time Low to High t NLH 3 ns 2, 3 Non-overlap Time High to Low t NHL 2 ns 2, 3 1% to 9% Rise Time on V OUTP t PR 4 ns C P = C N = 4 nf, 3 9% to 1% Fall Time on V f = 2 khz, OUTP t PF 4 ns 3 Duty Cycle = %, 1% to 9% Rise Time on V OUTN t NR 4 ns I F = 8 ma 3 9% to 1% Fall Time on V OUTN t NF 3 ns 3 Delay time from DESAT threshold to % of High V GMOS t 1 2 ns C P = C N = 4 nf, C G = 1 nf, f = 2 Hz, Delay time from DESAT Duty Cycle = %, I F = 8 ma 19, 22, 28, 29 threshold to % of High V OUTP t 2 2 ns 19, 28, 29 Delay time from DESAT threshold to % of High FAULT Delay from % of V GMOS to % of V OUTN t μs R F = 1 kω, C F = 1 nf, V CC1 = 3.3 V or V, f = 2 Hz, Duty Cycle = %, I F = 8 ma t 4 11 ns C P = C N = 4 nf, C G = 1 nf, f = 2 Hz, Duty Cycle = %, I F = 8 ma Mute time t MUTE ms f = 7 Hz, Duty Cycle = %, I F = 8 ma Output High Level Common Mode Transient Immunity Output Low Level Common Mode Transient Immunity CM H 2 3 kv/μs T A = 2 C, V CM = V, V CC1 = V, C F = 1 nf, R F = 1 kω, I F = 8 ma with split resistors CM L 2 3 kv/μs T A = 2 C, V CM = V, V CC1 = V, C F = 1 nf, R F = 1 kω, V F = V 2, 28, 29 21, 23, 28, 29 24, 28, 29 4 Notes: 1. This load condition approximates the gate load of a 6V/A MOSFET 2. Pulse Width Distortion (PWD) is defined as t PHL t PLH for any given unit. 3. The difference between t PHL and t PLH between any two ACPL-339J parts under the same test conditions. 4. Auto Reset: This is the minimum amount of time when V OUTP will be asserted high, V OUTN asserted low, V GMOS asserted high and FAULT asserted high, after DESAT threshold is exceeded. See the Description of Operation (Auto Reset) topic in the application information section.. Common mode transient immunity in the high state is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in the high state (i.e., V OUTP V E > 12 V, V OUTN V EE > V or FAULT > 2 V). A 1 nf and a 1 kω pull-up resistor is needed in fault detection mode. 6. Common mode transient immunity in the low state is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in a low state (i.e., V OUTP V E < 1. V, V OUTN V EE < 1. V or FAULT <.8 V). 6 8

9 Table 7. Package Characteristics Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Input-Output Momentary Withstand Voltage V ISO V rms RH < %, t = 1 min., T A = 2 C Input-Output Resistance R I-O > 1 9 W V I-O = V 2 Input-Output Capacitance C I-O 1.3 pf freq =1 MHz Notes 1. In accordance with UL77, each optocoupler is proof tested by applying an insulation test voltage 6 Vrms for 1 second. This test is performed before the 1% production test for partial discharge (method b) shown in IEC/EN/DIN EN Insulation Characteristic Table, if applicable. 2. Device considered a two-terminal device: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together. 1, 2 HIGH OUTPUT VOLTAGE DROP - V V F = V I OUT = -1 ma VOUTPH-VCC2 VOUTNH-VE Figure 1. V OUTPH /V OUTNH vs. temperature LOW OUTPUT VOLTAGE DROP - V I F = 8 ma I OUT = 1 ma VOUTPL-VE VOUTNL-VEE Figure 2. V OUTPL /V OUTNL vs. temperature OUTPUT HIGH CURRENT - A V F = V T A = 2 C V OUTPH -V CC2 /V OUTNH -V E - V -12 IOUTPH IOUTNH OUTPUT LOW CURRENT - A I F = 8 ma T A = 2 C V OUTPL -V E /V OUTNL -V EEE - V 12 IOUTPL IOUTNL 14 Figure 3. I OUTPH /I OUTNH vs.v OUTPH /V OUTNH Figure 4. I OUTPL /I OUTNL vs.v OUTPL /V OUTNL 9

10 HIGH OUTPUT RDSON - Ω V F = V I OUT = -1 A ROUTPH ROUTNH Figure. R OUTPH /R OUTNH vs. temperature LOW OUTPUT RDSON - Ω I F = 8 ma I OUT = 1 A ROUTPL ROUTNL Figure 6. R OUTPL /R OUTNL vs. temperature VGMOS HIGH OUTPUT RDSON - Ω I F = 8 ma I OUTG = -8 ma Figure 7. R OUTGH vs. temperature VGMOS LOW OUTPUT RDSON - Ω V F = V I OUTG = -8 ma 1 DESAT = OPEN Figure 8. R OUTGL vs. temperature VCC2 SUPPLY CURRENT - ma V F = V (ICC2H) I F = 8 ma (ICC2L) ICC2H ICC2L Figure 9. I CC2 vs. temperature VCC2 SUPPLY CURRENT - ma I F = 8 ma (ICC2L) 8.2 V F = V (ICC2H) T A = 2 C ICC2L 8.2 V E -V EE = 6 V ICC2H V CC2 -V E - V Figure 1. I CC2 vs. V CC2 1

11 VEE SUPPLY CURRENT - ma V F = V (IEEH) I F = 8 ma (IEEL) IEEH IEEL Figure 11. I EE vs. temperature VEE SUPPLY CURRENT - ma I F = 8 ma (IEEL) 7.9 V F = V (IEEH) T A = 2 C IEEL V CC2 -V E = V IEEH V E -V EE - V Figure 12. I EE vs. V EE VOUTP/VOUTN OUT VOLTAGE - V VOUTP VOUTN LOW TO HIGH INPUT CURRENT THRESHOLD - ma Figure 13. V OUTPH /V OUTNH vs. I FLH T A = 2 C LOW TO HIGH CURRENT THRESHOLD - ma IFLH ON IFLH OFF Figure 14. I FLH vs. temperature VDESAT DESAT THRESHOLD - V Figure. V DESAT vs. temperature ICHGB LANKING CAPACITOR CHARGING CURRENT - µa Figure 16. I CHG vs. temperature 11

12 tp/td PROPAGATION DELAY - ns C P /C N = 4 nf f = 2 khz DC = % tphl tplh tdp tdn Figure 17. t P /t D vs. temperature tp/td PROPAGATION DELAY - ns I F = 8 ma T A = 2 C f = 2 khz DC = % tphl tplh tdp tdn C P /C N - LOAD CAPACITANCE - nf Figure 18. t P /t D vs. C P /C N t1/t2 DELAY TIME - ns C P /C N = 4 nf f = 2 Hz DC = % Figure 19. t 1 /t 2 vs. temperature t1 t2 t3 DELAY TIME - ns C F = 1 nf R F = 1 kω f = 2 Hz DC = % Figure 2. t 3 vs. temperature t4 DELAY TIME - ns C G = 1 nf f = 2 Hz DC = % Figure 21. t 4 vs. temperature t1 DELAY TIME - ns C P /C N = 4 nf 1 I F = 8 ma T A = 2 C f = 2 Hz DC = % C G - LOAD CAPACITANCE - nf Figure 22. t 1 vs. C G 12

13 t4 DELAY TIME - ns I F = 8 ma T A = 2 C f = 2 Hz DC = % C N /C G - LOAD CAPACITANCE - nf Figure 23. t 4 vs. C N /C G f = 7 Hz.88 DC = % Figure 24. t MUTE vs. temperature tmute MUTE TIME - ms tnlh/tnhl NON-OVERLAP TIME - ns C P /C N = 4 nf f = 2 khz DC = % t NLH t NHL Figure 2. t NLH /t NHL vs. temperature 13

14 Applications Information Product Overview Description 3 ANODE 2, 4 CATHODE LED1 D R I V E R UVLO_P Drive Logic & Overlap Protection V CC2 V OUTP V E V CC1 FAULT 6 7 SHIELD LED2 UVLO_N 11 9 V OUTN V EE DESAT, 8 V GND1 SHIELD DESAT 14 V GMOS Figure 26. Block Diagram of ACPL-339J Recommended Application Circuit R NC CATHODE ANODE V E DESAT V GMOS µf 1 µf C BLANK 1 Ω 33 Ω D DESAT + _ R 4 CATHODE V GND1 V CC2 V OUTP ^R P *MP1 + _ R GP R S = 33 Ω Q1 + V CE _ + _.3 µf R F = 1 kω C F = 1 nf V CC1 FAULT V GND1 V OUTN NC V EE µf ^R N *MN1 + _ MP1 = Si74DN/Si746DP MN1 = Si7414DN/Si7848DP MN2 = Si2318 MN3 = BSP149 * MP1 and MN1 equivalent C LOAD to be < nf ^ R P and R N is not required unless capacitive loading of MP1 or MN1 draws > 4 A of peak current. R GN MN2 MN3 Q2 Figure 27. Typical de-saturation protected gate drive circuit, non-inverting 14

15 Output Control The outputs (V OUTP, V OUTN, V GMOS and FAULT) of the ACPL-339J are controlled by the combination of I F, UVLO and DESAT conditions. Once UVLO_P and UVLO_N is not active (V CC2 - V E > V UVLOP+, V E - V EE > V UVLON+ ), V OUTP is allowed to go low and V OUTN is allowed to go high. Thereafter, the DESAT (pin ) detection feature of the ACPL-339J will be the primary source of IGBT/MOSFET protection. DESAT will remain functional until V CC2 - V E is decreased below V UVLOP- or V E - V EE is decreased below V UVLON-. Thus, the DESAT detection and UVLO features of the ACPL-339J work alternatively to ensure constant IGBT/MOSFET protection. I F UVLO_P and UVLO_N DESAT Function Pin 7 (FAULT) Output V OUTP V OUTN V GMOS X Active Not Active V CC1 V CC2 V E V E ON Not Active Active (with DESAT fault) V CC1 V CC2 V EE V E ON Not Active Active (no DESAT fault) V GND1 V E V EE V EE OFF Not Active Not Active V GND1 V CC2 V E V EE Description of Operation during DESAT Fault Condition The DESAT pin monitors the IGBT Vce voltage. The DESAT fault detection circuitry must remain disabled for a short time period following the turn-on of the IGBT to allow the collector voltage to fall below the DESAT threshold. This time period, called the DESAT blanking time, is controlled by the internal DESAT charge current, the DESAT voltage threshold, and the external DESAT capacitor. The nominal blanking time is calculated in terms of external capacitance (C BLANK ), FAULT threshold voltage (V DESAT ), and DESAT charge current (I CHG ) as T BLANK = C BLANK x V DESAT / I CHG. The nominal blanking time with the recommended 1 pf capacitor is 1 pf * 8 V/2 µa = 3.2 µsec. The capacitance value can be scaled slightly to adjust the blanking time, though a value smaller than 1 pf is not recommended. This nominal blanking time also represents the longest time it will take for the ACPL-339J to respond to a DESAT fault condition. Once DESAT fault is detected and after T BLANK time, both V OUTP and V OUTN will turn off the respective external MP1 and MN1 and V GMOS switches from low to high, turning on an external MN2 pull down device, in order to softly turn-off the IGBT. Also activated is an internal feedback channel which brings the FAULT output from low to high for the purpose of notifying the micro-controller of the fault condition. Once fault is detected, the output will be muted for T MUTE time. All input LED signals will be ignored during the mute period to allow the driver to completely soft shut down the IGBT. The fault is auto-reset upon the 1ms (typical) mute time (T MUTE ) timeout or upon LED INPUT high to low transition, whichever is later. In this way, there is a minimum timeout but also the flexibility of lengthening the timeout freely. See Figure 28 and 29. Soft IGBT Shut Down during Fault Condition When a DESAT fault is detected, V GMOS switches from low to high, turning on an external MN2 pull down device. MN2 slowly discharges the IGBT gate at a decay rate corresponding to the RC constant of R S and C IN (IGBT input capacitance). Based on a R S of 33 Ω and C IN of 1 nf, the entire soft shut down will decay in 4.8 * 33 Ω * 1 nf =.8 µs. Soft shut down prevents fast changes in the collector current that can cause damaging voltage spikes due to lead and wire inductance.

16 I F LED ON LED OFF 8V V DESAT V GMOS V G(IGBT) t 1 Soft Shut Down V OUTN Ext NMOS(MN1) OFF Ext NMOS ON Ext NMOS OFF t 4 V OUTP Ext PMOS(MP1) OFF Ext PMOS ON FAULT t 2 Internal DESAT T MUTE Timer t 3 t MUTE Figure 28. DESAT Fault State Timing Diagram with LED turn OFF before the T MUTE timeout I F LED ON LED OFF 8V V DESAT V GMOS V G(IGBT) t 1 Soft Shut Down V OUTN Ext NMOS(MN1) OFF Ext NMOS ON t 4 V OUTP Ext PMOS(MP1) OFF FAULT t 2 Internal DESAT T MUTE Timer t 3 t MUTE Figure 29. Desat Fault State Timing Diagram with LED OFF after the T MUTE timeout 16

17 Timing Diagram & Cross-Conduction Scheme I F t DP t PHL t PR t PF V OUTP Ext PMOS(MP1) OFF V CC2 V TH(PMOS) V OUTN t NLH Ext NMOS (MN1) ON t NHL t NR t NF V EE + V TH(NMOS) t PLH t DN V G(IGBT) IGBT OFF IGBT ON IGBT OFF Figure 3. Timing diagram and Cross Conduction Scheme The MOS Driver monitors V OUTP & V OUTN to detect for V CC2 - V OUTP or V OUTN -V EE equals V TH(MOS) during the respective external MOSFET s turn-off transition. Upon detection, the complimentary V OUT is turned on after some inherent delay t NLH /t NHL. Description of Under Voltage Lock Out Insufficient gate voltage to IGBT can increase turn on resistance of IGBT, resulting in large power loss and IGBT damage due to high heat dissipation. ACPL-339J monitors the output power supply constantly. When output power LED1 ON supply is lower than under voltage lockout (UVLO) threshold gate driver output will shut off to protect IGBT from low voltage bias. ACPL-339J has two UVLO logic blocks, UVLO_P and UVLO_N to control the V OUTP and V OUTN respectively. The UVLO control logic takes precedence over input I F and DESAT. In another words, I F and DESAT are ignored when V CC2 and V EE supplies are not sufficient causing UVLO clamp to be active. Both V UVLOP+ and V UVLON+ will need to be crossed before the clamp can be released. Thereafter, V OUTP and V OUTN will respond to I F and DESAT accordingly. LED1 ON V CC2 V V CC2 V V UVLOP+ V UVLOP+ V E time V E time V UVLON+ 8 V V UVLON+ 8 V V EE V EE V OUTP V OUTP V V V E time V E time 8 V 8 V V OUTN V OUTN FAULT FAULT V CC1 V CC1 V GND1 time V GND1 time Figure 31. UVLO, V OUT and FAULT logic diagram 17

18 Drive and Shutdown MOSFET Selection The MOSFETs, MP1 and MN1 driving strength can be estimated by the gate charge and desired charge time needed. The equation below shows an example of this: Qg = I CHARGE x T CHARGE Qg is the total gate charge that can be picked readily from the IGBT data sheets. For a 12/ A IGBT, the typical Qg is approximately 3 nc and for desired charging time of 2 ns, the I CHARGE will be, I CHARGE = 3 nc / 2 ns = 1. A The charging current calculated is an average current. The peak gate current of the MOSFET driver can be estimated using the rule of thumb of doubling the I CHARGE. So for this example, a 3 A peak current MOSFET driver rating will be appropriate. Listed in the table below, are some recommended MOSFET ratings and part numbers suitable for their respective IGBT class. Applications IGBT Class Qg Low Power 12 V / A 3 nc 3A Sanyo ECH8619 Mid Power 12 V / 3 A 2 nc 8A Vishay SI7414 High Power 12 V / 6 A 4 nc 16A Vishay SIS434 Estimated Peak Charging Current MN1 MP1 MN2 MN3 Sanyo ECH8619 Vishay SI74 Vishay SI7611 Vishay SI238 Vishay SI238 Fairchild FDC612 Siemens BSS9 Siemens BSS9 CLARE CPC373 Selecting the Gate Resistor (R G ) The IGBT switching time is determined by the charging and discharging of the gate of the IGBT. Higher gate peak current will decrease the turn-on and turn-off time and hence reduce the the switching losses. The charging and discharging currents are controlled by the gate resistors R GP and R GN respectively. The R G must be able to limit the peak current below the maximum allowed for the PMOS(MP1) and NMOS(MN1). The internal R DSON of MP1 and MN1 must be taken into account when calculating the peak current. VCC VEE RGP IOP(MAX) RDSONP VCC VEE RGN ION(MAX) RDSONN Other Recommended Components The application circuit in Figure 27 includes a depletion-mode MOSFET, a DESAT pin protection resistor, FAULT pin capacitor and pull-up resistor, false FAULT prevention diodes. 18

19 Split Resistors Input LED Drive Circuit Figure 32 shows the recommended drive circuit that gives optimum common-mode rejection. The two current setting resistors balance the common mode impedances at the LED s anode and cathode. This helps to equalize the common mode voltage change at the anode and cathode. µc + V R 1 R 2 Figure 32. Split Resistors Input LED Drive Circuit Depletion-mode MOSFET V DD =. V: R 1 = 287 Ω ±1% R 2 = 143 Ω ±1% R 1 /R 2 2 NC CATHODE ANODE CATHODE V GND1 During start-up, the supplies across V CC2 and V EE build up slowly from V. It will be harmful to allow the gate driver output to turn on at low supply voltages. UVLO protection kicks in to prevent ACPL-339J outputs from turning on until the supplies reach the UVLO thresholds. But IGBT or Power MOSFET can still be triggered by Miller effect developed by any high dv/dt noise across collector and emitter pins. This miss-triggering can be prevented by depletion-mode MOSFET, MN3. A depletion-mode MOSFET will conduct even if its gate voltage is at V with respect to its source pin voltage. During start-up, the V GMOS output voltage stays high, at V E, to turn on MN3 to shunt away any miller current that appears at the IGBT gate. This will prevent the IGBT from miss-triggering. After the supplies cross the UVLO thresholds, V GMOS output voltage will at V EE to turn off MN3 and resume normal Inverter operations. MN3 is optional for extra protection. DESAT Diode and DESAT Threshold The DESAT diode s function is to conduct forward cur rent, allowing sensing of the IGBT s saturated collector-toemitter voltage, V CESAT, (when the IGBT is on ) and to block high voltages (when the IGBT is off ). During IGBT switching off and towards the end of the forward conduction of the DESAT diode, a reverse current flow for short time. This reverse recovery effect causes the diode not able to achieve its blocking capability until the mobile charge in the junction is depleted. During this time, there is commonly a very high dv CE /dt voltage ramp rate across the IGBT s collector-to-emitter. This results in I CHARGE = C D-DESAT x dv CE /dt charging current which will charge the blanking capacitor, C BLANK. In order to minimize this charging current and avoid false DESAT triggering, it is best to use fast response diodes. Listed in the below table are fast-recovery diodes that are suitable for use as a DESAT diode (D DESAT ). In the recommended appli cation circuit shown in Figure 27, the voltage on pin (DESAT) is V DESAT = V F + V CE, (where V F is the forward ON voltage of D DESAT and V CE is the IGBT collector-to-emit ter voltage). The value of V CE which triggers DESAT to signal a FAULT condition, is nominally 8 V V F. If desired, this DESAT threshold voltage can be decreased by using multiple DESAT diodes or low voltage zener diode in series. If n is the number of DE SAT diodes, the nominal threshold value becomes V CE,FAULT(TH) = 8 V n x V F. If zener diode is used, the nominal threshold value becomes V CE,FAULT(TH) = 8 V V F V z. In the case of using two diodes instead of one, diodes with half of the total required maximum reverse-voltage rating may be chosen. V E DESAT V GMOS 16 C BLANK 14 1 Ω Figure 33. DESAT Diode and DESAT threshold D ZENER DDESAT Q1 + V CE Part Number Manufacturer t rr (ns) 19 Max. Reverse Voltage Rating, V RRM (Volts) Package Type MUR11E Motorola (axial leaded) MURS16T3 Motorola 7 6 Case 43A (surface mount) UF47 General Semi. 7 1 DO-24AL (axial leaded) BYM26E Philips 7 1 SOD64 (axial leaded) BYV26E Philips 7 1 SOD7 (axial leaded) BYV99 Philips 7 6 SOD87 (surface mount)

20 DESAT Pin Protection Resistor The freewheeling of flyback diodes connected across the IGBTs can have large instantaneous forward voltage transients which greatly exceed the nominal forward voltage of the diode. This may result in a large negative voltage spike on the DESAT pin which will draw substantial current out of the driver if protection is not used. To limit this current to levels that will not damage the driver IC, a 1 ohm resistor should be inserted in series with the DESAT diode. The added resistance will not alter the DESAT threshold or the DESAT blanking time. False Fault Prevention Diodes One of the situations that may cause the driver to generate a false fault signal is if the substrate diode of the driver becomes forward biased. This can happen if the reverse recovery spikes coming from the IGBT freewheeling diodes bring the DESAT pin below ground. Hence the DESAT pin voltage will be brought above the threshold voltage. This negative going voltage spikes is typically generated by inductive loads or reverse recovery spikes of the IGBT/MOSFETs free-wheeling diodes. In order to prevent a false fault signal, it is highly recommended to connect a zener diode and schottky diode across the DESAT pin and V E pin This circuit solution is shown in Figure 34. The schottky diode will prevent the substrate diode of the gate driver optocoupler from being forward biased while the zener diode (value around 7. to 8 V) is used to prevent any positive high transient voltage to affect the DESAT pin. FAULT Pin Capacitor and Pull-up Resistor UVLO fault is feedback to the FAULT pin through LED2. If LED2 is normally-off during normal operation, a V CC2 or V EE power supplies fault might result in insufficient drive current to turn on LED2 to report the UVLO fault. To avoid such a condition, LED2 need to be normally-on during normal operations. To reduce power consumption, LED2 operates at % duty cycle at a frequency of MHz provided by an internal oscillator. A RC network at the FAULT pin is required to filter this oscillation to read a stable low for no fault condition. The RC network consists of a FAULT pin capacitor, C F and a pull-up resistor R F. To achieve effective filtering and high CMR, a 1 nf capacitor should be connected between the FAULT pin and ground, and a 1 KΩ pull-up resistor between FAULT pin and V CC1. Due to the active high FAULT logic, the FAULT pins of more than one ACPL-339J cannot be tied together to achieve a common FAULT signal for the controller. An OR ing circuit shown in Figure 3 can be used to overcome the problem. FAULT 4.7 kω 47 kω + _ V.3 µf R F = 1 kω C F = 1 nf V CC1 FAULT IC1 V GND1 ACPL-339J V E DESAT V GMOS 16 C BLANK 14 1 V Zener 1N92A Schottky Diode MBR4 1 Ω DDESAT Q1 + V CE 4.7 kω 47 kω + _ V.3 µf R F = 1 kω C F = 1 nf IC2 V CC1 FAULT V GND1 ACPL-339J Figure 34. False fault prevention diodes Figure 3. OR ing the FAULT outputs 2

21 Dead Time and Propagation Delay Specifications The ACPL-339J includes a Propagation Delay Difference (PDD) specification intended to help designers minimize dead time in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q1 and Q2 in Figure 37) are off. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices between the high and low voltage motor rails. To minimize dead time in a given design, the turn on of LED2 should be delayed (relative to the turn off of LED1) so that under worst-case conditions, transistor Q1 has just turned off when transistor Q2 turns on, as shown in Figure 36. The amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay difference specification, PDD MAX, which is specified to be 2 ns over the operating temperature range of -4 C to C. LED1 I F 1 t PHL MIN V OUTP 1 V OUTN 1 t PLH MAX t PLH MAX V G(IGBT) Q1 Q1 IGBT OFF Q1 IGBT ON V G(IGBT) Q2 Q2 IGBT ON Q2 IGBT OFF t PHL MIN t PHL MIN V OUTP 2 V OUTN 2 t PLH MAX LED2 I F 2 PDD = t PLH MAX - t PHL MIN PDD = t PLH MAX - t PHL MIN Figure 36. Minimum LED skew for zero dead time 21

22 Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specifications as shown in Figure 37. The maximum dead time for the ACPL-339J is 4 ns (= 2 ns (-2 ns)) over an operating temperature range of -4 C to C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs. LED1 I F 1 t PHL MIN V OUTP 1 V OUTN 1 V G(IGBT) Q1 V G(IGBT) Q2 t PLH MIN Q1 IGBT OFF Q1 IGBT ON Max. Dead Time Max. Dead Time = PDD MAX PDD MIN = PDD MAX PDD MIN Q2 IGBT ON t PLH MIN Q2 IGBT OFF t PHL MAX t PHL MAX V OUTP 2 V OUTN 2 t PLH MIN LED2 I F 2 Figure 37. Waveforms for dead time 22

23 Thermal Model Definitions Symbol C/W Junction to Ambient Thermal Resistance of LED1 due to heating of LED1 R Junction to Ambient Thermal Resistance of LED1 due to heating of Feedback Detector R Junction to Ambient Thermal Resistance of LED1 due to heating of LED2 R Junction to Ambient Thermal Resistance of LED1 due to heating of Output IC R Junction to Ambient Thermal Resistance of Feedback Detector due to heating of LED1 R Junction to Ambient Thermal Resistance of Feedback Detector due to heating of Feedback Detector R 22 8 Junction to Ambient Thermal Resistance of Feedback Detector due to heating of LED2 R Junction to Ambient Thermal Resistance of Feedback Detector due to heating of Output IC R Junction to Ambient Thermal Resistance of LED2 due to heating of LED1 R Junction to Ambient Thermal Resistance of LED2 due to heating of Feedback Detector R Junction to Ambient Thermal Resistance of LED2 due to heating of LED2 R Junction to Ambient Thermal Resistance of LED2 due to heating of Output IC R Junction to Ambient Thermal Resistance of Output IC due to heating of LED1 R 41 2 Junction to Ambient Thermal Resistance of Output IC due to heating of Feedback Detector R Junction to Ambient Thermal Resistance of Output IC due to heating of LED2 R Junction to Ambient Thermal Resistance of Output IC due to heating of Output IC R P 1 : Power dissipation of LED1 (W) P 2 : Power dissipation of Feedback Detector (W) P 3 : Power dissipation of LED2 (W) P 4 : Power dissipation of Output IC (W) T 1 : Junction temperature of LED1 ( C) T 2 : Junction temperature of Feedback Detector ( C) T 3 : Junction temperature of LED2 ( C) T 4 : Junction temperature of Output IC ( C) T A : Ambient temperature. Ambient temperatures were measured approximately 1.2 cm above optocoupler at ~2 C in still air. This thermal model assumes the device is mounted on a high conductivity test board as per JEDEC 1-7. The junction temperatures at the LED1, Feedback Detector, LED2 and Output IC junctions of the optocoupler can be calculated using the equations below. T 1 = (R 11 * P 1 + R 12 * P 2 + R 13 * P 3 + R 14 * P 4 ) + T A -- (1) T 2 = (R 21 * P 1 + R 22 * P 2 + R 23 * P 3 + R 24 * P 4 ) + T A -- (2) T 3 = (R 31 * P 1 + R 32 * P 2 + R 33 * P 3 + R 34 * P 4 ) + T A -- (3) T 4 = (R 41 * P 1 + R 42 * P 2 + R 43 * P 3 + R 44 * P 4 ) + T A -- (4) All junction temperatures should be within the absolute maximum rating of 12 C. For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright Avago Technologies. All rights reserved. AV2-3784EN - March 13, 213