ACPL-071L and ACPL-074L Single-channel and Dual-channel High Speed 15 MBd CMOS optocoupler with Glitch-Free Power-Up Feature.

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ACPL-071L and ACPL-07L Single-channel and Dual-channel High Speed 1 MBd CMOS optocoupler with Glitch-Free Power-Up Feature Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options

1 ACPL-071L and ACPL-07L Single-channel and Dual-channel High Speed 1 MBd CMOS optocoupler with Glitch-Free Power-Up Feature Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a lead-free product Description The ACPL-071L (single-channel) and ACPL-07L (dualchannel) are 1 MBd CMOS optocouplers in SOIC-8 package. The optocouplers utilize the latest CMOS IC technology to achieve outstanding performance with very low power consumption. Basic building blocks of ACPL-071L and ACPL-07L are high speed LEDs and CMOS detector ICs. Each detector incorporates an integrated photodiode, a high speed transimpedance amplifier, and a voltage comparator with an output driver. Applications Digital field bus isolation: CANBus, RS8, USB Multiplexed data transmission Computer peripheral interface Microprocessor system interface DC/DC converter Functional Diagram Features +.V and + V CMOS compatibility 0 ns max. pulse width distortion 0ns max. propagation delay (for.v supply voltage) 0 ns max. propagation delay skew High speed: 1 MBd min kv/µs minimum common mode rejection 0 to C temperature range Glitch-Free Power-Up Feature Safety and regulatory approvals: - UL recognized: 70 V rms for 1 min. per UL CSA component acceptance Notice # - IEC/EN/DIN EN NC ANODE CATHODE ACPL-071L ACPL-07L 1 8 V DD ANODE1 1 8 V DD 7 NC 7 V o1 CATHODE1 CATHODE V o V o TRUTH TABLE LED, OUTPUT OFF H ON L NC SHIELD GND ANODE SHIELD GND A 0.1uF bypass capacitor must be connected between pins and 8. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

2 Ordering Information ACPL-071L/07L are UL Recognized with 70 Vrms for 1 minute per UL177. Part number ACPL-071L ACPL-07L Option RoHS Compliant -000E Package Surface Mount Tape & Reel X IEC/EN/DIN EN Quantity 0 per tube -00E X X 0 per reel SO-8-00E X X 0 per tube -0E X X X 0 per reel -000E X 0 per tube -00E X X 0 per reel SO-8-00E X X 0 per tube -0E X X X 0 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: ACPL-071L-00E to order product of Small Outline SO-8 package in Tape and Reel packaging in RoHS compliant. Example : ACPL-07L-000E to order product of Small Outline SO-8 package in tube packaging and RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Reflow Soldering Profile Recommended reflow condition as per JEDEC Standard, J-STD-00 (latest revision). Non-Halide Flux should be used. Regulatory Information The ACPL-071L and ACPL-07L have been approved by the following organizations: UL Recognized under UL 177, component recognition program, File E1. CSA Approved under CSA Component Acceptance Notice #, File CA88. IEC/EN/DIN EN 077--

3 Package Dimensions ACPL-071L and ACPL-07L (Small Outline S0-8 Package) LAND PATTERN RECOMMENDATION ± 0.17 (0.1 ± 0.00).99 ± 0.0 (0. ± 0.008) 7.9 (0.9) PIN ONE ± 0.07 (0.01 ± 0.00) 1.70 (0.00) BSC 0. (0.0) 1.9 (0.07) *.080 ± 0.17 (0.00 ± 0.00) 7 X 0. (0.017).17 ± 0.17 (0.1 ± 0.00) 1. (0.00) 0 ~ ± 0.0 (0.009 ± 0.001) * TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH).07 ± 0. (0.0 ± 0.0) DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0. mm (0.00 INCHES) MAX. 0.0 (0.01) MIN. 0.0 ± 0. (0.008 ± 0.00) OPTION NUMBER 00 NOT MARKED. NOTE: FLOATING LEAD PROTRUSION IS 0.1 mm ( mils) MAX. Package Marking ACPL-071L and ACPL-07L (Small Outline S0-8 Package) Device Part Number Lead Free Pin 1 Dot NNNN Z YYWW EEE Test Rating Code Date Code Lot ID

4 Insulation and Safety Related Specifications Parameter Symbol Value Units Conditions Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) L(I01).9 mm Measured from input terminals to output terminals, shortest distance through air. L(I0).8 mm Measured from input terminals to output terminals, shortest distance path along body mm Insulation thickness between emitter and detector; also known as distance through insulation. CTI 17 Volts DIN IEC 11/VDE 00 Part 1 Isolation Group IIIa Material Group (DIN VDE 01, 1/89, Table 1) All Avago Technologies data sheets report the creepage and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. However, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. For creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. There are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. Creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.

5 IEC/EN/DIN EN Insulation Characteristics* Description Symbol Option 00 Unit Installation classification per DIN VDE 01, Table 1 for rated mains voltage Vrms for rated mains voltage 00 Vrms for rated mains voltage 00 Vrms I IV I IV I III Climatic Classification 0/8/1 Pollution Degree (DIN VDE 01/9) Maximum Working Insulation Voltage V IORM 7 Vpeak Input to Output Test Voltage, Method b* V IORM x 1.87 = V PR, 0% Production Test with tm=1 sec, Partial discharge < pc Input to Output Test Voltage, Method a* V IORM x 1. = V PR, Type and Sample Test, tm= sec, Partial discharge < pc V PR Vpeak V PR 907 Vpeak Highest Allowable Overvoltage (Transient Overvoltage tini = 0 sec) V IOTM 000 Vpeak Safety-limiting values maximum values allowed in the event of a failure. Case Temperature Input Current Output Power T S I S, INPUT P S, OUTPUT Insulation Resistance at T S, V IO = 00 V R S 9 Ω 00 C ma mw Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature T S +1 C Ambient Operating Temperature T A 0 + C Supply Voltages V DD 0.0 Volts Output Voltage 0. V DD +0. Volts Average Forward Input Current I F ma Average Output Current I o -.0 ma Input Power Dissipation P I mw Output Power Dissipation P O 0 mw Lead Solder Temperature 0 C for sec., 1. mm below seating plane Solder Reflow Temperature Profile See Reflow Soldering Profile Recommended Operating Conditions Parameter Symbol Min. Max. Units Ambient Operating Temperature T A 0 + C Supply Voltages V DD.. V.0. V Input Current (ON) I F 1 18 ma Supply Voltage Slew Rate [1] S R V/ms

6 Electrical Specifications Over recommended temperature (T A = 0 C to + C),.0V V DD.V and. V V DD. V. All typical specifications are at T A =+ C, V DD = +.V. Parameter Symbol Part Number Min. Typ. Max. Units Test Conditions Input Forward Voltage V F V I F = 1mA Input Reverse Breakdown Voltage BV R.0 V I R = µa Logic High Output Voltage H V DD -1 V DD -0. V I F = 0, I O = - ma, V DD =.V V DD -1 V DD -0. V I F = 0, I O = - ma, V DD =V Logic Low Output Voltage L V I F = 1mA, I O =ma, V DD =.V V I F = 1mA, I O = ma, V DD =V Input Threshold Current I TH. 8.8 ma I OL = 0 µa Logic Low Output Supply Current Logic Low Output Supply Current I DDL ACPL-071L.1.0 ma I F = 1 ma ACPL-07L ma I F = 1 ma I DDH ACPL-071L.8.0 ma I F = 0 ACPL-07L ma I F = 0 Switching Specifications Over recommended temperature (T A = 0 C to + C),.0V V DD.V and. V V DD. V. All typical specifications are at T A =+ C, V DD = +.V. Parameter Symbol Min. Typ. Max. Units Test Conditions Propagation Delay Time to t PHL 9 0 ns I F = 1mA, C L = 1pF, V DD =.V Logic Low Output [] 0 ns I F = 1mA, C L = 1pF, V DD =V Propagation Delay Time to t PLH 0 ns I F = 1mA, C L = 1pF, V DD =.V, Logic High Output [] Pulse Width t PW.7 ns 0 ns I F = 1mA, C L = 1pF, V DD =V, Pulse Width Distortion [] PWD 0 7 ns I F = 1mA, C L = 1pF, V DD =.V, 0 ns I F = 1mA, C L = 1pF, V DD =V, Propagation Delay Skew [] t PSK 0 ns I F = 1mA, C L = 1pF Output Rise Time (% 90%) Output Fall Time (90% - %) t R 0 ns I F = 1mA, C L = 1pF t F ns I F = 1mA, C L = 1pF Common Mode Transient CM H 1 kv/µs V CM = 00 V, T A = C, I F = 0 ma Immunity at Logic High Output [] Common Mode Transient CM L 1 kv/µs V CM = 00 V, T A = C, I F = 1 ma Immunity at Logic Low Output []

7 Package Characteristics All Typical at T A = C. Parameter Symbol Min. Typ. Max. Units Test Conditions Input-Output Insulation I I-O 1.0 µa % RH, t = s V I-O = kv DC, T A = C Input-Output Momentary Withstand Voltage V ISO 70 Vrms RH 0%, t = 1 min., T A = C Input-Output Resistance R I-O 1 W V I-O = 00 V dc Input-Output Capacitance C I-O 0. pf f = 1 MHz, T A = C Notes: 1. Slew rate of supply voltage ramping is recommended to ensure no glitch more than 1V to appear at the output pin.. t PHL propagation delay is measured from the 0% level on the rising edge of the input pulse to the 0% level of the falling edge of the signal. t PLH propagation delay is measured from the 0% level on the falling edge of the input pulse to the 0% level of the rising edge of the signal.. PWD is defined as t PHL - t PLH.. t PSK is equal to the magnitude of the worst case difference in t PHL and/or t PLH that will be seen between units at any given temperature within the recommended operating conditions.. CM H is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.. CM L is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state. I F -FORWARD CURRENT-mA VF IF T A = C V F -FORWARD VOLTAGE-V Figure 1. Typical input diode forward characteristic. I th -INPUT THRESHOLD CURRENT-mA 1 0 I ol =0uA V.V T A -TEMPERATURE- o C Figure. Typical input threshold current vs. temperature. I DDH -LOGIC HIGH OUTPUT SUPPLY CURRENT -ma V DD =.0V V DD =.V T A -TEMPERATURE- o C Figure. Typical logic high O/P supply current vs. temperature for ACPL-07L. IDDl -LOGIC LOW OUTPUT SUPPLY CURRENT-mA V DD =.0V V DD =.V T A -TEMPERATURE- o C Figure. Typical logic low O/P supply current vs. temperature for ACPL-07L. 7

8 tp PROPAGATION DELAY; PWD-PULSE WIDTH DISTORTION ns T PHL CH PWD CH1 V DD =V T A = C T PLH CH T PHL CH1 T PLH CH1 PWD CH I F PULSE INPUT CURRENT ma Figure. Typical switching speed vs. pulse input current at V supply voltage. V F-FORWARD VOLTAGE-V T A -TEMPERATURE- o C Figure 7 Typical V F vs. temperature. tp PROPAGATION DELAY; PWD-PULSE WIDTH DISTORTION ns T PHL CH PWD CH1 V DD =.V T A = C T PLH CH T PHL CH1 T PLH CH1 PWD CH I F PULSE INPUT CURRENT ma Figure. Typical switching speed vs. pulse input current at.v supply voltage. Application Information Bypassing and PC Board Layout The ACPL-071L and ACPL-07L optocouplers are extremely easy to use. ACPL-071L and ACPL-07L provide CMOS logic output due to the high-speed CMOS IC technology used. The external components required for proper operation are the input limiting resistor and the output bypass capacitor. Capacitor values should be between 0.01 µf and 0.1 µf. For each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 0 mm. I F GND1 1 XXX YWW 8 7 NC C V DD I F1 GND 1 GND 1 1 XXX YWW 8 7 C V DD 1 GND I F GND ACPL-071L ACPL-07L C = 0.01mF to 0.1mF Figure 8. Recommended printed circuit board layout 8

9 Propagation Delay, Pulse-Width Distortion and Propagation Delay Skew Propagation delay is a figure of merit which describes how quickly a logic signal propagates through a system. The propagation delay from low to high (t PLH ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low (t PHL ) is the amount of time required for the input signal to propagate to the output, causing the output to change from high to low (see Figure 9). Pulse-width distortion (PWD) results when t PLH and t PHL differ in value. PWD is defined as the difference between t PLH and t PHL and often PWD is defined as the difference between t PLH and t PHL and often determines the maximum data rate capability of a transmission system. PWD can be expressed in percent by dividing the PWD (in ns) by the minimum pulse width (in ns) being transmitted. Typically, PWD on the order of 0-0% of the minimum pulse width is tolerable; the exact figure depends on the particular application (RS, RS, T-1, etc.). Propagation delay skew, t PSK, is an important parameter to consider in parallel data applications where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either t PLH or t PHL, for any given group of optocouplers which are operating under the same conditions (i.e., the same supply voltage, output load, and operating temperature). As illustrated in Figure, if the inputs of a group of optocouplers are switched either ON or OFF at the same time, t PSK is the difference between the shortest propagation delay, either t PLH or t PHL, and the longest propagation delay, either t PLH or t PHL. As mentioned earlier, t PSK can determine the maximum parallel data transmission rate. Figure is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t PSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. I F 0% DATA 0%, CMOS INPUTS CLOCK t PSK I F 0% DATA OUTPUTS t PSK 0%, CMOS CLOCK t PSK Figure 9. Propagation delay and skew waveform Figure. Parallel data transmission example 9

10 The t PSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulsewidth distortion and propagation delay skew over the recommended temperature, and power supply ranges. Powering Sequence V DD needs to achieve a minimum level of.0v before powering up the output connecting component. Input Limiting Resistors ACPL-071L and ACPL-07L are direct current driven (Figure 8), and thus eliminate the need for input power supply. To limit the amount of current flowing through the LED, it is recommended that a ohm resistor is connected in series with anode of LED (i.e. Pin for ACPL-071L and Pin 1 and for ACPL-07L) at V input signal. At.V input signal, it is recommended to connect 80ohm resistor in series with anode of LED. The recommended limiting resistors are based on the assumption that the driver output impedence is 0Ω (as shown in Figure 11). Speed Improvement A peaking capacitor can be placed across the input current limit resistor (Figure 11) to achieve enhanced speed performance. The value of the peaking cap is dependent to the rise and fall time of the input signal and supply voltages and LED input driving current (I f ). Figure 1 shows significant improvement of propagation delay and pulse with distortion with added peak capacitor at driving current of 1mA and.v or V power supply. Vin + - GND 1 R drv =0Ω C peak R limit SHIELD 0.1µF Figure 11 Connection of peaking capacitor (Cpeak) in parallel of the input limiting resistor (Rllimit) to improve speed performance V DD GND tp - PROPAGATION DELAY; PWD-PULSE WIDTH DISTORTION -ns t PHL t PLH PWD t PHL t PLH With peaking cap Without peaking cap T A - TEMPERATURE - o C tp - PROPAGATION DELAY; PWD-PULSE WIDTH DISTORTION -ns t PHL tplh t PHL PWD t PLH With peaking cap Without peaking cap T A - TEMPERATURE - o C (i) V DD =.V, C peak =0pF, R limit =80Ω (ii) V DD =V, C peak =0pF, R limit =Ω Figure 1. Improvement of t p and PWD with added 0pF peaking capacitor in parallel of input limiting resistor.

11 A V CM B I F R limit SHIELD 0.1µF V DD monitoring note GND V CM 0 V V DD GND SWITCH AT A: I = 0 ma F SWITCH AT B: I = 1 ma F V CM (PEAK) (min.) (max.) CM H CM L Pulse Gen. Zo=0Ω + - Figure 1. Test circuit for common mode transient immunity and typical waveforms. R total is the total resistance of the driver output impedence (which is assumed to be 0 Ω) and the limiting resistor (R total =R drv +R limit ). For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright Avago Technologies. All rights reserved. AV0-09EN - June, 01

ACPL-071L and ACPL-074L Single-channel and Dual-channel High Speed 15 MBd CMOS optocoupler with Glitch-Free Power-Up Feature. Features.

ACPL-071L and ACPL-074L Single-channel and Dual-channel High Speed 15 MBd CMOS optocoupler with Glitch-Free Power-Up Feature. Features. ACPL-7L and ACPL-7L Single-channel and Dual-channel High Speed MBd CMOS optocoupler with Glitch-Free Power-Up Feature Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available;