TRUTH TABLE (POSITIVE LOGIC) Z Z H L H H L L
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1 HCPL-, HCPL-9 Low Input Current Logic Gate Optocouplers Data Sheet Description The HCPL-/9 are optically coupled logic gates that combine a GaAsP LED and an integrated high gain photo detector. The detector has a three state output stage and has a detector threshold with hysteresis. The three state output eliminates the need for a pullup resistor and allows for direct drive of data busses. The hysteresis provides differential mode noise immunity and eliminates the potential for output signal chatter. A superior internal shield on the HCPL-9 guarantees common mode transient immunity of. kv/µs at a common mode voltage of volts. The Electrical and Switching Characteristics of the HCPL-/9 are guaranteed over the temperature range of C to C and a range of. volts to volts. Low I F and wide range allow compatibility with TTL, LSTTL, and CMOS logic and result in lower power consumption compared to other high speed optocouplers. Logic signals are transmitted with a typical propagation delay of nsec. The HCPL-/9 are useful for isolating high speed logic interfaces, buffering of input and output lines, and implementing isolated line receivers in high noise environments. Functional Diagram Features. kv/µs minimum Common Mode Rejection (CMR) at V CM = V (HCPL-9) Compatible with LSTTL, TTL, and CMOS logic Wide range (. to V). Mbd guaranteed over temperature Low input current (. ma) Three state output (no pullup resistor required) Guaranteed performance from C to C Hysteresis Safety approval UL recognized - V rms for minute CSA approved IEC/EN/DIN EN -- approved with V IORM = V peak (HCPL-9 Option only) MIL-PRF- hermetic version available (HCPL-/) Applications Isolation of high speed logic systems Computer-peripheral interfaces Microprocessor system interfaces Ground loop elimination Pulse transformer replacement Isolated buss driver High speed line receiver NC ANODE CATHODE NC SHIELD V E TRUTH TABLE (POSITIVE LOGIC) LED ENABLE ON OFF ON OFF H H L L Z Z H L A. µf bypass capacitor must be connected between pins and. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
2 Selection Guide Small-Outline Widebody Minimum CMR -Pin DIP ( Mil) SO- ( Mil) Hermetic Input On- Single Dual Single Single Single and Dual dv/dt V CM Current Channel Channel Channel Channel Channel (V/µs) (V) (ma) Package Package Package Package Packages,. HCPL- [] HCPL- HCNW HCPL- HCPL-. HCPL-,. HCPL-9 [], [] []. HCPL- HCPL- HCNW HCPL-. HCPL-,. HCPL-XX HCPL-XX Notes:. HCPL-/9 devices include output enable/disable functionality.. Minimum CMR of kv/µs with V CM = V can be achieved with input current, I F, of ma.
3 Ordering Information HCPL-, HCPL-9 are UL Recognized with Vrms for minute per UL and are approved under CSA Component Acceptance Notice #, File CA. Option Part RoHS non RoHS Surface Gull Tape UL Vrms/ IEC/EN/DIN Number Compliant Compliant Package Mount Wing & Reel Minute rating EN -- Quantity -E no option mil DIP- per tube HCPL- -E - X X per tube -E - X X X per reel -E no option mil DIP- per tube -E - X X per tube HCPL-9 -E - X X X per reel -E - X per tube -E - X X X per tube -E - X X X X per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : HCPL-9-E to order product of mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN -- Safety Approval and RoHS compliant. Example : HCPL- to order product of mil DIP package in Tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation #XXX is used for existing products, while (new) products launched since July, and RoHS compliant will use XXXE. Schematic I CC I F + V F SHIELD I O I E V E
4 UR Package Outline Drawings -Pin DIP Package 9. ±. (. ±.). ±. (. ±.) TYPE NUMBER A XXXXZ OPTION CODE* DATE CODE. ±. (. ±.) YYWW UL RECOGNITION.9 (.) MAX.. ±. (. ±.). (.) MAX.. (.) MAX. TYP (. +.) -.). ±. (. ±.). (.) MIN..9 (.) MIN. DIMENSIONS IN MILLIMETERS AND (INCHES). *MARKING CODE LETTER FOR OPTION NUMBERS. "V" = OPTION OPTION NUMBERS AND NOT MARKED.. (.) MAX. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.. ±. (. ±.) -Pin DIP Package with Gull Wing Surface Mount Option LAND PATTERN RECOMMENDATION 9. ±. (. ±.). (.). ±. (. ±.).9 (.). (.). (.).9 (.) MAX.. (.) MAX.. ±. (. ±.) 9. ±. (. ±.). ±. (. ±.) (. +.) -.). ±. (. ±.).. ±. (.) (. ±.) BSC DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY =. mm (. INCHES).. ±. (. ±.) NOM. NOTE: FLOATING LEAD PROTRUSION IS. mm ( mils) MAX.
5 Solder Reflow Thermal Profile TEMPERATURE ( C) ROOM TEMPERATURE PREHEATING RATE C + C/. C/SEC. REFLOW HEATING RATE. C ±. C/SEC. C C C C + C/. C Recommended Pb-Free IR Profile TEMPERATURE. C ±. C/SEC. PREHEATING TIME C, 9 + SEC. T p +/- C T L C RAMP-UP C/SEC. MAX. T smax - C T smin PEAK TEMP. C SEC. SEC. SEC. PEAK TEMP. C SOLDERING TIME C PEAK TEMP. C TIGHT TYPICAL LOOSE TIME (SECONDS) Note: Non-halide flux should be used. t s PREHEAT to SEC. t p t L TIME WITHIN C of ACTUAL PEAK TEMPERATURE - SEC. RAMP-DOWN C/SEC. MAX. to SEC. Regulatory Information The HCPL-/9 have been approved by the following organizations: UL Recognized under UL, Component Recognition Program, File E. CSA Approved under CSA Component Acceptance Notice #, File CA. IEC/EN/DIN EN -- Approved under: IEC --:99 + A: EN --: + A: DIN EN -- (VDE Teil ):-. (Option only) t C to PEAK TIME NOTES: THE TIME FROM C to PEAK TEMPERATURE = MINUTES MAX. T smax = C, T smin = C Note: Non-halide flux should be used. Insulation and Safety Related Specifications Parameter Symbol Value Units Conditions Min. External Air Gap L(IO). mm Measured from input terminals to output terminals, (External Clearance) shortest distance through air. Min. External L(IO). mm Measured from input terminals to output terminals, Tracking Path shortest distance path along body. (External Creepage) Minimum Internal. mm Through insulation distance, conductor to conductor, Plastic Gap usually the direct distance between the photoemitter (Internal Clearance) and photodetector inside the optocoupler cavity. Tracking Resistance CTI V DIN IEC /VDE Part (Comparative Tracking Index) Isolation Group IIIa Material Group (DIN VDE, /9, Table ) Option surface mount classification is Class A in accordance with CECC.
6 IEC/EN/DIN EN -- Insulation Related Characteristics (HCPL-9 OPTION ONLY) Description Symbol Characteristic Units Installation classification per DIN VDE /.9, Table for rated mains voltage V rms for rated mains voltage V rms Climatic Classification // Pollution Degree (DIN VDE /.9) Maximum Working Insulation Voltage V IORM V peak Input to Output Test Voltage, Method b* V IORM x. = V PR, % Production Test with t m = sec, V PR V peak Partial Discharge < pc Input to Output Test Voltage, Method a* V IORM x. = V PR, Type and sample test, V PR 9 V peak t m = sec, Partial Discharge < pc Highest Allowable Overvoltage* (Transient Overvoltage, t ini = sec) V IOTM V peak Safety Limiting Values (Maximum values allowed in the event of a failure, also see Figure, Thermal Derating curve.) Case Temperature T S C Input Current I S,INPUT ma Output Power P S, mw Insulation Resistance at T S, V IO = V R S 9 Ω *Refer to the front of the optocoupler section of the current catalog, under Product Safety Regulations section, IEC/EN/DIN EN --, for a detailed description. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. I-IV I-III
7 Absolute Maximum Ratings (No Derating Required up to C) Parameter Symbol Min. Max. Units Note Storage Temperature T S - C Operating Temperature T A - C Average Forward Input Current I F(AVG) ma Peak Transient Input Current I F(TRAN). A ( µs Pulse Width, pps) Reverse Input Voltage V R V Average Output Current I O ma Supply Voltage V Three State Enable Voltage V E -. V Output Voltage -. V Total Package Power Dissipation P T mw Lead Solder Temperature C for sec.,. mm below seating plane Solder Reflow Temperature Profile See Package Outline Drawings section Recommended Operating Conditions Parameter Symbol Min. Max. Units Power Supply Voltage. V Enable Voltage High V EH. V Enable Voltage Low V EL. V Forward Input Current I F(ON).* ma Forward Input Current I F(OFF). ma Operating Temperature T A [] C Fan Out N TTL Loads *The initial switching threshold is. ma or less. It is recommended that. ma be used to permit at least a % CTR degradation guardband.
8 Electrical Specifications For C T A [] C,. V V,. ma I F(ON) ma,. V V EH V,. V V EL. V, ma I F(OFF). ma. All Typicals at T A = C, = V, I F(ON) = ma unless otherwise specified. See Note. Parameter Sym. Min. Typ. Max. Units Test Conditions Fig. Note Logic Low L. V I OL =. ma ( TTL Loads) Output Voltage Logic High H. * V I OH = -. ma *H = -. V Output Voltage Output Leakage I OHH µa =. V I F = ma Current (UT > ) µa = V =. V Logic High Enable V EH. V Voltage Logic Low Enable V EL. V Voltage Logic High Enable I EH µa V EN =. V Current µa V EN =. V. µa V EN = V Logic Low Enable I EL -. ma V EN =. V Current Logic Low Supply I CCL.. ma =. V I F = ma Current I O = Open.. ma = V V E = Don t Care Logic High Supply I CCH.. ma =. V I F = ma Current I O = Open.. ma = V V E = Don t Care High Impedance State Output Current I OZL - µa =. V V EN = V, I F = ma I OZH µa =. V V EN = V, µa =. V I F = ma µa = V Logic Low Short I OSL ma V O = =. V I F = ma Circuit Output Current ma = = V Logic High Short I OSH - ma =. V I F = ma, Circuit Output = Current - ma = V Input Current I HYS. ma = V Hysteresis Input Forward V F.. V T A = C I F = ma Voltage. Input Reverse BV R V I R = µa Breakdown Voltage Input Diode V F -. mv/ C I F = ma Temperature T A Coefficient Input Capacitance C IN pf f = MHz, V F = V, Pins and
9 Switching Specifications (AC) For C T A [] C,. V V,. ma I F(ON) ma,. ma I F(OFF). ma. All Typicals at T A = C, = V, I F(ON) = ma unless otherwise specified. Parameter Sym. Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time to t PHL ns Without Peaking Capacitor,, Logic Low Output Level With Peaking Capacitor Propagation Delay Time to t PLH ns Without Peaking Capacitor,, Logic High Output Level With Peaking Capacitor Output Enable Time to t PZH ns, 9 Logic High Output Enable Time to t PZL ns, Logic Low Output Disable Time from t PHZ ns, 9 Logic High Output Disable Time from t PLZ ns, Logic Low Output Rise Time (-9%) t r ns, Output Fall Time (9-%) t f ns, Parameter Sym. Device Min. Units Test Conditions Fig. Note Logic High CM H I F =. ma HCPL-, V/µs V Common Mode CM = V = V Transient T A = C Immunity HCPL-9, V/µs V CM = V Logic Low CM L V F = V Common Mode HCPL-, V/µs V CM = V = V Transient T A = C Immunity HCPL-9, V/µs V CM = V Package Characteristics Parameter Sym. Min. Typ. Max. Units Test Conditions Fig. Note Input-Output Momentary V ISO V rms RH %, t = min.,, Withstand Voltage* T A = C Input-Output Resistance R I-O Ω V I-O = VDC Input-Output Capacitance C I-O. pf f = MHz, V I-O = VDC *The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to the IEC/EN/DIN EN -- Insulation Characteristics Table (if applicable), your equipment level safety specification or Avago Application Note entitled Optocoupler Input-Output Endurance Voltage, publication number 9-E. 9
10 Notes:. Derate total package power dissipation, P T, linearly above C free air temperature at a rate of. mw/ C.. Duration of output short circuit time should not exceed ms.. Device considered a two-terminal device: pins,,, and shorted together and pins,,, and shorted together.. The t PLH propagation delay is measured from the % point on the leading edge of the input pulse to the. V point on the leading edge of the output pulse. The t PHL propagation delay is measured from the % point on the trailing edge of the input pulse to the. V point on the trailing edge of the output pulse.. When the peaking capacitor is omitted, propagation delay times may increase by ns.. CM L is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state ( <. V). CM H is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic high state ( >. V).. Use of a. µf bypass capacitor connected between pins and is recommended.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage V rms for one second (leakage detection current limit, I I-O µa). This test is performed before the % production test for partial discharge (Method b) shown in the IEC/EN/DIN EN -- Insulation Characteristics Table, if applicable. L LOW LEVEL VOLTAGE V =. V I F = ma =. ma - - T A TEMPERATURE C I OH HIGH LEVEL CURRENT ma =. V =. V =. V I F = ma - - T A TEMPERATURE C VOLTAGE V I OL =. ma. =. V T A = C. I OH = -. ma. I F INPUT CURRENT ma. Figure. Typical logic low output voltage vs. temperature. Figure. Typical logic high output current vs. temperature. Figure. Output voltage vs. forward input current. I F FORWARD CURRENT ma..... I F + V F... V F FORWARD VOLTAGE V Figure. Typical input diode forward characteristic. T A = C. PULSE GEN. t r = t f = ns f = khz % DUTY CYCLE = V I F INPUT MONITORING NODE R INPUT I F Figure. Test circuit for t PLH, t PHL, t r, and t f. HCPL- C = pf MONITORING NODE C = pf THE PROBE AND JIG CAPACITANCES ARE INCLUDED IN C AND C. R I. kω. kω I F (ON). ma ma Ω ma ALL DIODES ARE N9 OR N. I F (ON) % I F (ON) ma PLH PHL H V. VOL D kω V 9 Ω D D D
11 t P PROPAGATION DELAY ns t PHL - = V C ( pf) PEAKING CAPACITOR IS USED. SEE FIGURE. t PLH T A TEMPERATURE C I F (ma). - - Figure. Typical propagation delays vs. temperature.. I F INPUT V C MONITORING NODE PULSE GENERATOR Z O = Ω t r = t f = ns C L = pf INCLUDING PROBE AND JIG CAPACITANCES. HCPL- D - ARE N9 OR N. C L + V S D 9 Ω D kω D D S INPUT V E. V t PZL t PLZ V S AND. V S CLOSED S CLOSED. V. V S OPEN L t. V PZH. V H. V V S OPEN S CLOSED t PHZ S AND S CLOSED Figure. Test circuit for t PHZ, t PZH, t PLZ, and t PZL. T p ENABLE PROPAGATION DELAY ns - C L = pf t PLZ t PZL V. V V. V - - t P ENABLE PROPAGATION DELAY ns - C L = pf V t PHZ. V V. V t PZH - - t r, t f RISE, FALL TIME ns - = V C = pf - - t r t f T A TEMPERATURE C T A TEMPERATURE C T A TEMPERATURE C Figure. Typical logic low enable propagation delay vs. temperature. Figure 9. Typical logic high enable propagation delay vs. temperature. Figure. Typical rise, fall time vs. temperature.
12 B R IN V FF A V CM V H L PULSE GENERATOR * SEE NOTE. HCPL- + V V CM SWITCH AT A: I F =. ma (MIN.)* SWITCH AT B: I F = ma (MAX.)*. µf BYPASS MONITORING NODE POWER P S, INPUT CURRENT I S HCPL-9 OPTION ONLY P S (mw) I S (ma) T S CASE TEMPERATURE C Figure. Thermal derating curve, dependence of safety limiting value with case temperature per IEC/EN/DIN EN --. Figure. Test circuit for common mode transient immunity and typical waveforms. (+ V) DATA INPUT TOTEM POLE GATE. kω TTL OR LSTTL pf HCPL- (+ V) DATA UP TO LSTTL LOADS OR TTL LOADS (+ V) DATA INPUT TOTEM POLE GATE. kω TTL OR LSTTL pf (OPTIONAL*) V V V V HCPL- R L. K. K. K. K (. TO V) R L CMOS DATA Figure. Recommended LSTTL to LSTTL circuit. Figure. LSTTL to CMOS interface circuit. (+ V). kω HCPL- (+ V). kω pf (OPTIONAL*) HCPL- DATA INPUT TTL OR LSTTL D DATA INPUT OPEN COLLECTOR GATE. kω TTL OR LSTTL D (N) REQUIRED FOR ACTIVE PULL-UP DRIVER. Figure. Recommended LED drive circuit. Figure. Series LED drive with open collector gate (. kω resistor dhunts I OH from the LED). *The pf capacitor may be omitted in applications where ns propagation delay is sufficient.
13 For product information and a complete list of distributors, please go to our website: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright Avago Technologies Limited. All rights reserved. Obsoletes 99-EN AV-EN July,
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