Features V CC2 V OUT DESAT 9, 12 V EE. Applications V CLAMP V LED

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1 ACPL-J. Amp Output Current IGBT Gate Driver Optocoupler with Integrated (V CE ) Desaturation Detection, UVLO Fault Status Feedback, Active Miller Clamp and Auto-Fault Reset Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a lead-free product Description The ACPL-J is an advanced. A output current, easyto-use, intelligent gate drivers which make IGBT V CE fault protection compact, affordable, and easy-to implement. Features such as integrated V CE detection, under voltage lockout (UVLO), soft IGBT turn-off, isolated open collector fault feedback, active Miller clamping and Autofault reset provide maximum design flexibility and circuit protection. The ACPL-J contains a AlGaAs LED. The LED is optically coupled to an integrated circuit with a power output stage. ACPL-J are ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The voltage and current supplied by these optocouplers make them ideally suited for directly driving IGBTs with ratings up to 0 V and A. For IGBTs with higher ratings, the ACPL-J can be used to drive a discrete power stage which drives the IGBT gate. The ACPL-J have an insulation voltage of V IORM = V PEAK. Block Diagram,,, LED SHIELD SHIELD LED D R I V E R UVLO, V CC Features. A maximum peak output current.0 A minimum peak output current 0 ns maximum propagation delay over temperature range.a Active Miller Clamp.Clamp pin short to if not used Desaturation Detection Under Voltage Lock-Out Protection (UVLO) with Hysteresis Open Collector Isolated fault feedback Soft IGBT Turn-off Automatic Fault Reset after fixed mute time, typical μs Available in SO- package 0 ns maximum pulse width distortion (PWD) 0 kv/μs minimum common mode rejection (CMR) at V CM = 0 V I CC(max) < ma maximum supply current Wide V CC operating range: V to 0 V over temperature range Wide operating temperature range: 0 C to C Safety approvals: UL approval, 000 V RMS for minute, CSA approval, IEC/EN/DIN-EN 0-- approval V IORM = V PEAK Applications Isolated IGBT/Power MOSFET gate drive AC and brushless DC motor drives Industrial inverters and Uninterruptible Power Supply (UPS) CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

2 Pin Description Pin Symbol Description Input Ground Positive input supply voltage. (. V to. V) V CC Fault output. changes from a high impedance state to a logic low output within μs of the voltage on the pin exceeding an internal reference voltage of. V. output is an open collector which allows the outputs from all ACPL-J in a circuit to be connected together in a wired OR forming a single fault bus for interfacing directly to the micro-controller. Input Ground Cathode Anode Anode Cathode Output supply voltage. Miller clamp Gate drive voltage output Output supply voltage. V CC Positive output supply voltage Desaturation voltage input. When the voltage on exceeds an internal reference voltage of. V while the IGBT is on, output is changed from a high impedance state to a logic low state within μs. LED anode. This pin must be left unconnected for guaranteed data sheet performance. (For optical coupling testing only) Common (IGBT emitter) output supply voltage. Ordering Information ACPL-J is UL Recognized with 000 Vrms for minute per UL. Part number Option RoHS Compliant Package Surface Mount Tape& Reel IEC/EN/DIN EN 0-- Quantity ACPL-J -000E SO- X X per tube -00E X X X 0 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : ACPL-J-00E to order product of SO- Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 0-- Safety Approval in RoHS compliant. Example : ACPL-J-000E to order product of SO- Surface Mount package in tube packaging with IEC/EN/DIN EN 0-- Safety Approval and RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation #XXX is used for existing products, while (new) products launched since th July 00 and RoHS compliant option will use -XXXE.

3 Package Outline Drawings ACPL-J -Lead Surface Mount Package 0.0 (0.) 0.00 (.0) LAND PATTERN RECOMMENDATION A J YYWW 0. ± 0.0 (. ± 0.) TYPE NUMBER DATE CODE 0. (.) 0.0 (.) 0.0 ± 0. (. ± 0.) 0.0 (0.) 0. ± 0.0 (. ± 0.) ALL LEADS TO BE COPLANAR ± (0.) 0. ± 0.00 (.0 ± 0.) MIN. 0.0 ± 0.0 (. ± 0.) 0.00 ± 0.00 (0.0 ± 0.0) STANDOFF Dimensions in inches (millimeters) Notes: Initial and continued variation in the color of the ACPL-J s white mold compound is normal and does note affect device performance or reliability. Floating Lead Protrusion is 0. mm ( mils) max. Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-00 (latest revision). Non-Halide Flux should be used.

4 Regulatory Information The ACPL-J is approved by the following organizations: IEC/EN/DIN EN 0-- Approval under: IEC 0-- : + A:00 EN 0--:00 + A:00 DIN EN 0-- (VDE 0 Teil ):00-0 UL Approval under UL, component recognition program up to V ISO = 000 V RMS. File E. CSA Approval under CSA Component Acceptance Notice #, File CA. Table. IEC/EN/DIN EN 0-- Insulation Characteristics* Description Symbol Characteristic Unit Installation classification per DIN VDE 00/., Table for rated mains voltage V rms for rated mains voltage 00 V rms for rated mains voltage 00 V rms for rated mains voltage 00V rms Climatic Classification /0/ Pollution Degree (DIN VDE 00/.) Maximum Working Insulation Voltage V IORM V peak Input to Output Test Voltage, Method b**, V IORM x.=v PR, 0% Production Test with t m = sec, Partial discharge < pc V PR 0 V peak Input to Output Test Voltage, Method a**, V IORM x.=v PR, Type and Sample Test, t m = sec, Partial discharge < pc I IV I IV I IV I III V PR V peak Highest Allowable Overvoltage (Transient Overvoltage t ini = 0 sec) V IOTM 000 V peak Safety-limiting values maximum values allowed in the event of a failure. Case Temperature T S C Input Current I S, INPUT 00 ma Output Power P S, OUTPUT 0 mw Insulation Resistance at T S, V IO = 00 V R S > Ω * Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. Surface mount classification is class A in accordance with CECCOO0. ** Refer to the optocoupler section of the Isolation and Control Components Designer s Catalog, under Product Safety Regulations section IEC/EN/ DIN EN 0--, for a detailed description of Method a and Method b partial discharge test profiles. Dependence of Safety Limiting Values on Temperature. (take from DS AV0-0EN Pg.)

5 Table. Insulation and Safety Related Specifications Parameter Symbol ACPL-J Units Conditions Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) L(). mm Measured from input terminals to output terminals, shortest distance through air. L(). mm Measured from input terminals to output terminals, shortest distance path along body. 0. mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. CTI > V DIN IEC /VDE 00 Part Isolation Group IIIa Material Group (DIN VDE 00, /, Table ) Table. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature T S - C Operating Temperature T A -0 C Output IC Junction Temperature T J C Average Input Current I F(AVG) ma Peak Transient Input Current, I F(TRAN).0 A (< μs pulse width, 00pps) Reverse Input Voltage V R V High Peak Output Current I OH(PEAK). A Low Peak Output Current I OL(PEAK). A Positive Input Supply Voltage V Output Current I.0 ma Pin Voltage V -0. V Total Output Supply Voltage (V CC - ) -0. V Negative Output Supply Voltage ( - ) -0. V Positive Output Supply Voltage (V CC - ) ( - ) V Gate Drive Output Voltage V O(PEAK) -0. V CC V Peak Clamping Sinking Current I Clamp. A Miller Clamping Pin Voltage V Clamp -0. V CC V Voltage V + V Output IC Power Dissipation P O 00 mw Input IC Power Dissipation P I mw Solder Reflow Temperature Profile See Package Outline Drawings section Table. Recommended Operating Conditions Parameter Symbol Min. Max. Units Note Operating Temperature T A - 0 C Total Output Supply Voltage (V CC - ) 0 V Negative Output Supply Voltage ( - ) 0 V Positive Output Supply Voltage (V CC - ) 0 - ( - ) V Input Current (ON) I F(ON) ma Input Voltage (OFF) V F(OFF) V

6 Table. Electrical Specifications (DC) Unless otherwise noted, all typical values at T A = C, V CC - = 0 V, - = 0 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. Positive Supply Voltage used. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Logic Low Output Voltage V L V I =. ma, =.V V I =. ma, =.V Logic High I H μa V =. V, =.V Output Current μa V =. V, =.V High Level Output Current I OH A V O = V CC -,, -.0 A V O = V CC Low Level Output Current I OL 0.. A V O = +.,,.0 A V O = + Low Level Output Current I OLF ma - = V During Fault Condition High Level Output Voltage V OH V CC -. V CC -.0 V I O = -0 μa,,, Low Level Output Voltage V OL V I O = 0 ma, Clamp Pin Threshold Voltage V tclamp.0 V Clamp Low Level Sinking Current I CL 0.. A V O = +. High Level Supply Current I CCH. ma I O = 0 ma,, Low Level Supply Current I CCL. ma I O = 0 ma, Blanking Capacitor I CHG ma V = V,, Charging Current Blanking Capacitor I DSCHG 0 ma V =.0 V Discharge Current Threshold V.. V V CC - >V UVLO- UVLO Threshold V UVLO+... V V O > V,, V UVLO-... V V O < V,, UVLO Hysteresis (V UVLO+ 0.. V - V UVLO- ) Threshold Input Current I FLH.0 ma I O = 0 ma, V O > V Low to High Threshold Input Voltage V FHL 0. V High to Low Input Forward Voltage V F... V I F = ma Temperature Coefficient ΔV F /ΔT A -. mv/ C of Input Forward Voltage Input Reverse Breakdown BV R V I R = μa Voltage Input Capacitance C IN 0 pf f = MHz, V F = 0 V

7 Table. Switching Specifications (AC) Unless otherwise noted, all typical values at T A = C, V CC - = 0 V, - = 0 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. Only Positive Supply Voltage used. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Propagation Delay Time to High Output Level Propagation Delay Time to Low Output Level t PLH ns R g = Ω, C g = nf, f = khz,,,,,, t Duty Cycle = 0%, PHL ns,, I F = ma,,, V CC = 0 V, Pulse Width Distortion PWD ns, Propagation Delay Difference Between Any Two Parts or Channels (t PHL - t PLH ) PDD Rise Time t R 0 ns Fall Time t F 0 ns Sense to 0% VO Delay Sense to % VO Delay Sense to Low Level Signal Delay Sense to Low Propagation Delay, -0 0 ns, t (0%) μs C = 0pF, R g = Ω, C g = nf, V CC = 0 V t (%) μs C = 0pF, R g = Ω, C g = nf, V CC = 0 V t () μs C = 0 pf, R F =. kω, C F = Open, Rg = Ω, Cg = nf, V CC = 0 V 0. C = 0 pf, R F =. kω, C F = nf, Rg = Ω, Cg = nf, V CC = 0 V t (LOW) 0. μs C = 0pF, R F =. kω, R g = Ω, C g = nf, V CC = 0 V, 0,, 0, Input Mute t (MUTE) 0 μs C = 0pF, R F =. kω, R g = Ω, C g = nf, =.V, V CC = 0 V Output High Level Common Mode Transient Immunity Output Low Level Common Mode Transient Immunity CM H kv/μs T A = C, I F = ma V CM = 0 V, V CC = 0 V, R F =. kω, C F = pf 0 0 T A = C, I F = ma V CM = 0 V, V CC = 0 V, R F =. kω, C F = nf CM L kv/μs T A = C, V F = 0 V V CM = 0 V, V CC = 0 V, R F =. kω, C F = pf 0 0 T A = C, V F = 0 V V CM = 0 V, V CC = 0 V, R F =. kω, C F = nf,,,,,, 0,

8 Table. Package Characteristics Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Input-Output Momentary Withstand Voltage V ISO 000 V rms RH < 0%, t = min., T A = C, Input-Output Resistance R I-O > Ω V I-O = 00 V Input-Output Capacitance C I-O. pf freq= MHz Output IC-to-Pins & Thermal Resistance θ 0-0 C/W T A = C Notes:. Derate linearly above 0 C free air temperature at a rate of 0. ma/ C.. In order to achieve the absolute maximum power dissipation specified, pins,, and require ground plane connections and may require airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB Layout section in the application notes for layout considerations. Output IC power dissipation is derated linearly at mw/ C above 0 C. Input IC power dissipation does not require derating.. Maximum pulse width = μs. This value is intended to allow for component tolerances for designs with I O peak minimum =.0 A. Derate linearly from.0 A at + C to. A at + C. This compensates for increased I OPEAK due to changes in V OL over temperature.. This supply is optional. Required only when negative gate drive is implemented.. Maximum pulse width = 0 μs.. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details.. V is the recommended minimum operating positive supply voltage (V CC - ) to ensure adequate margin in excess of the maximum V UVLO+ threshold of.v. For High Level Output Voltage testing, V OH is measured with a dc load current. When driving capacitive loads, V OH will approach V CC as I OH approaches zero units.. Maximum pulse width =.0 ms.. Once V O of the ACPL-J is allowed to go high (V CC - > V UVLO+ ), the detection feature of the ACPL-J will be the primary source of IGBT protection. UVLO is needed to ensure is functional. Once V CC is increased from 0V to above V UVLO+, will remain functional until V CC is decreased below V UVLO-. Thus, the detection and UVLO features of the ACPL-J work in conjunction to ensure constant IGBT protection.. See the fault detection blanking time section in the applications notes at the end of this data sheet for further details.. This is the increasing (i.e. turn-on or positive going direction) of V CC -. This is the decreasing (i.e. turn-off or negative going direction) of V CC -. This load condition approximates the gate load of a 0 V/A IGBT.. Pulse Width Distortion (PWD) is defined as t PHL - t PLH for any given unit.. As measured from I F to V O.. The difference between t PHL and t PLH between any two ACPL-J parts under the same test conditions.. As measured from, of LED to. This is the amount of time from when the threshold is exceeded, until the output goes low.. This is the amount of time the threshold must be exceeded before begins to go low, and the output to go low. This is supply voltage dependent. 0. Fault Reset: This is the amount of time when will be asserted low after threshold is exceeded. See the Description of Operation (Fault Reset) topic in the application information section.. Common mode transient immunity in the high state is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in the high state (i.e., V O > V or > V).. Common mode transient immunity in the low state is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in a low state (i.e., V O <.0 V or < 0. V).. To clamp the output voltage at V CC - V BE, a pull-down resistor between the output and is recommended to sink a static current of 0 μa while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pull-down resistor is not used.. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage 000 Vrms for second. This test is performed before the 0% production test for partial discharge (method b) shown in IEC/EN/DIN EN 0-- Insulation Characteristic Table.\. This is a two-terminal measurement: pins - are shorted together and pins - are shorted together.. Split resistors network with a ratio of : is needed at input LED. See Figure.

9 I F t r t f 0% 0% % t PLH t PHL Figure. VOUT propagation delay waveforms.0 IOH - OUTPUT HIGH CURRENT - A T A - TEMPERATURE - C o IOL - OUTPUT LOW CURRENT = +V = +.V T A - TEMPERATURE - o C Figure. I OH vs. temperature Figure. I OL vs. temperature (VOH - VCC) - HIGH OUTPUT VOLTAGE DROP - V 0 I OUT = -0uA T A - TEMPERATURE - o C VOL - OUTPUT LOW VOLTAGE - V T A - TEMPERATURE - o C Figure. V OH vs. temperature Figure. V OL vs. temperature

10 V OH - HIGH OUTPUT VOLTAGE DROP - V 0 o C o C o C I OH - OUTPUT HIGH CURRENT - A Figure. V OH vs. I OH VOL - LOW OUTPUT VOLTAGE DROP - V 0 o C o C o C I ol - OUTPUT LOW CURRENT - A Figure. V OL vs. I OL.0 ICL - CLAMP LOW LEVEN SINKING CURRENT ICC - OUTPUT SUPPLY CURRENT - ma I CC H I CC L T A - TEMPERATURE - o C T A - TEMPERATURE - o C Figure. I CL vs. temperature Figure. I CC vs. temperature I Cc H ICC - OUTPUT SUPPLY CURRENT - ma... I CC L ICH - BLANKING CAPACITOR CHARGING CURRENT - ma V CC - OUTPUR SUPPLY VOLTAGE - V Figure. I CC vs. V CC T A - TEMPERATURE - o C Figure. I CHG vs. temperature

11 t PLH t PHL V - THRESHOLD - V.0. TP - PROPAGATION DELAY - ns T A - TEMPERATURE - o C Figure. threshold vs. temperature T A - TEMPERATURE - o C Figure. Propagation delay vs. temperature TP - PROPAGATION DELAY - ns t PLH t PHL TP - PROPAGATION DELAY - ms t PLH t PHL Vcc - SUPPLY VOLTAGE - V Figure. Propagation delay vs. supply voltage LOAD RESISTANCE - ohm Figure. Propagation delay vs. load resistance 00 TP - PROPAGATION DELAY - ms t PLH t PHL LOAD CAPACITANCE - nf Figure. Propagation delay vs. load capacitance

12 T 0% - Sense to 0% Vo Delay - ns T - Sense to % Vo Delay - us V cc =V V cc =0V T A - TEMPERATURE - o C T A - TEMPERATURE - o C Figure. sense to 0% VOUT delay vs. temperature Figure. sense to % VOUT delay vs. temperature T % - Sense to % Vo Delay - us V cc =V V cc =0V LOAD RESISTANCE - ohm T % - Sense to % Vo Delay - ms V cc =V V cc =0V LOAD CAPACITANCE - nf Figure. sense to % VOUT delay vs. load resistance Figure 0. sense to % VOUT delay vs. load capacitance

13 V CC V Pulsed ma I OUT 0V Figure. I OH Pulsed test circuit V CC V Pulsed I OUT 0V Figure. I OL Pulsed test circuit V CC ma 0μA 0V Figure. V OH Pulsed test circuit

14 V CC 0mA 0V Figure. V OL Pulsed test circuit V CC I CC ma 0V Figure. I CCH test circuit V CC I CC 0V Figure. I CCL test circuit

15 I CHG V CC ma 0V Figure. I CHG Pulsed test circuit V V CC IDSCHG 0V Figure. I DSCHG test circuit V CC Ω nf 0V ma, khz, 0% Duty Cycle Figure. t PLH, t PHL, t f, t r, test circuit

16 R F =.kω V IN V C F V V CC ma Ω nf 0V Figure 0. t fault test circuit V R F =.kω C F =pf or nf SCOPE V CC Ω 0V 0Ω nf Figure. CMR Test circuit LED off V CM V R F =.kω C F =pf or nf SCOPE V CC Ω 0V 0Ω nf Figure. CMR Test Circuit LED on V CM

17 V R F =.kω C F =pf or nf V CC 0V SCOPE Ω 0Ω nf Figure. CMR Test circuit LED off V CM V R F =.kω C F =pf or nf V CC 0V 0Ω SCOPE Ω nf V Split resistors network with a ratio of : Figure. CMR Test Circuit LED on V CM

18 Application Information Product Overview Description The ACPL-J are highly integrated power control devices that incorporate all the necessary components for a complete, isolated IGBT / MOSFET gate drive circuit with fault protection and feedback into one SO- package. Active Miller clamp function eliminates the need of negative gate drive in most application and allows the use of simple bootstrap supply for high side driver. An optically isolated power output stage drives IGBTs with power ratings of up to A and 0 V. A high speed internal optical link minimizes the propagation delays between the microcontroller and the IGBT while allowing the two systems to operate at very large common mode voltage differences that are common in industrial motor drives and other power switching applications. An output IC provides local protection for the IGBT to prevent damage during over current, and a second optical link provides a fully isolated fault status feedback signal for the microcontroller. A built in watchdog circuit, UVLO monitors the power stage supply voltage to prevent IGBT caused by insufficient gate drive voltages. This integrated IGBT gate driver is designed to increase the performance and reliability of a motor drive without the cost, size, and complexity of a discrete design. Two light emitting diodes and two integrated circuits housed in the same SO- package provide the input control circuitry, the output power stage, and two optical channels. The output Detector IC is designed manufactured on a high voltage BiCMOS/Power DMOS process. The forward optical signal path, as indicated by LED, transmits the gate control signal. The return optical signal path, as indicated by LED, transmits the fault,,, LED SHIELD SHIELD LED D R I V E R UVLO, V CC status feedback signal. Under normal operation, the LED directly controls the IGBT gate through the isolated output detector IC, and LED remains off. When an IGBT fault is detected, the output detector IC immediately begins a soft shutdown sequence, reducing the IGBT current to zero in a controlled manner to avoid potential IGBT damage from inductive over voltages. Simultaneously, this fault status is transmitted back to the input via LED, where the fault latch disables the gate control input and the active low fault output alerts the microcontroller. During power-up, the Under Voltage Lockout (UVLO) feature prevents the application of insufficient gate voltage to the IGBT, by forcing the ACPL-J s output low. Once the output is in the high state, the (VCE) detection feature of the ACPL-J provides IGBT protection. Thus, UVLO and work in conjunction to provide constant IGBT protection. Recommended Application Circuit The ACPL-J have an LED input gate control, and an open collector fault output suitable for wired OR applications. The recommended application circuit shown in Figure (page ) illustrates a typical gate drive implementation using the ACPL-J. The following describes about driving IGBT. However, it is also applicable to MOSFET. Depending upon the MOSFET or IGBT gate threshold requirements, designers may want to adjust the VCC supply voltage (Recommended V CC =.V for IGBT and.v for MOSFET). The two supply bypass capacitors (0. μf) provide the large transient currents necessary during a switching transition. Because of the transient nature of the charging currents, a low current (ma) power supply suffices. The desaturation diode D 00V/0V fast recovery type, t rr below ns (e.g. ERA-) and capacitor C BLANK are necessary external components for the fault detection circuitry. The gate resistor R G serves to limit gate charge current and controls the IGBT collector voltage rise and fall times. The open collector fault output has a passive pull-up resistor R F (. kω) and a 00 pf filtering capacitor, C F. A kω pull down resistor R PULL-DOWN on provides a predictable high level output voltage (V OH ). In this application, the IGBT gate driver will shut down when a fault is detected and fault reset by next cycle of IGBT turn on. Application notes are mentioned at the end of this datasheet. Figure. Block Diagram of ACPL-J

19 C BLANK R F 0 Ω D C F V CC R Figure. Recommended application circuit (Single Supply) with desaturation detection and active Miller Clamp R G R PULL-DOWN Q Q + V CE - + V CE - + HVDC -PHASE AC -HVDC Description of Operation Normal Operation During normal operation, of the ACPL-J is controlled by input LED current IF (pins,, and ), with the IGBT collector-to-emitter voltage being monitored through. The output is high. See Figure. Fault Condition The pin monitors the IGBT V ce voltage. When the voltage on the pin exceeds. V while the IGBT is on, is slowly brought low in order to softly turn-off the IGBT and prevent large di/dt induced voltages. Also activated is an internal feedback channel which brings the output low for the purpose of notifying the micro-controller of the fault condition. Fault Reset Once fault is detected, the output will be soft-shut down to low. All input LED signals will be ignored during the fault period to allow the driver to completely soft shut-down the IGBT. For ACPL-J, the driver will automatically reset the pin after a fixed mute time of μs (typical). See Figure. I F t (LOW).V Automatic Reset after mute time V t BLANK t (%) 0% t (0%) % 0% 0% t () t (MUTE) Figure. Fault Timing diagram (ACPL-J)

20 Output Control The outputs ( and ) of the ACPL-J are controlled by the combination of I F, UVLO and a detected IGBT Desat condition. Once UVLO is not active (V CC - > V UVLO ), VOUT is allowed to go high, and the (pin ) detection feature of the ACPL-J will be the primary source of IGBT protection. Once V CC is increased from 0V to above V UVLO+, will remain functional until V CC is decreased below V UVLO-. Thus, the detection and UVLO features of the ACPL-J work in conjunction to ensure constant IGBT protection. Desaturation Detection and High Current Protection The ACPL-J satisfies these criteria by combining a high speed, high output current driver, high voltage optical isolation between the input and output, local IGBT desaturation detection and shut down, and an optically isolated fault status feedback signal into a single -pin surface mount package. The fault detection method, which is adopted in the ACPL-J, is to monitor the saturation (collector) voltage of the IGBT and to trigger a local fault shutdown sequence if the collector voltage exceeds a predetermined threshold. A small gate discharge device slowly reduces the high short circuit IGBT current to prevent damaging voltage spikes. Before the dissipated energy can reach destructive levels, the IGBT is shut off. During the off state of the IGBT, the fault detect circuitry is simply disabled to prevent false fault signals. The alternative protection scheme of measuring IGBT current to prevent desaturation is effective if the short circuit capability of the power device is known, but this method will fail if the gate drive voltage decreases enough to only partially turn on the IGBT. By directly measuring the collector voltage, the ACPL-J limits the power dissipation in the IGBT even with insufficient gate drive voltage. Another more subtle advantage of the desaturation detection method is that power dissipation in the IGBT is monitored, while the current sense method relies on a preset current threshold to predict the safe limit of operation. Therefore, an overly conservative over current threshold is not needed to protect the IGBT. Slow IGBT Gate Discharge during Fault Condition When a desaturation fault is detected, a weak pull-down device in the ACPL-J output drive stage will turn on to softly turn off the IGBT. This device slowly discharges the IGBT gate to prevent fast changes in drain current that could cause damaging voltage spikes due to lead and wire inductance. During the slow turn off, the large output pull-down device remains off until the output voltage falls below + Volts, at which time the large pull down device clamps the IGBT gate to. Fault Detection Blanking Time The fault detection circuitry must remain disabled for a short time period following the turn-on of the IGBT to allow the collector voltage to fall below the threshold. This time period, called the blanking time is controlled by the internal charge current, the voltage threshold, and the external capacitor. The nominal blanking time is calculated in terms of external capacitance (C BLANK ), threshold voltage (V ), and charge current (I CHG ) as t BLANK = C BLANK x V / I CHG. The nominal blanking time with the recommended 0pF capacitor is 0pF *. V / 0 μa =. μsec. The capacitance value can be scaled slightly to adjust the blanking time, though a value smaller than 0 pf is not recommended. This nominal blanking time represents the longest time it will take for the ACPL-J to respond to a fault condition. If the IGBT is turned on while the collector and emitter are shorted to the supply rails (switching into a short), the soft shut-down sequence will begin after approximately μsec. If the IGBT collector and emitter are shorted to the supply rails after the IGBT is already on, the response time will be much quicker due to the parasitic parallel capacitance of the diode. The recommended 0pF capacitor should provide adequate blanking as well as fault response times for most applications. I F UVLO(V CC - ) Function Pin () Output ON Active Not Active High Low ON Not Active Active (with fault) Low () Low ON Not Active Active (no fault) High (or no fault) High OFF Active Not Active High Low OFF Not Active Not Active High Low 0

21 Under Voltage Lockout The ACPL-J Under Voltage Lockout (UVLO) feature is designed to prevent the application of insufficient gate voltage to the IGBT by forcing the ACPL-J output low during power-up. IGBTs typically require gate voltages of V to achieve their rated V CE(ON) voltage. At gate voltages below V typically, the V CE(ON) voltage increases dramatically, especially at higher currents. At very low gate voltages (below V), the IGBT may operate in the linear region and quickly overheat. The UVLO function causes the output to be clamped whenever insufficient operating supply (V CC ) is applied. Once V CC exceeds V UVLO+ (the positive-going UVLO threshold), the UVLO clamp is released to allow the device output to turn on in response to input signals. As V CC is increased from 0 V (at some level below V UVLO+ ), first the protection circuitry becomes active. As V CC is further increased (above V UVLO+ ), the UVLO clamp is released. Before the time the UVLO clamp is released, the protection is already active. Therefore, the UVLO and Fault detection feature work together to provide seamless protection regardless of supply voltage (V CC ). Active Miller Clamp A Miller clamp allows the control of the Miller current during a high dv/dt situation and can eliminate the use of a negative supply voltage in most of the applications. During turn-off, the gate voltage is monitored and the clamp output is activated when gate voltage goes below V (relative to ). The clamp voltage is V OL +.V typ for a Miller current up to 00mA. The clamp is disabled when the LED input is triggered again. V CC Figure. Output pull-down resistor. Pin Protection Resistor V CC R G R PULL-DOWN The freewheeling of flyback diodes connected across the IGBTs can have large instantaneous forward voltage transients which greatly exceed the nominal forward voltage of the diode. This may result in a large negative voltage spike on the pin which will draw substantial current out of the driver if protection is not used. To limit this current to levels that will not damage the driver IC, a 0 ohm resistor should be inserted in series with the diode. The added resistance will not alter the threshold or the blanking time. Other Recommended Components The application circuit in Figure includes an output pull-down resistor, a pin protection resistor, a pin capacitor, and a pin pullup resistor and Active Miller Clamp connection. V CC 0pF 0 Ω V CC D Output Pull-Down Resistor R G During the output high transition, the output voltage rapidly rises to within diode drops of V CC. If the output current then drops to zero due to a capacitive load, the output voltage will slowly rise from roughly V CC -(V BE ) to V CC within a period of several microseconds. To limit the output voltage to V CC -(V BE ), a pull-down resistor, R PULL-DOWN between the output and is recommended to sink a static current of several 0 μa while the output is high. Pull-down resistor values are dependent on the amount of positive supply and can be adjusted according to the formula, R pull-down = [V CC - * (V BE )] / 0 μa. Figure. pin protection.

22 Capacitor on Pin for High CMR Rapid common mode transients can affect the fault pin voltage while the fault output is in the high state. A 00 pf capacitor should be connected between the fault pin and ground to achieve adequate CMOS noise margins at the specified CMR value of 0 kv/μs. Pull-up Resistor on Pin The pin is an open collector output and therefore requires a pull-up resistor to provide a high-level signal. Also the output can be wire OR ed together with other types of protection (e.g. over-temperature, overvoltage, over-current ) to alert the microcontroller. Other Possible Application Circuit (Output Stage) V CC Optional R Optional R R G R PULL-DOWN +_ * Q Q + V CE - + V CE - + HVDC -PHASE AC - HVDC Figure 0. IGBT drive with negative gate drive, external booster and desaturation detection ( should be connected to when it is not used) VCLAMP is used as secondary gate discharge path. * indicates component required for negative gate drive topology V CC Optional R Optional R R G R PULL-DOWN * Q Q + V CE - + V CE - + HVDC -PHASE AC - HVDC R Figure. Large IGBT drive with negative gate drive, external booster. control secondary discharge path for higher power application.

23 Thermal Model The ACPL-J is designed to dissipate the majority of the heat through pins,, & for the input IC and pins & for the output IC. (There are two pins on the output side, pins and, for this purpose.) Heat flow through other pins or through the package directly into ambient are considered negligible and not modeled here. In order to achieve the power dissipation specified in the absolute maximum specification, it is imperative that pins,, and have ground planes connected to them. As long as the maximum power specification is not exceeded, the only other limitation to the amount of power one can dissipate is the absolute maximum junction temperature specification of C. The junction temperatures can be calculated with the following equations: T ji = P i (θ i + θ A ) + T A T jo = Po (θ o, + θ,a ) + T A where P i = power into input IC and P o = power into output IC. Since θ A and θ,a are dependent on PCB layout and airflow, their exact number may not be available. Therefore, a more accurate method of calculating the junction temperature is with the following equations: T ji = P i θ i + T P T jo = P o θ o, + T P, These equations, however, require that the pin and pins, temperatures be measured with a thermal couple on the pin at the ACPL-J package edge. If the calculated junction temperatures for the thermal model in Figure is higher than C, the pin temperature for pins and should be measured (at the package edge) under worst case operating environment for a more accurate estimate of the junction temperatures. Figure. ACPL-J Thermal Model T ji = junction temperature of input side IC T jo = junction temperature of output side IC T P = pin temperature at package edge T P, = pin and temperature at package edge θ I = input side IC to pin thermal resistance θ o, = output side IC to pin and thermal resistance θ A = pin to ambient thermal resistance θ,a = pin and to ambient thermal resistance *The θ A and θ,a values shown here are for PCB layouts with reasonable air flow. This value may increase or decrease by a factor of depending on PCB layout and/or airflow. Related Application Notes AN Active Miller Clamp AN Soft Turn-off Feature AN Common-Mode Noise : Sources and Solutions AV0-0EN - Plastic Optocouplers Product ESD and Moisture Sensitivity For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 00-0 Avago Technologies. All rights reserved. Obsoletes AV0-0EN AV0-EN - October, 0