ACPL-337J 4.0 Amp Gate Drive Optocoupler with Integrated (V CE ) Desaturation Detection, Active Miller Clamping, Fault and UVLO Status Feedback

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1 ACPL-J.0 Amp Gate Drive Optocoupler with Integrated (V CE ) Desaturation Detection, Active Miller Clamping, Fault and Status Feedback Data Sheet Lead (Pb) Free RoHS fully compliant RoHS fully compliant options available; -xxxe denotes a lead-free product Description Avago s ACPL-J gate drive optocoupler features fast propagation delay with excellent timing skew performance. Smart features that are integrated to protect the IGBT include IGBT desaturation detection with softshutdown protection and fault feedback, undervoltage lockout and feedback, and active Miller current clamping. This full-featured and easy-to-implement IGBT gate drive optocoupler comes in a compact, surface-mountable SO- package for space-savings. It is suitable for driving IGBTs and power MOSFETs used in motor control and inverter applications. Avago isolation products provide reinforced insulation and reliability that delivers safe signal isolation critical in high voltage and noisy industrial applications. Functional Diagram V IN DRV V CC E Input LED Driver Fault Decoder LED LED Output Driver V CC Soft Shut Features.0 A maximum peak output current Rail-to-rail output voltage.0 A Miller Clamp IGBT desaturation detection Integrated fail-safe IGBT protection - Desaturation detection, Soft IGBT turn-off and fault feedback - UnderVoltage LockOut () Protection with feedback 0 ns maximum propagation delay over temperature Integrated LED driver 0 kv/µs minimum Common Mode Rejection (CMR) at V CM = 00 V Wide operating voltage: V to 0 V Wide operating temperature range: -0 C to C SO- package with mm clearance and creepage Regulatory approvals: UL, V ISO = 000 V RMS for min. CSA IEC/EN/DIN EN 0-- V IORM = V peak Applications Isolated IGBT/Power MOSFET gate drive Renewable energy inverters AC and brushless DC motor drives Industrial Inverters Switching power supplies CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.

2 Product Overview Description The ACPL-J is a highly integrated power control device that incorporates all the necessary components for a complete, isolated IGBT gate drive circuit. It features IGBT desaturation detection with soft-shutdown protection and fault feedback, undervoltage lockout and feedback, and active Miller current clamping in a SO- package. Direct LED input with or without integrated LED driver allows flexible logic configuration and differential current mode driving with low input impedance, greatly increasing its noise immunity. Pin Description Pin Symbol Description E E Input common V IN Non inverting voltage control input. V IN V CC Input power supply (. V to. V) V CC DRV V CC DRV Integrated LED driver output. V CC undervoltage lockout feedback fault feedback Input LED anode Input LED cathode Negative power supply Miller current clamping output Driver output to IGBT gate V CC Positive power supply Common (IGBT emitter) output supply voltage. Desaturation voltage input. When the voltage on exceeds an internal reference voltage of V while the IGBT is on, will soft shut down and will change from High impedance to Low logic state No connection, for testing only Negative power supply Ordering Information ACPL-J is UL Recognized with 000 Vrms for minute per UL. Part number Option RoHS Compliant Package Surface Mount Tape & Reel IEC/EN/DIN EN 0-- Quantity ACPL-J -000E SO- X X per tube -00E X X X 0 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example : ACPL-J-00E to order product of SO- Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 0-- Safety Approval in RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

3 Package Outline Drawings ACPL-J -Lead Surface Mount Package 0.0 (0.) 0.00 (.0) LAND PATTERN RECOMMENDATION 0.0 (0. ) AVAGO LEAD-FREE A J YYWW EEE 0. ± 0.0 (. ± 0.) TYPE NUMBER DATE CODE 0. (.) LOT ID 0.0 ± 0. (. ± 0.) 0. ± 0.0 (. ± 0.) 0.0 (.) ALL LEADS TO BE COPLANAR ± (0.) 0. ± 0.00 (.0 ± 0.) MIN. 0.0 ± 0.0 (. ± 0.) 0.00 ± 0.00 (0.0 ± 0.0) STANDOFF Dimensions in inches (millimeters) Notes: Initial and continued variation in the color of the ACPL-J s white mold compound is normal and does note affect device performance or reliability. Lead coplanarity = 0. mm (0.00 inches) Floating Lead Protrusion is 0. mm ( mils) max. Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-00 (latest revision). Non- Halide Flux should be used. Regulatory Information The ACPL-J is approved by the following organizations: IEC/EN/DIN EN 0-- Maximum working insulation voltage V IORM = V PEAK UL Approval under UL, component recognition program up to V ISO = 000 V RMS. File E. CSA Approval under CSA Component Acceptance Notice #, File CA.

4 Table. IEC/EN/DIN EN 0-- Insulation Characteristics* Description Symbol Characteristic Unit Installation classification per DIN VDE 0/, Table for rated mains voltage 0 V RMS for rated mains voltage 00 V RMS for rated mains voltage 00 V RMS for rated mains voltage 00 V RMS I IV I IV I IV I III Climatic Classification 0// Pollution Degree (DIN VDE 0/) Maximum Working Insulation Voltage V IORM V peak Input to Output Test Voltage, Method b** V IORM x. = V PR, 0% Production Test with t m = sec, Partial discharge < pc Input to Output Test Voltage, Method a** V IORM x. = V PR, Type and Sample Test, t m = sec, Partial discharge < pc V PR V peak V PR V peak Highest Allowable Overvoltage (Transient Overvoltage t ini = 0 sec) V IOTM 000 V peak Safety-limiting values maximum values allowed in the event of a failure. Case Temperature T S C Input Current I S, INPUT 00 ma Output Power P S, OUTPUT 0 mw Insulation Resistance at T S, V IO = 00 V R S > W * Isolation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits in application. Surface mount classification is class A in accordance with CECCOO0. ** Refer to the optocoupler section of the Isolation and Control Components Designer s Catalog, under Product Safety Regulations section IEC/EN/ DIN EN 0--, for a detailed description of Method a and Method b partial discharge test profiles. Table. Insulation and Safety Related Specifications Parameter Symbol ACPL-J Units Conditions Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) L(). mm Measured from input terminals to output terminals, shortest distance through air. L(). mm Measured from input terminals to output terminals, shortest distance path along body. 0. mm Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. CTI > V DIN IEC /VDE 00 Part Isolation Group IIIa Material Group (DIN VDE 0, /, Table )

5 Table. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note Storage Temperature T S - C Operating Temperature T A -0 C Output IC Junction Temperature T J C Average Input Current I F(AVG) 0 ma Peak Transient Input Current (< µs pulse width, 00 pps) I F(TRAN) A Reverse Input Voltage V R V Peak Output Current I O(PEAK) A Output Current I ma Pin Voltage V -0. V CC V Output Current I ma Pin Voltage V -0. V CC V Non Inverting Voltage Control Input Voltage V IN -0. V CC V Integrated LED Driver Output Current I LEDDRV 0 ma Integrated LED Driver Output Voltage DRV -0. V CC V Positive Input Supply Voltage V CC V Total Output Supply Voltage V CC -0. V Negative Output Supply Voltage -0. V Positive Output Supply Voltage V CC -0. ( E ) V Gate Drive Output Voltage V O(PEAK) -0. V CC V Peak Clamping Sinking Current I CLAMP A Miller Clamping Pin Voltage -0. V CC V Voltage V 0. (V CC 0.) V Output IC Power Dissipation P O 00 mw Input LED Power Dissipation P I 0 mw Notes:. Derate linearly above 0 C free-air temperature at a rate of 0. ma/ C.. Maximum pulse width = µs. This supply is optional and is required only when negative gate drive is implemented.. Derate linearly above C free-air temperature at a rate of 0 mw/ C.. Derate linearly above C free-air temperature at a rate of mw/ C. The maximum LED junction temperature should not exceed C. Table. Recommended Operating Conditions Parameter Symbol Min. Max. Units Note Operating Temperature T A -0 C Input supply voltage V CC.. V Total Output Supply Voltage V CC 0 V Negative Output Supply Voltage ( E ) 0. V Positive Output Supply Voltage V CC 0 ( E ) V Input LED Current I F(ON) ma Input Voltage (OFF) V F(OFF) V Notes:. In most applications V CC will be powered up first (before V CC ) and powered down last (after V CC ). This is desirable for maintaining control of the IGBT gate. In applications where V CC is powered up first, it is important to ensure that input remains low until V CC reaches the proper operating voltage (minimum. V) to avoid any momentary instability at the output during V CC ramp-up or ramp-down.. V is the recommended minimum operating positive supply voltage (V CC - ) to ensure adequate margin in excess of the maximum V threshold of. V.. This supply is optional and is required only when negative gate drive is implemented.

6 Table. Electrical Specifications (DC) Unless otherwise noted, all typical values at T A = C, V CC = V, V CC = 0 V, = 0 V; all Minimum/ Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note Logic Low Input Voltage V INL 0. V Logic High Input Voltage V INH V Logic High LED Driver Output R DS(ON) R LEDDRVH.. Ω I LEDDRV = - ma, V IN = V Logic Low LED Driver Output Voltage DRVL V I LEDDRV =. ma, V IN = 0 V Input Low Supply Current I CCL ma I F = 0 ma, V IN = 0 V Input High Supply Current I CCH ma I F = ma, V IN =0 V ma I LEDDRV = ma, V IN = V Output Low Supply Current I CCL.. ma I F = 0 ma, Output High Supply Current I CCH.. ma I F = ma, LED Forward Voltage V F... V I F = ma Temperature Coefficient of Input ΔV F /ΔT A -. mv/ C I F = ma Forward Voltage LED Reverse Breakdown Voltage V BR V I F = µa Input Capacitance C IN 0 pf LED Turn on Current Threshold Low I TH 0. ma = V to High LED Turn on Current Threshold High I TH ma = V to Low LED Turn on Current Hysteresis I THHYS 0. ma High Level Output Current I OH A V CC - = V Low Level Output Current I OL. A - E = V High Output Transistor R DS(ON) R DS,OH 0... Ω I OH = - A Low Output Transistor R DS(ON) R DS,OL 0... Ω I OL = A Low Level Output Current During Fault Condition I OLF ma - E = V High Level Output Voltage V OH V CC 0. V CC 0. V I OUT = -0 ma,, Low Level Output Voltage V OL V I OUT = 0 ma Clamp Threshold Voltage V THCLAMP V Clamp Low Level Sinking Current I CLAMP 0.. A = E. Clamp Output Transistor R DS(ON) R DS,CLAMP.. Ω I CLAMP = A V CC Threshold Low to High V.. V > V,, V CC Threshold High to Low V -... V < V,, V CC Hysteresis V HYS 0.. V Detection Threshold V.. V Charging Current I CHG ma V = V, Discharging Current I DSCHG 0 ma V = V Logic Low Output Current I L.0 ma V = 0. V Logic High Output Current I H 0 µa V = V Logic Low Output Current I L.0 ma V = 0. V Logic High Output Current I H 0 µa V = V Notes:. Maximum pulse width = μs.. Output is sourced at -.0 A/.0 A with a maximum pulse width = μs.. For further details, see the description of operation during fault condition section in the application notes.. V is the recommended minimum operating positive supply voltage (V CC ) to ensure adequate margin in excess of the maximum V threshold of. V. For High Level Output Voltage testing, V OH is measured with a DC load current. When driving capacitive loads, V OH will approach V CC as I OH approaches zero.. Maximum pulse width =.0 ms.. Once of ACPL-J is allowed to go High (V CC > V ), the detection feature of the ACPL-J will be the primary source of IGBT protection. is needed to ensure is functional. Once V CC exceeds V threshold, will remain functional until V CC is below V - threshold. Thus, the detection and features of the ACPL-J work in conjunction to ensure constant IGBT protection.. This is the increasing (i.e. turn-on or positive going direction) of V CC.. This is the decreasing (i.e. turn-off or negative going direction) of V CC.. For further details, see the fault detection blanking time section in the applications notes.

7 Table. Switching Specifications (AC) Unless otherwise noted, all typical values at T A = C, V CC = V, V CC = 0 V, = 0 V; all Minimum/ Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note Input LED to High Level Output Propagation Delay Time Input LED to Low Level Output Propagation Delay Time t PLH 0 0 ns R G = Ω, C G = nf, f = khz, Duty Cycle = 0%,, t PHL 0 0 ns,, Pulse Width Distortion PWD ns, Propagation Delay Difference Between Any Parts (t PHL -t PLH ) P DD -0 0 ns, Propagation Delay Skew t PSK 0 ns, % to 0% Rise Time t R 0 ns 0% to % Fall Time t F ns Blanking Time t (BLANKING) 0.. µs Sense to 0% Delay t (0%). µs R G = Ω, C G = nf Sense to % Delay t (%).. µs Sense to Low Propagation Delay Sense to Low Level Signal Delay t (LOW) 0. µs t (). µs R F = kω, C F = Open Output Mute Time due to t (MUTE)..0. ms Time Input Kept Low Before Fault Reset to High t (RESET)..0. ms R F = kω, C F = Open V CC to High Delay t PLH µs V CC to Low Delay t PHL µs V CC to High Delay t ON. µs V CC to Low Delay t OFF µs Output High Level Common Mode Transient Immunity Output Low Level Common Mode Transient Immunity CM H 0 >0 kv/µs T A = C, I F = ma, V CM = 00 V, V CC = 0 V CM L 0 >0 kv/µs T A = C, I F = 0 ma, V CM = 00 V, V CC = 0 V,,, 0,, Notes:. t PLH is defined as propagation delay from 0% of LED input I F to 0% of High level output.. t PHL is defined as propagation delay from 0% of LED input I F to 0% of Low level output.. Pulse Width Distortion (PWD) is defined as t PHL - t PLH for any given unit.. As measured from I F to.. The difference between t PHL and t PLH between any two ACPL-J parts under the same test conditions.. t PSK is equal to the worst-case difference in t PHL and t PLH that will be seen between units under the same test condition.. The ACPL-J internal delay time to respond to a fault condition without any external capacitor.. The amount of time from when threshold is exceeded to 0% of V GATE at mentioned test conditions.. The amount of time from when threshold is exceeded to % of V GATE at mentioned test conditions.. The amount of time from when threshold is exceeded to Low voltage, 0. V.. The amount of time from when threshold is exceeded to output Low 0% of V CC voltage.. The amount of time when threshold is exceeded, output is muted to LED input.. The amount of time when mute time is expired, LED input must be kept low for status to return to High.. The delay time when V CC exceeds threshold to high 0% of positive-going edge.. The delay time when V CC exceeds - threshold to low 0% of negative-going edge.. The delay time when V CC exceeds threshold to 0% of high level output.. The delay time when V CC exceeds - threshold to 0% of low level output.. Common mode transient immunity in the high state is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in the high state (i.e., > V or > V or > V). A 0 pf and a kω pull-up resistor are needed in and detection mode.. Common mode transient immunity in the low state is the maximum tolerable dv CM /dt of the common mode pulse, V CM, to assure that the output will remain in a low state (i.e., <.0 V or < 0. V or < 0. V). 0. Split resistor network in the ratio : at the anode and cathode. For further details, see description of input LED driver and split resistors circuit section in the application notes., 0, 0

8 Table. Package Characteristics Parameter Symbol Min. Typ. Max. Units Test Conditions Note Input-Output Momentary Withstand Voltage V ISO 000 V RMS RH < 0%, t = min., T A = C Resistance (Input-Output) R I-O > W V I-O = 00 V DC Capacitance (Input-Output) C I-O. pf freq = MHz Thermal Coefficient Between LED and Input IC LED and Output IC Input IC and Output IC LED and Ambient Input IC and Ambient Output IC and Ambient A EI A EO A IO A EA A IA A OA..... Notes. In accordance with UL, each optocoupler is proof tested by applying an insulation test voltage 000 V RMS for second. This test is performed before the 0% production test for partial discharge (method b) shown in IEC/EN/DIN EN 0-- Insulation Characteristic Table, if applicable.. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating, refer to your equipment level safety specification or IEC/EN/DIN EN 0-- Insulation Characteristics Table.. Device considered a two-terminal device: pins to are shorted together and pins to are shorted together.. For further details, see thermal calculation section in the application notes. C/W C/W C/W C/W C/W C/W,, ICC - INPUT SUPPLY CURRENT - ma I F = ma for I CCH I F = 0 ma for I CCL V CC = 0 V E = 0 V I CCL I CCH T A - TEMPERATURE - C Figure. I CC vs. temperature ICC - OUTPUT SUPPLY CURRENT - ma I F = ma for I CCH I F = 0 ma for I CCL V CC = 0 V E = 0 V.0. I CCL I CCH T A - TEMPERATURE - C Figure. I CC vs. temperature ICC- SUPPLY CURRENT - ma I F = ma for I CCH I F = ma for I CCL T A = C E = 0 V.0 I. CCL I CCH.0 V CC - SUPPLY VOLTAGE - V Figure. I CC vs.v CC I F - LED FORWARD CURRENT - ma V F - LED FORWARD VOLTAGE - V Figure. LED Input Current vs. forward voltage

9 VOH - OUTPUT HIGH VOLTAGE - V 0 I F = ma V CC = 0 V E = 0 V I OH - OUTPUT HIGH CURRENT - A Figure. I OH vs.v OH VOL - OUTPUT LOW VOLTAGE - V I F = 0 ma V CC = 0 V E = 0 V I OL - OUTPUT LOW CURRENT - A Figure. I OL vs.v OL VOH - HIGH OUTPUT VOLTAGE DROP - V I F = ma I OUT = -0 ma V CC = 0 V = 0 V T A - TEMPERATURE - C Figure. V OH vs. temperature V OL - LOW OUTPUT VOLTAGE - V T A - TEMPERATURE - C Figure. V OL vs. temperature I F = 0 ma I OUT = -0 ma V CC = 0 V E = 0 V I OLF - LOW LEVEL OUTPUT CURRENT DURING CONDITION - ma E - OUTPUT LOW VOLTAGE - V Figure. I OLF vs. output voltage V - THRESHOLD - V T A - TEMPERATURE - C Figure. V vs. temperature

10 ICHG - CHARGING CURRENT - ma T A - TEMPERATURE - C Figure. I CHG vs. temperature IDSCHG - DISCHARGING CURRENT - ma T A - TEMPERATURE - C Figure. I DSCHG vs. temperature I 0 F = ma R G = Ω, C G = nf t 0 PLH DUTY CYCLE = 0% f = khz t PHL T A - TEMPERATURE - C Figure. Propagation delay vs. temperature tp - PROPAGATION DELAY - ns tp - PROPAGATION DELAY - ns I F = ma R G = Ω, C G = nf DUTY CYCLE = 0% f = khz 0 0 V CC - SUPPLY VOLTAGE - V Figure. Propagation delay vs. supply voltage t PLH t PHL tp - PROPAGATION DELAY - ns I F = ma C G = nf DUTY CYCLE = 0% f = khz 0 t PLH t PHL LOAD RESISTANCE - Ω Figure. Propagation delay vs. load resistance

11 VEE VIN VCC V VLEDDRV V CC Ω nf 0 V Scope V CM = 00 V Figure. CMR High test circuit VEE VIN VCC VLEDDRV V CC Ω nf 0 V Scope V CM = 00 V Figure. CMR Low test circuit VEE VIN VCC kω Scope 0 pf V VLEDDRV V CC Ω nf 0 V Figure. CMR High test circuit V CM = 00 V

12 VEE VIN VCC kω Scope 0 pf V VLEDDRV V CC Ω nf 0 V Figure. CMR Low test circuit V CM = 00 V VEE VIN VCC Scope kω 0 pf V VLEDDRV V CC Ω nf 0 V Figure 0. CMR High test circuit V CM = 00 V VEE VIN VCC Scope kω 0 pf V VLEDDRV V CC Ω nf V CM = 00 V Figure. CMR Low test circuit

13 Applications Information Recommended Application Circuit kω kω 0 pf 0 pf VEE VIN VCC VLEDDRV V CC k Ω C BLANK =0 pf R G D Q Q V CE - Figure. Typical gate drive circuits with detection kω kω 0 pf 0 pf VEE VIN VCC VLEDDRV V CC k Ω D C BLANK =0 pf R OUT R G R C Figure. Typical parallel IGBT gate drive circuits with detection The ACPL-J has non-inverting gate control inputs, and an open drain and outputs suitable for wired OR applications. The two supplies bypass capacitors () provide the large transient currents necessary during a switching transition. The diode and 0 pf blanking capacitor are the necessary external components for the fault detection circuitry. The gate resistor (R G ) serves to limit gate charge current and indirectly control the IGBT collector voltage rise and fall times. The open drain and outputs have passive kω pull-up resistors and a 0 pf filtering capacitor.

14 Introduction to Detection The power stage of a typical three phase inverter is susceptible to several types of failures, most of which are potentially destructive to the power IGBTs. These failure modes can be grouped into four basic categories: phase and/or rail supply short circuits due to user misconnect or bad wiring, control signal failures due to noise or computational errors, overload conditions induced by the load, and component failures in the gate drive circuitry. Under any of these fault conditions, the current through the IGBTs can increase rapidly, causing excessive power dissipation and heating. The IGBTs become damaged when the current load approaches the saturation current of the device, and the collector to emitter voltage rises above the saturation voltage level. The drastically increased power dissipation very quickly overheats the power device and destroys it. To prevent damage to the drive, fault protection must be implemented to reduce or turn-off the IGBTs during a fault condition. A circuit providing fast local detection and shutdown is an ideal solution, but the number of required components, board space consumed, cost, and complexity have until now limited its use to high performance drives. The features that this circuit must have are high speed, low cost, low resolution, low power dissipation, and small size. The ACPL-J satisfies these criteria by combining a high speed, high output current driver, high voltage optical isolation between the input and output, local IGBT desaturation detection and shut down, and optically isolated fault and status feedback signal into a single -pin surface mount package. The fault detection method, which is adopted in the ACPL-J, is to monitor the saturation (collector) voltage of the IGBT and to trigger a local fault shutdown sequence if the collector voltage exceeds a predetermined threshold. A small gate discharge device slowly reduces the high short circuit IGBT current to prevent damaging voltage spikes. Before the dissipated energy can reach destructive levels, the IGBT is shut off. During the off state of the IGBT, the fault detect circuitry is simply disabled to prevent false fault signals. The alternative protection scheme of measuring IGBT current to prevent desaturation is effective if the short circuit capability of the power device is known, but this method will fail if the gate drive voltage decreases enough to only partially turn on the IGBT. By directly measuring the collector voltage, the ACPL-J limits the power dissipation in the IGBT even with insufficient gate drive voltage. Another more subtle advantage of the desaturation detection method is that power dissipation in the IGBT is monitored, while the current sense method relies on a preset current threshold to predict the safe limit of operation. Therefore, an overly-conservative overcurrent threshold is not needed to protect the IGBT. Output Control The outputs (, and ) of the ACPL-J are controlled by the combination of V CC, V CC (), LED current I F and IGBT desaturation condition. The following table shows the logic truth table for these outputs. V CC V CC () I F Fault Low Low X Not Active Low Low Low Low High Low Not Active Low Low Low Low High High Active (no fault) High Low Low Low High High Active ( fault) Low Low Low High Low X Not Actve Low High Low High High High Active ( fault) Low Low High High High Low Not Active Low High High High High High Active (no fault) High High High The logic level is defined by the respective threshold of each function pin.

15 Description of UnderVoltage LockOut Insufficient gate voltage to IGBT can increase turn-on resistance of IGBT, resulting in large power loss and IGBT damage due to high heat dissipation. ACPL-J monitors the output power supply constantly. When output power supply is lower than undervoltage lockout () threshold, the gate driver output will shut off to protect IGBT from low voltage bias. The low output power supply fault will be reported via the feedback. In this way, the feedback can also serve as a READY signal to the controller during power up. V CC V CC V V LED I F t OFF ton t PHL t PLH Figure. and feedback behaviors and timing diagram Description of Input LED Driver and Split Resistors Circuit The ACPL-J has integrated an input LED driver that with high impedance input(v IN ) for interfacing with the controller. The LED driver s output(drv ) has to be connected with the recommended split resistors circuit to the LED anode to achieve the rated high CMR performance. The LED current can be calculated by I LEDDRV = (V CC - V F )/(R LEDDRVH R). Alternatively, if the LED driver is not used, LED can still be driven directly by other means of discrete driver configuration. It is recommended that the two resistors (R) connected to input LED s anode and cathode are split in the ratio :. They will help to balance the common mode impedances at the LED s anode and cathode. This helps to equalize the common mode voltage changes at the anode and cathode to give high CMR performance. V V E V IN V CC DRV R LEDDRVH I LEDDRV = (V CC - V F )/(R LEDDRVH R) I LEDDRV R R LED Figure. Input LED driver functional diagram

16 Fault Detection Blanking Time The fault detection circuitry must remain disabled for a short time period following the turn-on of the IGBT to allow the collector voltage to fall below the theshold. This time period, called the blanking time, is controlled by the internal charge current, the voltage threshold, and the external capacitor. The nominal blanking time is calculated in terms of external capacitance (C BLANK, see Figure and Figure ), threshold voltage (V ), and charge current (I CHG ) in addition to an internal blanking time (t (BLANKING) ). t BLANK = C BLANK (V /I CHG ) t (BLANKING) Description of Operation during Fault Condition. terminal monitors IGBT s V CE voltage.. When the voltage on the terminal exceeds V, a weak pull-down in the output stage(i OLF ) will turn on to softly turn off the IGBT. When the gate voltage falls below E V, the Miller Clamp will turn on to clamp the IGBT gate to E.. output goes low, notifying the microcontroller of the fault condition.. Microcontroller takes appropriate action.. When t (MUTE) expires, LED input needs to be kept low for t (RESET) before fault condition is cleared. status will return to high.. Output ( ) starts to respond to LED input after fault condition is cleared. t (MUTE) LED I F t (0%) 0% % V t (%) V t(blanking) t(low) t(blanking) 0% t() Figure. fault state timing diagram t(reset) Selecting the Gate Resistor (R G ) Step : Calculate R G minimum from the I O(PEAK) specification. The IGBT and R G in Figure can be analyzed as a simple RC circuit with a voltage supplied by ACPL-J. R G V CC E R DS, OH( MIN) I O(PEAK) = 0 0 V 0. Ω A = Ω or R G V CC E R DS, OL( MIN) I O(PEAK) = 0 0 V 0. Ω A =. Ω The external gate resistor, R G and internal minimum turn-on resistance, R DSON will ensure the output current will not exceed the device absolute maximum rating of A. In this case, we will use worst-case R G. Ω.

17 Step : Check the ACPL-J power dissipation and increase R G if necessary. The ACPL-J total power dissipation (P T ) is equal to the sum of the LED power (P E ), input IC power(p I ) and the output IC power (P O ). P T = P E P I P O Assuming operation conditions of I F (worst case) = ma, R G =. Ω, Max Duty Cycle = 0%, Q G = µc, f = khz and T A max = C. Calculation of LED Power Dissipation P E = I F V F Duty Cycle = ma. V 0. = mw Calculation of Input IC Power Dissipation P I = I CC (Max) * V CC (Recommended Max) = ma *. V = mw Calculation of Input IC Power Dissipation P O = P O(BIAS) P O(SWITCHING) = I CC (V CC - ) P HS P LS P HS = (V CC *Q G *f) * R DS,OH(MAX) / (R DS,OH(MAX) R G ) / P LS = (V CC *Q G *f) * R DS,OL(MAX) / (R DS,OL(MAX) R G ) / P HS = (0 V µc khz). Ω/(. Ω. Ω)/ =. mw P LS = (0 V µc khz). Ω/(. Ω. Ω)/ =. mw P O =. ma 0 V. mw. mw =. mw < 00 mw (P C) The value of. ma for I CC in the previous equation is the maximum I CC over the entire operating temperature range. Since P O is less than P O(MAX), R G =. Ω is all right for the power dissipation. Thermal Calculation Application and environmental design for ACPL-J needs to ensure that the junction temperature of the internal ICs and LED within the gate driver optocoupler do not exceed C. The following equations calculate the maximum power dissipation effect on junction temperatures. LED Junction Temperature, T E = A EA *P E A EI *P I A EO *P O T A =. C/W * mw. C/W * mw. C/W *. mw C =. C Input IC Junction Temperature, T I = A EI *P E A IA *P I A IO *P O T A =. C/W * mw C/W * mw.*. mw C =. C Output IC Junction Temperature, T O = A EO *P E A IO *P I A OA *P O T A =. C/W * mw. C/W * mw.*. mw C =. C

18 Diode and Threshold The diode's function is to conduct forward current, allowing sensing of the IGBT's saturated collector-to-emitter voltage, V CESAT, (when the IGBT is "on") and to block high voltages (when the IGBT is "off"). When the IGBT is switching off and toward the end of the forward conduction of the diode, a reverse current will flow for short time. This reverse recovery effect prevents the diode from achieving its blocking capability until the mobile charge in the junction is depleted. During this time, there is commonly a very high dv CE /dt voltage ramp rate across the IGBT s collector-to-emitter. This results in I CHARGE = C D- x dv CE /dt charging current which will charge the blanking capacitor, C BLANK. To minimize this charging current and avoid false triggering, it is best to use fastresponse diodes. In the recommended application circuit shown in Figure, the voltage on pin () is V = V F V CE, where V F is the forward ON voltage of D and V CE is the IGBT collector-to-emitter voltage. The value of V CE that triggers to signal a condition is nominally V V F. If desired, this threshold voltage can be decreased by using multiple diodes or low-voltage Zener diode in series. If n is the number of diodes, the nominal threshold value becomes V CE,(TH) = V n V F. If a Zener diode is used, the nominal threshold value becomes V CE,(TH) = V V F V Z. When using two diodes instead of one, then diodes with half of the total required maximum reverse-voltage rating may be chosen. kω D ZENER D V Zener NA kω D C BLANK Q V CE - C BLANK Schottky Diode MBR00 Q V CE - Figure. diode and threshold Pin Protection Resistor The freewheeling of flyback diodes connected across the IGBTs can have large instantaneous forward voltage transients that greatly exceed the nominal forward voltage of the diode. This may result in a large negative voltage spike on the pin, which will draw substantial current out of the driver if protection is not used. To limit this current to levels that will not damage the driver IC, make sure a kω resistor is inserted in series with the diode. False Fault Prevention Diodes Figure. False fault prevention diodes A situation that may cause the driver to generate a false fault signal is if the substrate diode of the driver becomes forward biased. This can happen if the reverse recovery spikes coming from the IGBT freewheeling diodes bring the pin below Ground. Therefore, the pin voltage will be brought above the threshold voltage. This negative going voltage spikes are typically generated by inductive loads or reverse recovery spikes of the IGBT/MOSFETs freewheeling diodes. To prevent a false fault signal, it is highly recommended that you connect a Zener diode and a Schottky diode across the pin and pin Figure shows this circuit solution. The Schottky diode will prevent the substrate diode of the gate driver optocoupler from being forward biased while the Zener diode ( V) is used to prevent any positive high transient voltage from affecting the pin. For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 00-0 Avago Technologies. All rights reserved. AV0-0EN - May, 0