Chapter 2 Nanoscale Effects: Gate Oxide Leakage Currents

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1 Chapter 2 Nanoscale Effects: Gate Oxide Leakage Currents 2.1 Introduction The microelectronics revolution has been primarily enabled by the nearly ideal properties of SiO 2 and its interface with Si. Continually thinner gate oxides have been a critical feature of the overall scaling of transistor dimensions for six decades, enabling continued speed improvement even as operating voltages decrease. Table 1.1 in Chap. 1 shows the 2004 ITRS trends for effective channel length (L eff ) and oxide thickness scaling. This reduction in the oxide thickness to nanometers causes a flow of leakage current between substrate and the gate through the oxide. This current is caused by carriers tunneling through the insulator potential barrier, quantum mechanical effects (QME) that has no classical explanation. The gate oxide current affects the performance of circuits that employ MOS devices, and it can be a limiting factor in further device down-scaling. Nevertheless, given the practical feasibility of devices that have a significant gate tunneling current under normal operating conditions, knowledge of the basic mechanisms of gate tunneling current and the modeling and circuit design issues that are involved, will probably be essential for anyone working with these devices. The aggressive scaling of CMOS technology is becoming more difficult because of the physical limits imposed on the Si and its oxide due to the leakage currents in both vertical and lateral directions. The aggressive scaling of CMOS technology is becoming more difficult because of the physical limits imposed on Si and its oxide due to the leakage currents in vertical directions. In nanoscale MOSFETs, the oxide thickness is of the order of a few angstroms and further scaling down is not possible with the existing technology. The leakage currents in such thin oxides reach such a high value as comparable to ON state currents that they make the device useless causing unwanted very high static power dissipation. A. Chaudhry, Fundamentals of Nanoscaled Field Effect Transistors, DOI / _2, # Springer Science+Business Media New York

2 26 2 Nanoscale Effects: Gate Oxide Leakage Currents 2.2 Gate Oxide Tunneling Phenomenon As MOSFETs are scaled down to nanoscale, QMEs need to be considered in MOSFET design and modeling. In today s CMOS technology, the gate oxide thickness of a MOSFET is less than 1.5 nm, and the channel is doped as high as cm 3. For MOSFETs with heavily doped channels and ultrathin oxide layers, the field in the oxide can reach very high values of MV/cm. The ultrathin oxide layer reduces the width of the energy barrier that separates the gate from the channel, thus making it easier for electrons/holes to tunnel through the insulator layer as shown in Fig This direct gate tunneling current could be the dominant source of device leakage, leading to faulty circuit operation and the increase in standby power in the MOSFET. In the ultrathin oxide MOSFETs, the application of the gate voltage has a big role in the type of leakage current. The larger the gate voltage, the larger the electric fields generated in the substrate will be and more energy will be given to the carriers in the substrate, thus increasing the chances of tunneling. Moreover, the oxide potential barrier becomes steep and allows QMT. Depending on the gate voltage magnitude, two types of tunneling take place. One is the Fowler Nordheim (FN) tunneling, and second is the QMDT FN Tunneling in a MOSFET For lower gate voltages, the FN tunneling occurs owing to the conduction of electrons from the conduction band of Si substrate to the conduction band of poly-si gate through the conduction band of SiO 2. Here the conduction band of the oxide is triangular in nature as shown in Fig The FN tunneling current density is a very important parameter to be considered in the nonvolatile memory operations GATE VOLTAGE gnd poly Gate Dielectric QM Tunneling Electrons/Holes gnd N + N + P Substrate Fig. 2.1 Cross section of MOSFET showing the gate tunneling current

3 2.2 Gate Oxide Tunneling Phenomenon 27 Fig. 2.2 FN tunneling in a triangular oxide barrier which depend entirely on tunneling phenomenon. The FN tunneling current density is given by (2.1) [21]. J FN ¼ C FN E 2 ox exp β E ox (2.1) E ox is the electrical field in oxide, β ¼ 8πð2m ox Þ 1=2 φ 3=2 b =3qh C FN ¼ q 3 m o / 8πhm ox φ b (A/V 2 ). In FN tunneling, barrier lowering due to image forces is neglected. The effect of the insulator can be described by a single effective mass. The tunneling probability takes into account only the component of the electron momentum in the direction normal to the surface QMDT in a MOSFET In a case of the ultrathin oxide MOSFET, an electric field existing at the ultrathin gate oxide is so high that QMDT takes place which cannot be explained using the classical physics. This tunneling is more pronounced in thin oxides, e.g., 4 nm or less. The conduction takes place directly through the energy barrier of the oxide. Here the oxide conduction band potential is trapezoidal in nature which allows the direct tunneling of the electrons from the Si/SiO 2 interface to the gate of the MOSFET as shown in Fig QMDT in the gate oxide is a more complicated process as compared with the FN tunneling. The direct tunneling into the oxide can be modeled and estimated only using the phenomenon of quantum mechanical theory. This plays an essential role in several physical phenomena, such as gate oxide tunneling in MOSFETs. The net current in a gate oxide is the summation of the FN tunneling and the QMDT. Usually, the FN current is very small and can be neglected. So the net current contribution is from the QMDT only.

4 28 2 Nanoscale Effects: Gate Oxide Leakage Currents Fig. 2.3 Direct QMT in a trapezoidal oxide barrier 2.3 Impact of Gate Oxide Tunneling According to the tunneling theory, the width of the potential barrier is an important parameter determining the magnitude of the tunneling probability. In MOSFETs, the gate dielectric plays the role of a potential barrier separating the carriers in the channel from the gate. With a thick gate dielectric layer, the carriers cannot extend to the gate by penetrating the potential barrier. In the thin gate oxide regime, the QMDT will be exponentially increased, leading to significant power dissipation and device performance deterioration which is a primary concern for a scaled MOSFET. The gate oxide leakage can subsequently cause circuit failures because the designs assume that there is no appreciable gate current. The decrease in the channel current due to the oxide leakage results in low drain currents and hence the operation of circuits at low power is seriously hampered. The QMDT in the gate oxide is more harmful at the deep submicron and the nanometer MOSFETs where the inversion charge density is reduced due to the quantization of energy bands at the Si-SiO 2 interface as also explained in Chap Models for QMDT in Gate Oxides A lot of gate oxide QMDT models have been developed since the scaling of the gate oxide started in the early 1970s. In 1969, Lezlinger and Snow [22] showed FN tunneling current through the gate oxide. However, the inversion layer quantization was not included in the model developed. Rana et al. [23] modeled gate oxide current including accumulation layers self consistently. Lo et al. [24] studied tunneling current from MOS inversion layer also. Shih and others [25] have proposed two approaches for calculating QMDT. These are S-P solution and the other is the WKB. The QMDT currents calculated by these two distinct approaches have been compared with oxide thickness ranging from 1.5 to 4 nm. Their findings suggest that the WKB approximation is a viable approach for predicting the QMDT. A modified WKB approximation has been proposed by Register et al. [26]. It includes the wave

5 2.4 Models for QMDT in Gate Oxides 29 reflections from the interface potential into the basic WKB equations. Yang et al. [27] have presented a QMDT current model for ultrathin gate oxides without considering the effects of wave-function penetration in gate oxide. Ghetti et al. [28] have calculated gate oxide tunneling current through transmission probability using Schrödinger s equation. Vogel et al. [29] modeled the tunneling currents for insulators with an effective oxide thickness of 2.0 nm using a numerical calculation of the WKB tunneling current. Mudanai et al. [30] computed the QMDT current for different gate dielectrics by numerically solving Schrödinger s equation including wave-function penetration into the gate dielectric stack. Lee [31], reports an analytical model of the QMDT current in ultrathin gate nitrided oxide MOSFETs. Shiu and Jeng [32] present a model for the gate oxide tunnel current by considering the QME using a WKB approximation for the transmission probability. Liu et al. [33] present a direct tunneling current model for the ultrathin gate dielectric MOS structure. The tunneling current is modeled by including the inversion layer quantization effect and the modified WKB method for calculating the transmission probability. Cassan et al. [34] present the QMDT current through ultrathin gate oxide of a MOSFET using the semiclassical approximation. Grgec et al. [35] report a model for the evaluation of tunnel currents in MOS structure for Monte Carlo (MC) device simulation. Cassan [36] presents the QMDT current through the 1.5 nm gate oxide layer in n-channel MOSFET using the semiclassical approximation of electron transport. Kajer et al. [37] determine QMDT leakage current in a 25 nm channel length n-channel MOSFET using an ensemble full-band MC simulation incorporating quantum effects using Schrödinger s equation. Kajer et al. [38] also present a full-band MC model that has been coupled to a Schrödinger equation solver to predict direct tunneling gate currents in a 50 nm gate length. Jin et al. [39] present a physics-based gate current model based on nonequilibrium electron energy distributions obtained from the spherical harmonic expansion of the Boltzmann equation. There are various other QMDT models have been developed using numeric methods such as Bardeen s approach [40], the resonant transfer matrix method [41] and transparency-based approximations [42]. Choi and Dutton [43] studied in detail the models of gate oxide tunneling current for thin oxide MOSFETs and DG-SOIs based on quantum mechanical principles. There are some industry-standard models called compact models for the QMDT problem. Some of the compact models are described below: BSIM 4 Model The BSIM 4 includes gate tunneling current starting from version [44]. BSIM4 gate current model is based on the semiempirical model of Lee and Hu [13]. The tunneling carriers can be either electrons or holes, or both, either from the conduction band or valence band, depending on the type of the gate and the bias applied.

6 30 2 Nanoscale Effects: Gate Oxide Leakage Currents Philips MOS Model 11 Philips MOS Model 11 is based on the explicit formulation of the surface potential, defined as the electrostatic potential at the Si/SiO 2 interface with respect to the neutral bulk [45]. This approach is different from the threshold voltage based models like BSIM3 or Philips MOS 9 model that use separate expressions for the drain current in the weak-inversion and strong inversion regions, and the moderate inversion region is modeled through the use of smoothing functions. In Philips MOS Model 11 model, it is assumed that the QMDT current is a small perturbation, and thus the surface potential is not affected by it SP Model SP is a surface potential-based compact MOS model [12] and its gate current model is based on tunneling in channel area and overlap area HiSIM Model HiSIM is a compact model based on the drift-diffusion approximation for the drain current, and it describes analytically all the device characteristics by the surface potential at the source and drain sides of the MOSFET channel [17]. The gate current model in HiSIM considers four tunneling mechanisms, i.e., the gate to channel, gate to bulk, gate to source, and gate to drain [18] EKV Model The EKV model is bulk referenced compact model. It includes both FN and QMDT in its modeling equations [14]. 2.5 Analytical Modeling of QMDT: A Case Study In this section, an analytical modeling of QMDT using WKB method has been given. The case study has been taken for an analytical model of QMDT for electrons tunneling directly from the conduction band of the Si substrate to the poly-si gate electrode through the gate oxide barrier. The electron concentration at the surface of the Si/SiO 2 interface and the transmission probability needs to be

7 2.5 Analytical Modeling of QMDT: A Case Study 31 accurately determined to estimate the QMDT. The transmission probability for QMDT estimation is based on the solution of Schrödinger s equation at the Si/ SiO 2 interface and the poly-si gate/oxide interface under all the conditions of applied voltage. The WKB method is a standard model used for transmission probability determination; it is used in the calculations for the tunneling current density. More details are given in Appendix 1. In this case study, different components of QMDT current in a scaled n-channel MOSFET with ultrathin gate oxides have been evaluated. The effect of inversion layer quantization on the surface potential has also been included analytically in the overall approach WKB Approximation The tunneling current density can be found by WKB analysis by calculating the transmission probability P(E) of electrons in the SiO 2 is found under the given conditions of the Si/SiO 2 interface. From quantum mechanical theory of transmission, the general expression for the transmission probability is given by (2.2) as [46]: 0 PðEÞ ¼exp@ 2 ðx 2 x 1 jkðxþ 1 jdxa (2.2) kx ðþ¼wave factor is given by 2m oxðvx ð Þ EÞ h 2 x 1, x 2 are the limits of finding the transmission probability. m ox is the effective electron mass in the SiO 2. h ¼ Effective Planck s constant. Putting the value of k(x) in the (2.2), PðEÞ ¼exp 4π ð x 2 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 4 f2moxðvðxþ ExÞgdx5 (2.3) h x 1 The QMDT current density in the gate oxide [47] is given as (2.4) J T ¼ 4πmtq ðv h 3 0 ð1 0 ½ f S ðeþ f G ðeþšde t TE ð s ÞdE x (2.4) m t is effective transverse mass of electron at the interface of substrate and dielectric ¼ 0.19 m o,f S (E) is electron distribution at the substrate/dielectric interface, f G (E) is electron distribution at the poly-si gate/sio 2 interface, E is total energy of electrons is

8 32 2 Nanoscale Effects: Gate Oxide Leakage Currents JT (A/cm2) Gate Voltage (V) Fig. 2.4 QMDT electron current density at t ox {3.6 nm (blue line) to 1.5 nm (yellow line)} and V gs (0 2.5 V) at (N a ¼ cm 3 ) (Source [48]: Reprinted with permission) equaltoenergyinthetransversedirection(e t ) and in the direction parallel to the Si/SiO 2 (E x ), E s is the electron energy at the source and V ¼ q χ V gs V fb φ sqm =2Þg, χ is the electron affinity with any dielectric, φ sqm is surface potential in the substrate valid in all regions of inversion including shift due to inversion layer quantization as given by variation approach from 3.20) (For details, refer to Chap. 3). Using (2.5), the QMDT current density (J T ) can be evaluated [48]. J T ¼ 4π h 3 m qkt ð Þ 2 1 þ βkt 2 p exp V 8 < : qφ sqm qφ f E g 2 Δφ s kt 9 = ; exp ð βp VÞ (2.5) The parameter β in 4πt ox (2m ox ) 1/2 /h, V is the barrier height, k is the Boltzmann constant, T is the temperature, φ f is the fermi potential and E g is the substrate bandgap. The Fig. 2.4 shows that the QMDT current density increases with the increase in the gate voltage but becomes stable at some gate voltage, where strong inversion has taken place. This is due to the non increase of the surface potential after the strong inversion has taken place in the channel. The inverted surface potential does not allow the substrate voltage to increase at the surface and the rest of the increase in the gate voltage is absorbed as the depletion potential below the surface potential. The current density so obtained gives an idea of how much insulation the oxide gives at a particular gate voltage. The larger the QMDT current density, the smaller the insulation effect of the gate oxide. Simulated QMDT current density obtained from this analytical model [48] demonstrate good agreement with the results from measured and numerical results [49]. The gate oxides vary from thicknesses ranging between 1.5 and 3.6nm. The main observation is that

9 2.5 Analytical Modeling of QMDT: A Case Study 33 Fig. 2.5 Poly-Si gate depletion in a MOSFET the QMDT current density becomes very high as the gate oxide is scaled down. It is of the order of several amperes per cm 2 and becomes independent of the gate voltage at the oxide thickness of 1.5 nm or below in an n-channel MOSFET [48] Gate Oxide Tunneling with Depletion in the Poly-Si Gate The poly-si gates are used in nanometer MOSFETs instead of metal gates in order to minimize the work function difference in the MOSFET hence to reduce the flat band voltage and ultimately to reduce the threshold voltage. The poly-si gates have more or less the same properties as the crystalline Si and hence, similar work functions. By adjusting the doping concentration in the poly Si gates, the fermi potential in the gate can be adjusted and hence, the work function difference can be properly maintained as per choice. But as the gate voltage is applied, the potential drops across the poly-si gate also. This potential, called poly-si gate potential, causes the charge carriers in the gate to get depleted and exposing the donor or acceptor ions in the gate as the case may be. This causes depletion in the gate and this effect is called poly-si gate depletion effect as shown in Fig This potential hence, reduces the effective voltage in the SiO 2 and Si. The reduced voltage in the substrate causes less inversion and hence less charge and ultimately less drain current, which is a big cause of concern for the circuits. As far as gate tunneling density in poly-si gate MOSFETs is concerned, 1 The text/figures/equations/references, etc., associated with [48] have been republished/ reorganized from the paper [48], Amit Chaudhry and Jatindra Nath Roy, Analytical Modeling of Gate Oxide leakage Tunneling Current in a MOSFET: A Quantum Mechanical Study, Micronano-electronic Technology, Vol. 48, No. 6, pp , June, 2011 with due permission from the publisher.

10 34 2 Nanoscale Effects: Gate Oxide Leakage Currents JT A/cm Gate Voltage (V) Fig. 2.6 QMDT current density at gate voltage (0 2.5 V) and t ox {3.6 nm (blue line) to 1.5 nm (yellow line)} in case of poly-si gate depletion at (N a ¼ /cm 3 and N p ¼ /cm 3 )at m ox ¼ 0.61m o (Source [53]: Reprinted with permission) a huge reduction in QMDT current density is expected in poly-si gates as the effective oxide thickness is increased [53]. 2 One of the major tasks of determining the QMDT current density in poly-si gates is the accurate and analytical model of the potential which gets dropped in the poly-si gate. Various models [50 52] have already been reported to estimate the poly-si gate depletion potential but most of them are either empirical or too complex in nature. One of the widely acceptable models also used in SPICE model BSIM 4 is given here. h V p ¼ 0:25 γ p þ γ 2 i 1 2 p þ 4V gs V fb φ 2 (2.6) s γ p is the ð2qε o ε si N p Þ 1=2 =C ox. When the poly-si gate depletion effect is accounted for, the potential drop on the gate oxide layer is reduced. For this reason, the tunneling current density in the poly-si gate is less when poly depletion is taken into account. This can be found easily for the various values of V p and hence the tunneling current density is altered by putting V ox ¼ V gs V fb φ sqm V p in the barrier height V ¼ qχ qv ox /2 in (2.5) as shown in Fig The text/figures/equations/references, etc., associated with [53] have been republished/ reorganized from the paper [53] Amit Chaudhry and Jatinder Nath Roy, Gate Oxide Leakage in Poly-depleted Nanoscale-MOSFET: A Quantum Mechanical Study, International Journal of Nanoelectronics and Materials, Vol. 4, No. 2, pp , 2011 with due permission from the publisher.

11 2.6 Impact of Other Parameters on QMDT Current Density Impact of Other Parameters on QMDT Current Density There are several parameters which have an effect on the QMDT current density as the MOSFET is scaled down to the nanometer scale. These are described below: Tunneling in Germanium (Ge) MOSFETs As the MOSFETs are scaled down to nanometer levels, the Si substrates have been replaced with the Ge or s-si substrates due to the high carrier mobility. The gate oxide QMT also takes place in such alternate material MOSFETs. Further details are given in Chap. 5 of this book Impact of Gate Length Effect (Fringing Field Effect) on Gate Oxide QMDT Current Density Fringing field effect is the effect of electrical fields originating from the substrate to poly-si gate of the ultra scaled oxide MOSFETs. This field results in the additional depletion region at the gate edge [54]. This additional region needs to be included in the overall gate oxide tunneling modeling Impact of Image Force Barrier Lowering on QMDT Current Density The electrons as waves emit from semiconductor surface to oxide causes build up of image charge near the Si/SiO 2 interface during the inversion conditions. The potential associated with these charges reduces the effective barrier height of the carriers tunneling from the semiconductor to the gate oxide [55]. The barrier height lowering increases with an increasing external field applied across the oxide and doping level of the substrate. The reduction in the barrier height at the Si/SiO 2 interface is called image force induced barrier lowering effect thereby increasing the QMDT current density Tunneling Impact on the CMOS Circuits The impact of QMDT on the MOSFET device would ultimately affect the working of the CMOS circuits made up of the MOSFETs. The main effect is on the increased static power dissipation. Choi [56] studied in detail the impact of the tunneling

12 36 2 Nanoscale Effects: Gate Oxide Leakage Currents current in different CMOS circuits by applying the macro-circuit model, which relies on the extracted tunneling current data from the device simulation of a single MOSFET. The results obtained in the paper show enhanced delay and power dissipation in CMOS circuits. In another paper Chen and Ker [57] study the influence of QMDT current density on the circuit performance of phase locked loop (PLL) in nanoscale CMOS technology by simulation. The various PLL parameters are degraded by the QMDT current density in MOS devices used in the PLL. Arumi et al. [58] study QMDT current density impact on the behavior of the interconnects at nanoscale. Narasimhulu and Ramgopal [59] also report the effect of QMDT on device analog behavior with extremely scaled oxides for mixed signal circuits. The performance of current mirror circuits degraded due to the increased QMDT current density. So, the QMDT current density is not only an issue for the devices in scaled regions but also a significant factor to be determined at the circuit level too. 2.7 Tunneling in Multiple Gate MOSFETs The QMDT in multiple gate MOSFETs (MuGFETs) has also been studied extensively in the existing literature. Chaves et al. [60] present an explicit compact quantum model for the QMDT current density in a dual gate (DG) MOSFET. Darbandy et al. [61] report QMDT current density in a DG-MOSFET at 22 nm using WKB tunneling probability through gate oxide. 2.8 Conclusion In this chapter, a review of gate oxide scaling problems and models in MOSFETs has been done. The basic physics of gate tunneling current modeling were presented. It is concluded that to continue scaling in the nanometer scale, there is a strong need to curtail the QMDT and hence the static power dissipation.

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