Real Time CMOS Optical Processor for a Shack Hartmann Wavefront Sensor

Transcription

1 Real Time CMOS Optical Processor for a Shack Hartma Wavefrot Sesor Boo 1 Hea Pui a, Barrie Hayes-Gill a, Matt Clark b, Mike Somekh b, Chug See b, Steve Morga b, Ala Ng b a VLS Desig Group, School of Electrical ad Electroic Egieerig, Uiversity of Nottigham, Uiversity Park, Nottigham NG7 2RD, U. b Optical Egieerig Group, School of Electrical ad Electroic Egieerig, Uiversity of Nottigham, Uiversity Park, Nottigham NG7 2RD, U. Abstract A real time VLS optical cetroid processor has bee developed as part of a larger Shack-Hartma wavefrot sesor system for applicatios i adaptive optics. The implemetatio of the optical cetroid detectio system was demostrated successfully usig a hardware emulatio system. Subsequetly, the desig has bee implemeted as a CMOS sigle-chip solutio. This has advatages i terms of power cosumptio, system size ad cost. The desig of the differet compoets of the system will be discussed alog with test results of the fabricated device. eywords Special ssue Sesors 2002, cetroid detectio, wavefrot sesor, photodiodes, active pixel, FPGA, CMOS C, itegrated detector NTRODUCTON For imagig or video applicatios, CCDs (charge-coupled devices) are the preferred techology because of their highquality images [1]. However, for machie visio or sesor applicatios where the output does ot cosist of images but of extracted, iterpreted data, CMOS offers the advatages of radom access to pixel regios of iterest, low power dissipatio ad high level of itegratio. This additioal itegratio provides o chip local processig thus allowig ehaced performace ad a reductio i overall system cost. Our iteded applicatio is that of a itegrated CMOS Shack Hartma wavefrot sesor for a adaptive optical system. APPLCATONS AND WOR DONE Aberratio caused by the turbulece i the atmosphere ca degrade the imagig property of the light beig detected by distortig the icomig wavefrot. A Shack-Hartma wavefrot sesor [2] uses a array of small leslets to sample the optical wavefrot (Figure 1). Local wavefrot tilts are measured by detectig the deviatio of the focussed spots from referece positios. Traditioal systems use a sigle CCD to sample the etire wavefrot resultig i a data bottleeck. our system, each local wavefrot tilt is measured by a local tilt sesor with its ow detector array ad local cetroid processig. The array of tilt sesors will be liked to a matrix processor to recostruct the estimate of the complete wavefrot. Oce calculated, the reduced badwidth wavefrot data ca the be trasferred off-chip. Hece, parallel processig is achieved whereby the data rate is idepedet of the umber of tilt sesors employed. Light Source e.g. star turbulece Leslet array Plaar photodetector arrays Figure 1. A Shack Hartma wavefrot sesor Cetroidig Systems There are several types of optical frot-ed devices besides CCDs that ca be used i a cetroidig or positio sesig system, amely lateral-effect photodiodes (LEP) or positio sesitive detectors (PSD); quad cells or quadrat detectors; ad multi-pixel arrays. Covetioal LEPs have high liearity but require a very uiform resistive layer with large sheet resistace, which is ot geerally available with a stadard CMOS process. Quad cells have simple readout schemes but are ot very liear. They are desiged primarily for measurig small deviatios because the icidet beam must impige simultaeously o all four sectors of the detector. With sufficiet umber of pixels, 1 Correspodece: Boo Hea Pui; Other author iformatio: eexbhp@ottigham.ac.uk; telephoe: ; Fax: ; Supported by: The Uiversity of Nottigham Alumi Fud; Uiversity of Nottigham teratioal Office; Uiversity of Nottigham i Malaysia; ad Egieerig ad Physical Scieces Research Coucil, Swido, U.

2 multi-pixel array systems have very high liearity ad good sub-pixel accuracy but require complex readout ad processig schemes. From a processig poit of view, there are several methods of computig the cetroid of a light spot. Most LEP systems [3] have the processig performed off-chip because the LEP itself is ot fabricated o a stadard CMOS process, ad because of its simplicity, the processig teds to be implemeted i aalogue. Computatio of quad cell systems [4] is also usually performed i aalogue. Most multi-pixel array systems [5,6,7,8] use a aalogue curret dividig method to fid the cetroid which require the use of a liear resistive or capacitive array. Usig aalogue cetroid computatio offers the advatage of high speed ad high fuctioal desity. However, they suffer from mismatch ad poor tolerace of the polysilico resistors or capacitors i the divider lie. Also, as CMOS techology scales, the advatages of speed ad fuctioal desity of aalogue over digital dimiishes. A geeric 256 x 256 pixel array system with a o-chip image processor has bee desiged which performs several commo imageprocessig algorithms icludig cetroidig [9]. However, i a adaptive optics system such as the Shack Hartma wavefrot sesor, a large umber of tilt sesors are required but the pixel cout of each tilt sesor ca be miimal. The desig, simulatio ad layout of a 5 x 5 tilt sesor for just such a system will be preseted i this paper. Hardware Emulatio System itially a hardware emulatio system [10] was desiged. This allowed us to test the optical processig ad system cotrol algorithms prior to CMOS foudry fabricatio. The system cosisted of a 5 x 5 photodetector array, multiplexers, a curret-to-voltage coverter, a sigle chael 16-bit aalogue-to-digital coverter (ADC), a Field Programmable Gate Array (FPGA) for cetroid computatio ad a RS232 serial iterface for trasmittig cetroid data to a PC. The system was tested usig both a commercial photodiode array ad our ow full custom CMOS photodetector array. The cetroid is computed by multiplexig each photodiode output ito a curret-to-voltage coverter, which is the digitised by the ADC. The FPGA the computes the cetroid ad trasmits this i RS232 format to the PC. The samplig frequecy of the ADC was 40kHz ad a cetroid was successfully computed oce every 0.75ms. SYSTEM DESGN After the hardware emulator verified the performace ad fuctioality of the system, the desig was implemeted i a sigle CMOS C. A block diagram of the overall system is show i Figure 2. t cosists of a active pixel sesor array, the aalogue frot ed ad aalogue-to-digital coversio circuitry, the digital cetroid processor ad a serial lik for trasmittig ad receivig data off-chip. The idividual compoets of the system are discussed i more detail i the followig sectios. Referece voltage 1 Referece voltage 2 5x5 active pixel array Vref1 Vref2 Vout Referece voltage 1 select comp1 comp2 row/colum pixel reset 12 Referece voltage 2 select 12 ADC Aalogue frot-ed ad ADC 11 Digitised light Cetroid processor 7 x-cetroid 7 y-cetroid Sigle CMOS Chip Figure 2. Block diagram of optical cetroid detectio system O-chip CMOS Photodetectors ad tegratig Active Pixel Sesor (APS) Array Several prototype photodiodes were previously implemeted i a stadard 0.7µm N-well CMOS process [10] amely: the shallow (diffusio-substrate or diffusio-well) photodiodes; the deep (N-well to p-substrate) photodiode; ad the combied deep ad shallow (p+ to N-well) photodiode (Figure 3). The shallow photodiodes have better spectral respose at shorter wavelegths while deep photodiodes have better spectral respose at loger wavelegths. The respositivities of the photodiodes compare favourably with commercial photodiodes ad is of the order of 0.4 A/W. For the photodiode array, the deep N-well to p- substrate photodiode is used as it is foud to have a reverse bias curret that is miimally affected by the reverse bias voltage, ulike the shallow ad combied photodiodes (Figure 4). The -V characteristics of the deep photodiode i room light ad i the dark is show i Figure 5. A Active regio + P-substrate (a) Shallow + photodiode A Active regio + N-well P-substrate (b) Deep N-well photodiode A N-well P-substrate Active regios + RS232 (c) Combied shallow ad deep photodiodes Serial output

3 Figure 3. Three differet photodiode cofiguratios implemeted i a stadard 0.7µm CMOS process 3.00E E-08 level varies with light itesity. The layout of this circuit is show i Figure 6(b). Circuitry other tha the photodetector is light shielded usig oe of the two available metal layers but is ot show i Figure 6(b). 2.00E E-08 Curret (A) 1.00E E-09 shallow deep combied 0.00E E E E E-08 Voltage (V) Figure 4. -V plots of deep, shallow ad combied 100µm x 100µm photodiodes i room light 2.00E E E E-08 (a) Active pixel circuit -2.00E-08 Curret (A) -3.00E E-08 room dark -5.00E E E E-08 Voltage(V) (a) room light ad i dark 4.00E E E E-13 Cu -4.00E-13 rre t (A ) -6.00E E E E E-12 Voltage (V) (b) Close up of dark curret Figure 5. -V plots of deep photodiodes i room light ad i dark A 5 by 5 photodiode array is used with each pixel havig a size of 100µm x 100µm. For each pixel, a itegratig active pixel structure is employed ad is show i Figure 6(a). This cosists of a sigle -well/p-substrate photodiode, a complemetary NMOS/PMOS reset gate, a source follower ad row-colum select trasistors. All pixels are reset globally ad the iverter output ad the bias trasistor () are shared with all pixels. Havig a CMOS trasmissio gate allows the pixel to be pulled up to 5V durig reset. This elimiates the problem obtaied with usig oly a NMOS reset trasistor whereby the reset (b) Layout of active pixel Figure 6. Active pixel circuit ad its layout Each pixel is globally reset to 5V for 8µs (with a 32MHz clock) after which the pixel photodiode is allowed to discharge through its ow photocurret (Figure 7). The discharge rate is proportioal to the photocurret of that pixel, which i tur is proportioal to its icidet light level. The discharge curve is approximately liear for voltages above 1V. This is because the photodiode capacitace varies iversely with the square root of the diode voltage. Also, as the diode ad the pixel output voltage drops the bias trasistor starts to operate i the liear regio ad is o loger idepedet of the output voltage. By measurig the time take for the voltage to drop to a particular voltage level i the liear regio, a readig proportioal to the coverted light level is obtaied. The discharge time is measured by startig a 8-bit couter whe it passes through a iitial voltage level ad stoppig it whe it

4 passes a secod lower voltage level. These voltage levels are set by referece voltage geerators. A programmable discharge clock is used such that for differet discharge rates or itesity levels, optimum resolutio ca be maitaied. Four programmable discharge clock frequecies are possible, which are iterally selected by two mode registers. The states of which ca be read via the o-chip RS232 receiver ratios of MACT, MRSEL, MCSEL improves the DC voltage gai ad liearity of the trasfer fuctio. The selected W/L ratios of the trasistors are show i Figure 8. Vout (V) V 0.6V 1.0V 1.4V Voltage (V) Time (us) Figure 7. The discharge curve of the active pixel circuit used The backed of the active pixel sesor i Figure 6(a) acts as a source follower buffer for the photodiode ode (Figure 8). t cosists of the source follower active trasistor (MACT), a row select trasistor (MRSEL), a colum select trasistor (MCSEL) ad a bias trasistor () shared by all pixels. Figure 8. Backed of the active pixel sesor Simulatio ad Circuit Aalysis To optimize the desig of the backed, simulatios were carried out to fid the optimum W/L of the trasistors ad biasig voltage. The gates of the row-colum access trasistors were held at VDD i.e. 5V. The results showed that as Vbias or the W/L ratio of is icreased, the dyamic rage is reduced ad the respose becomes more o-liear. Figure 9 shows the trasfer fuctios obtaied as Vbias is swept. A optimum bias voltage of 1V was selected to keep the biasig trasistor operatig above the threshold voltage of 0.76V but sufficietly small so as to maitai a wide liear operatig rage. For further optimisatio after fabricatio, the applied voltage of the bias trasistor of the active pixel array ca also be applied exterally. Simulatios also showed that icreasig the W/L actg acts VOUT Vi (V) Figure 9. VOUT agaist Vi for differet values of Vbias (W/L = 3µm/3µm) First order circuit aalysis of the circuit produces a output voltage give by:- Vout= ViV TMACT MACT ( Vbias VT ) 2 MRSEL 2 ( Vbias VT ) ( VDDVrow V ) TMRSEL 2 MCSEL 2 ( Vbias VT ) ( VDDVout V ) Furthermore, it shows that for small output voltages, as Vbias icreases the o-liearity icreases due to the last three terms i the above equatio. Aalogue Frot Ed ad ADC The aalogue frot-ed ad ADC (show dotted o the left had side of Figure 2) cosists of the active pixel array, 2 sets of referece voltage geerators, 2 comparators with its biasig ad the aalogue-to-digital coversio circuitry, which icludes row-colum decoders ad couters. Each set of referece voltage geerators ca geerate a voltage betwee 1V ad 3.75V with a step size of 0.25V ad each coects to a comparator iput. Six levels of oe of these referece geerators are show i Figure 10. The referece voltage geerator cosists of a set of voltage dividers implemeted usig active resistors ad trasmissio gates for selectig the desired voltage. These trasmissio gates are used to select the switchig poits of the comparators durig aalogue-to-digital coversio. Usig a series chai of active resistors istead of a sigle active resistor reduces the area required. TMCSEL

5 C(x) = r x ; C(y) = r y ; where r x is the displacemet i the x-directio r y is the displacemet i the y-directio is the light (curret) level of each photodetector The processor also determies the maximum light level ad the positio of the pixel with the maximum light level (ot show i Figure 11). Digitised light level To y-co-ordiate processor x-co-ordiate processor clock Mod N 1/2 couter Multiplier Figure 10. Referece voltage geerator Adder Adder Whe reset is fired, oe referece voltage (Vref1) will be set at 3.75V while the secod referece voltage (Vref2) will be set at 3.5V. The the referece voltages are decreased util both referece voltages are below the pixelreset level. This is determied by whe the comparators switch over. order to cope with a wide rage of light levels, three modes of operatio have bee desiged. the first mode, the couter is started whe the reset is removed ad stopped whe the discharge curve passes the 1 st referece voltage. the secod mode, the couter is started whe the discharge curve passes the 1 st referece voltage ad stopped whe it passes the 2 d referece voltage. This has the advatage that if the reset level varies from pixel to pixel, the readig will be idepedet of this offset. the third mode, a 2-cycle approach is used. the 1 st cycle, a readig is obtaied as i mode 2. the 2 d cycle the value of Vref2 is adjusted such that a larger dyamic rage is obtaied thereby icreasig the resolutio for higher light levels. Digital Backed The digitized light level at each pixel is the fed ito the cetroid processor - previously demostrated with the FPGA hardware emulatio system [10]. The cetroid is foud from the calculatio of the first order momet of the itesity distributio of the array. This requires the multiplicatio of the itesity of every pixel with the weightig of its positio. The summatio of which is divided by the overall sum of the itesities of every pixel to give the 7- bit x ad y cetroids (Figure 11). The cetroid of a array of photo-detectors is expressed i terms of its x ad y coordiates, C(x) ad C(y). The values of C(x) ad C(y) ad hece the cetroid of the array are foud from the 1 st momet equatios: Divider Output: 1 st momet of x Figure 11. Block diagram of cetroid processor i the x-directio These values are the trasmitted off-chip serially usig the RS-232 format. For testig purposes, the x-divided, y- divided, divisor ad the idividual pixel light level ca also be trasmitted off-chip. With this desig, a cetroid value is output oce every frame ad a frame lasts 26 pixel periods i.e. a frame rate of betwee 2.4kHz ad 4.8kHz depedig o the icidet light level of every pixel. This is a improvemet over the hardware emulatio system previously demostrated which could output cetroids at a rate of 1.3kHz. Usig a adjustable baud rate of up to bits/s, the trasmitted values will be observed i real-time. For observability, the reset of the pixels ad the row-colum addressig ca also be cotrolled exterally. CAD TOOLS, LAYOUT AND FABRCATON The CAD tools used were the Metor Graphics versio C4 tools ruig o Solaris 7 o a Su Ultra 60 Workstatio. The mixed aalogue ad digital CMOS 0.7µm libraries were provided by Alcatel Microelectroics (Mietec) via Europractice. The process was a double metal, sigle poly -well process with a gate desity of 1250/mm 2. Schematics were etered via Desig Architect. itially, "Accusim" is required to simulate the aalogue frot-ed. The models of trasistors, diodes ad the stadard cells were provided by Mietec. The the output sigals of the comparators are fed ito the digital circuitry for digital simulatio usig "QuickSim". The digital circuitry was sythesised from VHDL code ito Mietec digital compoets usig "Leoardo Spectrum". Static timig aalysis iclud-

6 ig delay path aalysis ad slack aalysis was carried out usig "QuickPath". Fially, whe the desig had bee thoroughly simulated ad its performace verified the layout was implemeted usig C statio (Figure 12). The chip cotaied 7200 logic gates ad has a size of 4500µm x 4000µm. This will scale favourably as techology scales ad as we move towards a triple metal process with improved routig capabilities. Also, because the divisio process is performed oly oce every frame, the divider, which makes up a sigificat amout of the processig, ca be shared with several arrays without icrease i size or loss of speed. y x-cetroid Figure 13. mage map of x-cetroids x Measured Figure 12. Layout of the tilt sesor EXPERMENTAL RESULTS A 3µm diameter beam from a 633m HeNe laser was scaed across the array at a speed of 2000µm/sec. Cetroid values were computed by the processor ad serially trasmitted i real time to a PC. The maximum rate of geeratio of these cetroid values was foud to be 4.8kHz. Figures 13 ad 15 show grey scale maps of the x ad y-cetroid values successfully recorded at each positio o the array. The dark regios correspod to smaller cetroid coordiates whilst lighter regios correspod to larger cetroid coordiates. As expected, as we sca i the x-directio, the x-cetroid values icreases while the y- cetroid values remai costat ad vice versa. Sice the laser beam size is less tha the size of oe pixel, a stepped appearace ca be see as the beam moves across the array passig from oe discrete detector to aother. Figures 14 ad 16 show the x ad y-cetroid values plotted as a fuctio of pixel positio Actual positio Figure 14. Measured vs. actual positio of x-cetroids y y-cetroid Figure 15. mage map of y-cetroids x

7 Measured Actual positio Figure 16. Measured vs. actual positio of y-cetroids CONCLUSONS A real time VLS optical cetroid processor was successfully desiged ad fabricated for itegratio ito a proposed Shack-Hartma wavefrot sesor. The chip cosists of a optimised 5 x 5 active pixel array ad aalogueto-digital coversio circuitry itegrated with the cetroid processor previously demostrated usig a hardware emulatio system. Cetroid values ca be outputted at a rate of more tha 2.4kHz allowig real time performace of the adaptive optical system. ACNOWLEDGMENTS The authors are grateful for the fiacial support of the Uiversity of Nottigham, Uiversity of Nottigham teratioal Office, Uiversity of Nottigham i Malaysia ad the Egieerig ad Physical Scieces Research Coucil (EPSRC), U. REFERENCES [1] Nico Ricquier, Bart Dierickx, Radom addressable CMOS image sesor for idustrial applicatios, Sesors ad Actuators A (44), Jauary [2] Robert Tyso. Priciples of adaptive optics. Academic Press, SBN: [3] Richard M. Turer ad ristia M. Johso, CMOS Photodetectors for Correlatio Peak Locatio, EEE Photoics Techology Letters, vol. 6, pp , April [4] D W de Lima Moteiro, G Vdovi ad P M Sarro, "tegratio of a Hartma-Shack wavefrot sesor", Proceedigs of 2d teratioal Workshop o Adaptive Optics for dustry ad Medicie, pages , World Scietific, [5] Stephe P. Deweerth, Aalogue VLS Circuits for Stimulus Localizatio ad Cetroid Computatio, teratioal Joural of Computer Visio, 8:2, pp , [6] David L. Stadley, A Object Positio ad Orietatio C with Embedded mager, EEE Joural of Solid-State Circuits, vol. 26, pp , December [7] W. R. Goaso, J. W. Haslett, F. N. Trofimekoff, A Low Cost High Resolutio Optical Positio Sesor, EEE Trasactios o strumetatio ad Measuremet, vol. 39, pp , August [8] B. Pai, E Su ad G Yag, CMOS APS With tegrated Cetroid Computatio Circuits, NASA Techical Brief, JPL New Techology Report NPO-20715, vol. 24, No. 9, September [9] R. Forcheimer,. Che, C. Svesso, A. Odmark, Sigle Chip mage Sesors With a Digital Processor Array Joural of VLS Sigal Processig, 5, pp , 1993, luwer Academic Publishers. [10]Boo Hea Pui, Barrie Hayes-Gill, Matt Clark, Mike Somekh, Chug See, Steve Morga, Ala Ng, "The desig ad characterisatio of a optical VLS processor for real time cetroid detectio", Proceedigs of SPE - The teratioal Society for Optical Egieerig, vol. 4408, p 73-80, SBN: