A review of the challenges and development of. the electronics industry

Transcription

1 SMTA LA/OC Expo, Long Beach, CA, USA A review of the challenges and development of SMT Wave and Rework assembly processes in SMT, the electronics industry Jasbir Bath, Consulting Engineer Christopher Associates Inc./ Koki Solder Jasbir@christopherweb.com www christopherweb com Lead Free SOLUTIONS you can TRUST Challenging New Technologies

2 Agenda Introduction SMT Wave Rework Test Conclusions Future Work

3 Introduction 3 The electronics assembly industry has been migrating from PTH to SMT over a number of years. This migration has seen a number of new components and technologies faced by the industry. The presentation will review the various new components and assembly challenges faced.

4 SMT Component Trends Move to miniaturization and System In Package type components Large System in Package components QFN/MLF/BTC components CSP/BGA components Chip components

5 Large System in Package components Increase in use of System in Package (SIP) components: Stacked Die in Package Stacked Package on Package (PoP) Modules Large BGAs/SIP sizes: 35mm to 55mm PoP 3000 to 3500 I/O with 0.8mm to 1mm pitch

6 Issues with large component sizes (SiP, PoP) Solder paste printing issues Component placement issues Coplanarity issues of component and board during assembly Potential for warpage of part during reflow (Head-in-Pillow defect) Issues during area array rework (high component temperatures, warpage during rework)

7 Warpage related to PoP assembly 7 Component warpage during the reflow process can lead to solder joint opens. More problematic with PoP components where each package is made thinner to minimize overall height, making it more vulnerable to warpage. Once solder bumps of PoP component separate from board pad land, even if they are in contact again, open solder joint failures result due to depleted tacky flux performance during reflow. Ref: J. Bath et. al, (Christopher/Koki) SMTAI Conference, 2010.

8 Reflow Issues Related to Package on Package (PoP) Components Work needed to improve assembly yields: warpage of the part during reflow Tacky flux versus Low viscosity solder paste for package attachment during reflow Tacky flux: Would the solder joint reliability be acceptable and potential for warpage Solder paste: Would solder bridging be an issue during assembly

9 Affect on Powder Size on solder paste transfer for PoP components Tests with Type 4 (20-38um) solder powder size versus 10-25um versus 5-20um for PoP showed the best results with 5-20um in terms of good paste transfer. Good paste amount deposited helped reduce head-in-pillow component soldering issues. 9 Ref: J. Bath et. al, (Christopher/Koki), SMTAI Conference, 2010.

10 Issues Related to Assembly of QFN/MLF/BTC (Micro Lead-Frame) Components Non-standard designs from component suppliers Refer to IPC 7093 standard for general guidelines: Design and Assembly Guidelines for BTC/MLF/QFN components Need to optimize solder paste volumes to use: Large center pad (voiding) Center Pad Via Plugging: Optimize i to reduce Voiding Soldering to edge of QFN/MLF which would have oxidized copper: decide on need to rework Low QFN/MLF standoff height (flux entrapment/ unactivated flux) Inspection difficulties for multiple rows of this component type

11 Issues Related to Rework of QFN/MLF/BTC (Micro- Lead-Frame) Components Potential high temperature component related issues Not very well standardized rework techniques (area array, hand soldering) Decide on use of solder paste or tacky flux during QFN rework and dhow to apply it.

12 QFN/BTC/MLF Reflow problems (Voiding) Develop suitable solder paste reflow profile to reduce voiding Assessment of solder paste to use. Solderability/ void exit issues under QFN/MLF component Voiding categories: Greater than 25% voiding termed a defect (IPC 610 standard) At what % over 25% will there be ATC or mechanical reliability issues. Potential void issues in terms of electrical/ thermal requirements for QFN/MLF what void % is an issue

13 Development of solder paste helps to reduce voiding in QFN/BTC/MLF. Tests on different board surface finishes on power transistor component showing different levels of voiding %. 13 Improved Lead-free Paste C OSP Sn NiAu HASL (SAC305) 2.55% 3.6% 5.4% 4.6% Conventional Lead-free Paste D OSP Sn NiAu HASL (SAC305) 25.2% 35.0% 17.5% 17.4% Ref: J.Bath et al. (Christopher Associates/ Koki Solder) SMTAI 2010

14 Development of solder paste to reduce voiding under QFN/MLF/BTC component 14 Improved wetting property for Lead-free Paste C extends duration of fluid/active state of the flux: Model: behav ior of v oids during reflow process Helps to push out more of the entrapped gas Remov al of oxidized f ilm & f low of flux prompt bubbles to ev acuate. Enables component to come closer to board pad, lowering component solder joint standoff height. New additiv e with good wetting properties pulls the component and helps to push out the bubbles. REF: J.Bath et al. (Christopher Associates. Koki solder) SMTAI 2010

15 Assembly with CSP/WL-CSP Components Reduction in CSP pitch: From 0.5mm to 0.4mm to 0.3mm Need to understand reliability implications for low volume solder joints such as 0.3mm pitch CSP Low profile CSP part (Potential flux activation issues) Solder Joint Voiding Warpage of part (Head in Pillow defect) Solder paste volume deposited and solder powder size used (Type 4 or 5 particle size paste for 0.3mm CSP versus Type 3 paste for coarser pitch components) Board Pad and Stencil design guideline recommendations

16 Assembly of Chip Components From 0402 to 0201 to chip components Board pad design considerations Stencil design (stencil thickness and aperture) Paste volume deposited and solder paste powder size used (Type 4 or 5 powder size paste for chip components) Placement accuracy of chip components Offset component placement in certain equipment dependent on paste location to board pad location Reflow behaviour Reworkability More challenges as movement is made from 0402 to 0201 to 01005

17 Board Pad and Stencil Design Guidelines for existing and emerging components Board Pad Design First step to optimize: Pad designs based on IPC design standards d (IPC 7351) or OEM/EMS guideline Understand how board pad designs were developed: Were they based on company evaluations or manufacturing yield data. Stencil aperture design Dependant on board pad designs and components used Refer to IPC stencil standards (IPC 7525) or OEM/EMS guidelines Understand how stencil aperture designs were developed Understand d stencil area ratios and aspect ratios for effective solder paste printing

18 SMT Solder Paste Printing As component sizes become smaller with smaller pad sizes, stencil area ratios guidelines are being challenged (Printing challenges when area ratios are < 0.66 and aspect ratios < 1.5). For a mix of large and small components on same board, more challenge to print large & small paste deposits on the board. 18 Courtesy: DEK Printing Machines

19 SMT Printing 19 Other solutions are being developed such as DEK Active Squeegee to print solder paste on a board with a mix of coarse and very fine pitch components (01005, 0.3mm CSP) [e.g. mobile phone type applications). Courtesy: DEK Printing Machines

20 Paste Inspection Equipment As more focus is placed on printing large and small paste deposits on same board in addition to ensuring printing accuracy and deposition, more use of paste inspection equipment. Use of 2D or 3D paste inspection increasing (move towards 3D paste inspection). Used for prototype builds and manufacturing. More emphasis needed on use of paste inspection not just to filter out some low solder paste print deposited boards but as a way to improve process yield.

21 Use of AOI (Automated Optical Inspection) and X-ray equipment AOI equipment considerations: AOI use after component placement (for high volume production) AOI use after reflow (for initial Prototype/NPI) X-ray equipment applications: Voiding detection in BGA/CSP and QFN/MLF/BTC components Holefill analysis for wave soldered TH components

22 Trend for Increased SMT Usage vs Wave Soldering with Paste-in-hole soldering More paste in hole processes mainly for consumer type products where board thickness is less than 63mil Greater than 63 mils more paste needed for good holefill with use of solder preforms but process window becomes more challenging to get good holefill Need to ensure paste in hole reflow soldered components are higher temperature rated for reflow versus wave soldering Need to ensure paste in hole soldered components can be reworked at lead-free reflow soldering temperatures Developments ongoing indicating that Paste in Hole can be used for thicker boards for assembly and rework [Ref: G.Subbarayan et. al: IPC APEX 2011, SMTAI 2011]

23 Lead-free SMT Alloys and Reflow Profiles used SMT solder pastes: Mainly Sn3-4Ag0.5Cu Some Sn1Ag0.5Cu and Sn0.7Cu based alloys Reflow Profiles: Tin-Lead: Time over 183ºC: sec, Peak: ºC Lead-free (Sn3-4Ag0.5Cu): Time over 217ºC: sec, Peak: ºC Lead-free Low silver alloys (Sn0.3Ag0.7Cu): Time over 227ºC: 30-90sec, Peak: 240C-270ºC

24 Issues transitioning to Low Silver Alloys for SMT Higher melting temperature SnAgCu alloys Sn3-4Ag0.5Cu (MP: 217ºC) Sn1Ag0.5Cu (MP:225ºC) to Sn0.7Cu (MP: 227ºC) Increased soldering temperatures, more likelihood of component and boardtemperature issues Need for updated component rating standards for Low Ag solder pastes [IPC/JEDEC J STD 020 standard] d]

25 Current Lead-free Alloys used and Issues Transitioning to Low Ag alloys for Wave Wave Alloys: Sn3-4Ag0.5Cu and Sn0.7Cu based alloys Increased solder usage in Wave machines versus SMT with more SnCu based lead-free wave alloys used due to cost Sn0.7CuNi, Sn0.7CuAg and Sn0.7CuAgNi (JEITA) alloys Lower Ag amount, lower cost: MP 227ºC vs Sn3-4Ag0.5Cu MP 217ºC JEITA alloys: Sn1Ag0.7Cu, Sn0.3Ag0.7Cu, Sn0.3Ag0.7Cu0.03Ni Sn0.7Cu based alloys Thicker boards: Higher pot temperatures- potential component and board issues and reduced wave holefill.

26 Wave Flux, Flux Spray Assessment and Wave Preheat Wave fluxes Trend to move to no-clean alcohol based wave fluxes for good holefill on thicker boards for lead-free Flux spray coverage assessment on board Flux Coverage/Board Penetration ti Assessment Good flux penetration Even spray pattern across surface assessed using flux paper Wave Board Preheat Important to consider amount of heat transfer into board Pre-heater: Pre-heater settings for optimized flux activation with more top-side preheat for better solder holefill

27 Example of Lead-free Wave Soldering Evaluation DCC RJ-45, USB CAP CAP 125 mils (3.2mm) thick board 18 layers, 11 oz total copper OSP Board surface finish (High temperature rated) Component types- Radial caps, LEDs, RJ45, USB & DCC Board size- 16 inch x 11inch High Tg FR4 laminate (175 C) 270 C solder pot temperature with Sn3Ag0.5Cu solder Ref: S. Gopalkumar et al. (Brocade, Foxconn and BTC), SMTAI 2010

28 Flux Screening Evaluation Results- 2D X-ray 1 (Signal) 50%~75% 2 (GND) 25%~50% 1 (Signal) >75% 2 (GND) 25%~50% 1 (GND) >75% 2 (Signal) >75% 1 (Signal) 25%~50% 2 (Signal) 25%~50% C46 C126 CR6 CR15 1 (Signal) >75% 1 (No Connect) >75% 2 (No Connect) >75% 3 (Signal) >75% 4 (Signal) >75% 5 (Signal) >75% 6 (Signal) >75% 7 (No Connect) >75% 8 (no Connect) >75% 9 G >75% 10 G >75% 1 (Signal) >75% 2 (Signal) >75% 3 (Signal) >75% 4 (Signal) >75% 5 (Signal) >75% 6 (Signal) >75% 7 (Signal) >75% 8 (Signal) >75% 9 (Signal) >75% 10 (GND) >75% 11 G >75% 12 G >75% 13 (Signal) 0%~25% 14 (Signal) >75% 15 (Signal) >75% 16 (Signal) >75% 2 (Signal) >75% 3 (Signal) >75% 4 (Signal) >75% 5 (Signal) >75% 6 (Signal) >75% 7 (Signal) >75% 8 (Signal) >75% 9 (Signal) >75% 10 (GND) >75% 11 G 25%~50% 12 G >75% 13 (Signal) >75% 14 (Signal) >75% 15 (Signal) >75% 16 (Signal) >75% 1 (Signal) >75% 2 (Signal) >75% 3 (Signal) >75% 4 (GND) >75% 5 (No Connect) 50%~75% 6 (No Connect) 50%~75% J12 J25 J27 J39 1 (P48V_RTN) 50%~75% 2 (P48V_DCC_ON) >75% 3 (P48V_RTN) >75% 4 (GND) >75% 5 (P12V_CP) >75% 1 (GND) 50%~75% 2 (Signal) >75% 3 (Signal) >75% 1 (Signal) >75% 2 (GND) 50%~75% 3 (Signal) >75% 4 (Signal) >75% 4 (GND) 50%~75% U32_1 U32_2 U109 U181 Incomplete wave solder barrel fill across most components on the pins connected to ground planes Ref: S. Gopalkumar et al. (Brocade, Foxconn and BTC), SMTAI Brocade Communications Systems, Inc. CONFIDENTIAL For Internal Use Only 11/2/

29 Results of Lead-free Wave Process Optimization Flux optimization Board redesign Preheat optimization Improved holefill with combination of above factors especially board redesign Ref: S. Gopalkumar et al.(brocade, Foxconn and BTC),SMTAI Brocade Communications Systems, Inc. 11/2/

30 Lead-free Wave Soldering Confirmation Run Results Cross-section results showed good barrel fill with no significant copper dissolution (Cu thickness>0.5 mils [12 um]) 44 m 56 m DCC 40 m 39 m 40 m 50 m Ref: S. Gopalkumar et al.(brocade, Foxconn and BTC),SMTAI Brocade Communications Systems, Inc. CONFIDENTIAL 11/2/

31 Current Rework Alloys and Issues Transitioning to Low Ag Lead-free Rework Alloys Rework Alloys: Sn3-4Ag0.5Cu, Sn3.5Ag, Sn0.7Cu based alloys Hand soldering: Sn0.7Cu based alloys (lower cost) Potentially higher soldering iron tip temperatures especially for thicker more thermally demanding board BGA/CSP rework Sn0.7Cu based alloys (lower cost) Higher board and component temperatures Mini-pot/solder fountain: Good holefill/ low copper dissolution Sn0.7Cu+Ni Sn0.7Cu0.3Ag0.03Ni(JEITA alloy) Higher board and component temperatures

32 Rework Flux Trends Hand-soldering Tacky flux versus liquid flux versus cored wire General trend to cored wire or tacky flux Hand soldering heat activation questions with use of liquid flux and tacky flux BGA/CSP rework Solder paste (typically for larger BGA) or tacky flux (CSP) Mini-pot/ solder fountain Liquid flux or tacky flux

33 Example of Lead-free Wave Rework Evaluation 125 mils (3.2mm) thick board, 18 layers, 11 oz total copper OSP Board surface finish (High temperature rated) Component types used for rework- RJ45, LED & DCC RJ45 connector and LED connector low/medium complexity DCC component high complexity Board size- 16 inch x 11inch, High Tg FR4 laminate (175ºC) 1 st pass wave soldering with Sn3Ag0.5Cu using wave pot temperature of 270ºC. Rework with Sn0.7Cu0.05Ni alloy with solder fountain pot temperature of 270ºC. Ref: S. Gopalkumar et al. (Brocade, Foxconn and BTC), SMTAI 2011

34 Effect of Reduced Preheat Temperature on Holefill during Lead-free PTH Rework Reduction of topside board temperature below 80ºC on DCC component resulted in reduced hole fill (40%) for component that did not meet IPC610 standard requirements. Ref: S. Gopalkumar et al. (Brocade, Foxconn and BTC), SMTAI

35 DCC Component Lead-free Wave Rework Results with increased topside board preheat 35 X-ray image and cross-section of reworked DCC component showing good holefill (100%) and minimum copper knee barrel thickness of 18um (>12 um criteria). Increased topside board preheat (>80ºC) Ref: S. Gopalkumar et al. (Brocade, Foxconn and BTC), SMTAI 2011

36 Affect of Lead-free and Tin-Lead Soldering on In- Circuit Test (ICT) Potential issues with probing of lead-free no-clean flux residue Chisel versus crown probe tips: Chisel tips have better flux residue probing Limits on amount of probe force used Air versus Nitrogen reflow atmosphere: Nitrogen atmosphere may make flux residue more probeable Time after assembly before ICT probe testing: Flux residue hardening over time

37 Affect of Lead-free and Tin-Lead on Board Surface Finish during In-Circuit Test (ICT) Potential issues with board surface finishes used (e.g. OSP, Sn) Lead-free paste spread during reflow on OSP test pads and vias (Non-uniform solder spreading affecting ICT probing) Unprinted test vias: exposed/oxidized OSP pads affecting ICT probing. Aged tin coated board surface finish (board surface finish consumed as Copper-Tin Intermetallic compound) Difficult to solder to and rework and potentially difficult to probe test vias and test pads

38 Conclusions With the movement from Wave to SMT and increasing component miniaturization, many new components are emerging which need to be assembled. PoP component assembly requires optimized print, placement and reflow processes and optimized soldering materials in assembly. QFN/BTC/MLF components need more optimization of solder paste volume deposited d and soldering materials to reduce voiding in addition to more standardized component designs and rework processes. Fine pitch CSP (0.3mm) and chip components need developments in paste printing techniques and stencil designs. Board pad and stencil design play a critical role in successful assembly of these component types. 38

39 Conclusions (cont.) For lead-free wave soldering, optimization needed for board preheat, flux spray coverage and board design for good holefill on thicker boards. For lead-free wave rework soldering, board preheat and leadfree alloy optimization are needed for good holefill and reduced copper knee dissolution. 39 Work on component board design, stencil apertures, solder materials, printer, placement, reflow, wave, rework and inspection/ test equipment all pay a role in successful assembly.