ORDERING INFORMATION Figure 1. Pinout: 20 Lead Packages Conductors (Top View) PIN ASSIGNMENT

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Neil Randolph Payne
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1 The MC74AC273/74ACT273 has eight edge-triggered D type flip flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW to HIGH clock transition, is transferred to the corresponding flip flop s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. Ideal Buffer for MOS Microprocessor or Memory Eight Edge-Triggered D Flip Flops Buffered Common Clock Buffered, Asynchronous Master Reset See MC74AC377 for Clock Enable ersion See MC74AC373 for Transparent Latch ersion See MC74AC374 for 3-State ersion Outputs Source/Sink 24 ma ACT273 Has TTL Compatible Inputs PDIP 20 N SUFFIX CASE 738 SO 20 DW SUFFIX CASE 751 TSSOP 20 DT SUFFIX CASE 948E EIAJ 20 M SUFFIX CASE 967 ORDERING INFORMATION Device Package Shipping MC74AC273N PDIP s/rail MC74ACT273N PDIP s/rail MC74AC273DW SOIC s/rail MC74AC273DWR2 SOIC Tape & Reel Figure 1. Pinout: 20 Lead Packages Conductors (Top iew) PIN ASSIGNMENT PIN D 0 D7 FUNCTION Data Inputs MC74ACT273DW SOIC s/rail MC74ACT273DWR2 SOIC Tape & Reel MC74AC273DT TSSOP s/rail MC74AC273DTR2 TSSOP Tape & Reel MC74ACT273DT TSSOP s/rail MC74ACT273DTR2 TSSOP Tape & Reel MR CP Q0 Q7 Master Reset Clock Pulse Input Data Outputs MC74AC273M EIAJ s/rail MC74AC273MEL EIAJ Tape & Reel MC74ACT273M EIAJ s/rail MC74ACT273MEL EIAJ Tape & Reel DEICE MARKING INFORMATION See general marking information in the device marking section on page 7 of this data sheet. Semiconductor Components Industries, LLC, 2001 May, 2001 Rev. 5 1 Publication Order Number: MC74AC273/D

2 Figure 2. Logic Symbol MODE SELECT-FUNCTION TABLE Inputs Outputs Operating Mode MR CP Dn Qn Reset (Clear) L X X L Load 1 H H H Load 0 H L L H = HIGH oltage Level L = LOW oltage Level X = Immaterial = LOW-to-HIGH Clock Transition NOTE: That this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Figure 3. Logic Diagram MAXIMUM RATINGS* Symbol Parameter alue CC DC Supply oltage (Referenced to GND) 0.5 to +7.0 IN DC Input oltage (Referenced to GND) 0.5 to CC +0.5 OUT DC Output oltage (Referenced to GND) 0.5 to CC +0.5 IIN DC Input Current, per Pin ±20 ma IOUT DC Output Sink/Source Current, per Pin ±50 ma ICC DC CC or GND Current per Output Pin ±50 ma Tstg Storage Temperature 65 to +150 C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. 2

3 RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Typ Max CC Supply oltage AC ACT in, out DC Input oltage, Output oltage (Ref. to GND) 0 CC Input Rise and Fall Time (Note 1) tr, tff AC Devices except Schmitt Inputs tr, tf ns/ Input Rise and Fall Time (Note 2) ACT Devices except Schmitt Inputs TJ Junction Temperature (PDIP) 140 C TA Operating Ambient Temperature Range C IOH Output Current High 24 ma IOL Output Current Low 24 ma 1. IN from 30% to 70% CC; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. IN from 0.8 to 2.0 ; see individual Data Sheets for devices that differ from the typical input rise and fall times. DC CHARACTERISTICS Symbol Parameter CC () 74AC TA = +25 C Typ 74AC TA = 40 C to +85 C Guaranteed Limits ns/ Conditions IH Minimum High Level e OUT = 0.1 Input oltage or CC IL Maximum Low Level e OUT = 0.1 Input oltage or CC OH Minimum High Level e IOUT = 50 µa Output oltage *IN = IL or IH ma IOH 24 ma ma OL Maximum Low Level e IOUT = 50 µa Output oltage IIN IOLD IOHD Maximum Input Leakage Current Minimum Dynamic Output t Current *IN = IL or IH ma IOL 24 ma ma 5.55 ±0.1 1 ±1.0 0 µa I = CC, GND ma OLD = 1.65 Max ma OHD = 3.85 Min ICC Maximum Quiescent Supply Current µa IN = CC or GND *All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time. NOTE: Note: IIN and 3.0 are guaranteed to be less than or equal to the respective 5.5 CC. 3

4 AC CHARACTERISTICS (For Figures and Waveforms See Section 3 of the ON Semiconductor FACT Data Book, DL138/D) Symbol Parameter CC* () 74AC TA = +25 C 74AC TA = 40 C to +85 C Min Typ Max Min Max Maximum Clock fmax Frequency Fig. No. Mhz 3 3 tplh Propagation Delay Clock to Output tphl Propagation Delay Clock to Output tphl Propagation Delay MR to Output ns 3 6 ns 3 6 ns 3 6 *oltage Range 3.3 is 3.3 ±0.3. oltage Range 5.0 is 5.0 ±0.5. AC OPERATING REQUIREMENTS Symbol Parameter CC* () Typ 74AC TA = +25 C 74AC TA = 40 C to +85 C Guaranteed Minimum Setup Time, HIGH or LOW ts Data to CP Hold Time, HIGH or LOW th Data to CP Clock Pulse Width tw HIGH or LOW MR Pulse Width tw HIGH or LOW Recovery Time trec MR to CP Fig. No. ns 3 9 ns 3 9 ns 3 6 ns 3 6 ns 3 9 *oltage Range 3.3 is 3.3 ±0.3. oltage Range 5.0 is 5.0 ±0.5. 4

5 DC CHARACTERISTICS Symbol Parameter CC () 74ACT TA = +25 C Typ 74ACT TA = 40 C to +85 C Guaranteed Limits IH Minimum High Level e Input oltage IL Maximum Low Level e Input oltage OH Minimum High Level e Output oltage Conditions OUT = 0.1 or CC 0.1 OUT = 0.1 or CC 0.1 IOUT = 50 µa OL Maximum Low Level e Output oltage *IN = IL or IH 24 ma IOH 24 ma IOUT = 50 µa *IN = IL or IH ma IOL 24 ma IIN Maximum Input 5.55 ±0.1 1 ±1.0 0 µa Leakage Current I = CC, GND ICCT Additional Max. ICC/Input ma I = CC 2.1 IOLD IOHD Minimum Dynamic Output t Current ma OLD = 1.65 Max ma OHD = 3.85 Min ICC Maximum Quiescent Supply Current *All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time µa IN = CC or GND AC CHARACTERISTICS (For Figures and Waveforms See Section 3 of the ON Semiconductor FACT Data Book, DL138/D) Symbol fmax tphl tplh tphl Maximum Clock Frequency Propagation Delay Clock to Output Propagation Delay Clock to Output Propagation Delay MR to Output *oltage Range 5.0 is 5.0 ±0.5. Parameter CC* () 74ACT TA = +25 C 74ACT TA = 40 C to +85 C Min Typ Max Min Max Fig. No MHz ns ns ns 3 6 5

6 AC OPERATING REQUIREMENTS Symbol Parameter ts Setup Time, HIGH or LOW Data to CP th Hold Time, HIGH or LOW Data to CP tw Clock Pulse Width HIGH or LOW tw MR Pulse Width HIGH or LOW trec Recovery Time MR to CP *oltage Range 5.0 is 5.0 ±0.5. CC* () Typ 74ACT TA = +25 C 74ACT TA = 40 C to +85 C Guaranteed Minimum Fig. No ns ns ns ns ns 3 6 CAPACITANCE Symbol Parameter alue Typ Test Conditions CIN Input Capacitance 4.5 pf CC = 5.0 CPD Power Dissipation Capacitance 50 pf CC = 5.0 6

7 MARKING DIAGRAMS PDIP 20 SO 20 TSSOP 20 EIAJ 20 MC74AC273N AWLYYWW AC273 AWLYYWW AC 273 ALYW 74AC273 AWLYWW MC74ACT273N AWLYYWW ACT273 AWLYYWW ACT 273 ALYW 74ACT273 AWLYWW A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week 7

8 PACKAGE DIMENSIONS PDIP 20 N SUFFIX 20 PIN PLASTIC DIP PACKAGE CASE ISSUE E T G E A F B K N D 20 PL C L M J 20 PL SO 20 DW SUFFIX 20 PIN PLASTIC SOIC PACKAGE CASE 751D 05 ISSUE F D A H 10X E h X 45 20X B 18X e B A A1 T C L 8

9 PACKAGE DIMENSIONS e L Z b 2X L/2 PIN 1 IDENT C T D 20X K REF A D G H TSSOP 20 DT SUFFIX 20 PIN PLASTIC TSSOP PACKAGE CASE 948E 02 ISSUE A E A HE A1 B U J J1 N N K K1 ÍÍÍ ÍÍÍ SECTION N N F DETAIL E DETAIL E EIAJ 20 M SUFFIX 20 PIN PLASTIC EIAJ PACKAGE CASE ISSUE O IEW P M LE L DETAIL P M Q1 c W 9

10 Notes 10

11 Notes 11

12 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada ONlit@hibbertco.com N. American Technical Support: Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center Nishi Gotanda, Shinagawa ku, Tokyo, Japan Phone: r14525@onsemi.com ON Semiconductor Website: For additional information, please contact your local Sales Representative. 12 MC74AC273/D

ORDERING INFORMATION Figure 1. Pinout: 20 Lead Packages Conductors (Top View) PIN ASSIGNMENT

ORDERING INFORMATION Figure 1. Pinout: 20 Lead Packages Conductors (Top View) PIN ASSIGNMENT The MC74AC574/74ACT574 is a high speed, low power octal flip flop with a buffered common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is stored in the