DATASHEET. Features. Applications. Pinouts EL5160 (8 LD SOIC) TOP VIEW EL5160, EL5161, EL5260, EL5261, EL5360

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1 DATASHEET EL6, EL6, EL6, EL6, EL6 MHz LowPower Current Feedback Amplifiers The EL6, EL6, EL6, EL6, and EL6 are current feedback amplifiers with a bandwidth of MHz and operate from just.7ma supply current. This makes these amplifiers ideal for today s high speed video and monitor applications. With the ability to run from a single supply voltage from V to V, these amplifiers are ideal for handheld, portable, or batterypowered equipment. The EL6, EL6, and EL6 also incorporate an enable and disable function to reduce the supply current to µa typical per amplifier. Allowing the CE pin to float or applying a low logic level enables the corresponding amplifier. The EL6 is available in the 6 Ld SOT and 8 Ld SOIC packages, the EL6 in Ld SOT package, the EL6 in the Ld MSOP package, the EL6 in 8 Ld SOIC package, the EL6 in 6 Ld SOIC and QSOP packages. All operate over the industrial temperature range of C to 8 C. Features FN787 Rev. MHz db bandwidth.7ma supply current 7V/µs slew rate Single and dual supply operation, from V to V supply span Fast enable/disable (EL6, EL6 and EL6 only) Available in SOT packages PbFree (RoHS compliant) Applications Batterypowered equipment Handheld, portable devices Video amplifiers Cable drivers RGB amplifiers Test equipment Instrumentation Currenttovoltage converters Pinouts EL6 (8 LD SOIC) EL6 (6 LD SOT) EL6 ( LD SOT) NC 8 CE 6 VS VS 7 6 VS CE VS VS VS NC EL6 ( LD MSOP) EL6 (8 LD SOIC) EL6 (6 LD SOIC, QSOP) VS A 8 VS INA 6 INA INA VS 7 6 B INB CEA VS INA INB VS CEB A VS B CE 6 CE INB INB NC 6 NC CEC 7 C INC 8 9 INC FN787 Rev. Page of 7

2 Ordering Information PART NUMBER (Notes, ) PART MARKING TAPE & REEL PACKAGE (Pbfree) PKG. DWG. # EL6ISZ 6ISZ 8 Ld SOIC ( mil) M8.E EL6ISZT7 (Note ) 6ISZ 7 8 Ld SOIC ( mil) M8.E EL6ISZT7A (Note ) 6ISZ 7 8 Ld SOIC ( mil) M8.E EL6ISZT (Note ) 6ISZ 8 Ld SOIC ( mil) M8.E EL6IWZT7 (Note ) BAAN (Note ) 7 (k pcs) 6 Ld SOT P6.6A EL6IWZT7A (Note ) BAAN (Note ) 7 ( pcs) 6 Ld SOT P6.6A EL6IWZT7 (Note ) BAJA (Note ) 7 (k pcs) Ld SOT P6.6A EL6IWZT7A (Note ) BAJA (Note ) 7 ( pcs) Ld SOT P6.6A EL6IYZ EL6IYZT7 (Note ) EL6IYZT (Note ) EL6ISZ EL6ISZT7 (Note ) EL6ISZT (Note ) EL6ISZ EL6ISZT7 (Note ) EL6ISZT (Note ) EL6IUZ(No longer available or supported) EL6IUZT7 (Note ) EL6IUZT (Note ) BAAAK Ld MSOP (.mm) M.8A BAAAK 7 Ld MSOP (.mm) M.8A BAAAK Ld MSOP (.mm) M.8A 6ISZ 8 Ld SOIC ( mil) M8.E 6ISZ 7 8 Ld SOIC ( mil) M8.E 6ISZ 8 Ld SOIC ( mil) M8.E EL6ISZ 6 Ld SOIC ( mil) MDP7 EL6ISZ 7 6 Ld SOIC ( mil) MDP7 EL6ISZ 6 Ld SOIC ( mil) MDP7 6IUZ 6 Ld QSOP ( mil) MDP 6IUZ 7 6 Ld QSOP ( mil) MDP 6IUZ 6 Ld QSOP ( mil) MDP NOTES:. Please refer to TB7 for details on reel specifications.. Intersil Pbfree plus anneal products employ special Pbfree material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pbfree soldering operations. Intersil Pbfree products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J STD.. For Moisture Sensitivity Level (MSL), please see product information page for EL6, EL6, EL6, EL6, EL6. For more information on MSL, please see tech brief TB6.. The part marking is located on the bottom of the part. FN787 Rev. Page of 7

3 Absolute Maximum Ratings (T A = C) Supply Voltage between and v Maximum Continuous Output Current ma Slew Rate of to V/µs Pin Voltages ().V to ().V Thermal Information Maximum Operating Junction Temperature C Maximum Power Dissipation see curves on page 7 Maximum Storage Temperature Range C to C Ambient Operating Temperature Range C to 8 C Pbfree reflow profile see link below CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications = V, = V, R F = 7Ω for A V =, R L = Ω, V CE, H =, V CE, L = () V, T A = C, Unless Otherwise Specified. Boldface limits apply across the operating temperature range, C to 8 C. PARAMETER DESCRIPTION CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT AC PERFORMANCE BW db Bandwidth A V =, R L = MHz A V =, R L = Ω MHz BW.dB Bandwidth R L = Ω MHz SR Slew Rate V O =.V to.v, A V =, R F = R G = kω, R L = Ω 9 7 V/µs EL6, EL6 8 V/µs SR Load 6 V/µs t S.% Settling Time V =.V to.v, A V = ns e N Input Voltage Noise nv/ Hz i N Input Current Noise 7 pa/ Hz i N Input Current Noise 8 pa/ Hz HD MHz,.V PP, R L = Ω, A V = 7 dbc HD MHz,.V PP, R L = Ω, A V = dbc dg Differential Gain Error (Note ) A V =. % dp Differential Phase Error (Note ) A V =. DC PERFORMANCE V OS Offset Voltage.6 mv T C V OS Input Offset Voltage Temperature Coefficient Measured from T MIN to T MAX 6 µv/ C R OL Open Loop Transimpedance Gain ±.V into Ω 8 kω INPUT CHARACTERISTICS CMIR Common Mode Input Range Guaranteed by CMRR test ± ±. V CMRR Common Mode Rejection Ratio V IN = ±V 6 7 db ICMR Input Current Common Mode Rejection µa/v I IN Input Current µa I IN Input Current µa R IN Input Resistance. MΩ C IN Input Capacitance pf FN787 Rev. Page of 7

4 Electrical Specifications = V, = V, R F = 7Ω for A V =, R L = Ω, V CE, H =, V CE, L = () V, T A = C, Unless Otherwise Specified. Boldface limits apply across the operating temperature range, C to 8 C. (Continued) PARAMETER DESCRIPTION CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNIT PUT CHARACTERISTICS V O Output Voltage Swing R L = Ω to GND ±. ±. ±.8 V R L = kω to GND ±.8 ±. ±. V I Output Current R L = Ω to GND 7 ma SUPPLY I SON Supply Current Enabled, per Amplifier No load, V IN = V (EL6, EL6, EL6, EL6) ma No load, V IN = V (EL6) ma I SOFF Supply Current Disabled, per Amplifier No load, V IN = V, Only EL6, EL6, µa I SOFF Supply Current Disabled, per Amplifier EL6 µa PSRR Power Supply Rejection Ratio DC, V S = ±.7V to ±.V 6 7 db IPSR Input Current Power Supply Rejection DC, V S = ±.7V to ±.V... µa/v ENABLE (EL6, EL6, EL6 ONLY) t EN Enable Time 6 ns t DIS Disable Time 8 ns I CE, H CE Pin Input High Current CE = µa I CE, L CE Pin Input Low Current CE = () V µa NOTE:. Standard NTSC test, AC signal amplitude = 86mV PP, f =.8MHz. 6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. Typical Performance Curves V S = V V S = V R L = Ω A V = R F = 86Ω R G = 86Ω 7 k M M M G V S = V V S = V A V = R L = R F = 8Ω 6 k M M M G FIGURE. FREQUENCY RESPONSE (A V = ) FIGURE. FREQUENCY RESPONSE (A V = ) FN787 Rev. Page of 7

5 Typical Performance Curves (Continued) R L = R F =.7kΩ A V = ±V ±V ±V ±.V ±6V A V = R L =Ω R F = R G = 76Ω ±V ±V ±.V ±V ±6V k M M M G FIGURE. FREQUENCY RESPONSE FOR VARIOUS ±V S 6 k M M M G FIGURE. FREQUENCY RESPONSE FOR VARIOUS SUPPLY VOLTAGES V S = V V S = V A V = R L = R F = 6Ω TRANSIMPEDANCE (Ω) M M k k k 6 k M M M G FIGURE. FREQUENCY RESPONSE (A V = ) k k k M M M G FIGURE 6. OPEN LOOP TRANSIMPEDANCE GAIN vs FREQUENCY (R OL ) INPUT V/DIV PUT mv/div INPUT V/DIV PUT mv/div V S = V V S = V A V = R L = Ω R F = R G = Ω V S = V V S = V A V = R L = Ω R F = R G = Ω ns/div FIGURE 7. PUT RISE TIME ns/div FIGURE 8. PUT FALL TIME FN787 Rev. Page of 7

6 Typical Performance Curves (Continued) V S = V V S = V CE V/DIV V/DIV CE mv/div V mv/div V V S = V V S = V ns/div FIGURE 9. DISABLE DELAY TIME ns/div FIGURE. ENABLE DELAY TIME PSRR (db) 6 8 V S = V V S = V V S V S PUT IMPEDANCE (Ω) K m V S = V V S = V k k k M M M G FIGURE. PSRR vs FREQUENCY m k k M M M FIGURE. CLOSED LOOP PUT IMPEDANCE vs FREQUENCY V S = ±V R G = 7Ω R L = Ω A V = A V = A V = V S = ±V A V = R L = Ω R F = kω R F =.kω R F = 768Ω R F =.kω 6 k M M M G 6 k M M M G FIGURE. FREQUENCY RESPONSE FOR VARIOUS GAIN SETTINGS FIGURE. FREQUENCY RESPONSE FOR VARIOUS FEEDBACK RESISTORS, A V = FN787 Rev. Page 6 of 7

7 Typical Performance Curves (Continued) V S = ±V R F = 768Ω R L = A V = A V = A V = A V = V S = ±V A V = R L = Ω R F = 7Ω R F =.8kΩ R F = kω 6 k M M M G FIGURE. FREQUENCY RESPONSE FOR VARIOUS GAIN SETTINGS k M M M G FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS FEEDBACK RESISTORS, A V = POWER DISSIPATION (W) JEDEC JESD7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD..W. SO6 (. ) 99mW JA = 8 C/W mw SOT/6 JA = C/W SO8 JA = C/W POWER DISSIPATION (W) JEDEC JESD7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD mW 87mW MSOP JA = C/W QSOP6 JA = C/W FIGURE 7. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 8. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE POWER DISSIPATION (W) JEDEC JESD LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD mW 6mW 9mW SO6 (. ) JA = C/W SOT/6 JA = 6 C/W 7 8 SO8 JA = 6 C/W FIGURE 9. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE POWER DISSIPATION (W) JEDEC JESD LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD mW 86mW MSOP JA = 6 C/W QSOP6 JA = 8 C/W 7 8 FIGURE. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN787 Rev. Page 7 of 7

8 Pin Descriptions EL6 (8 Ld SOIC) EL6 (6 Ld SOT) EL6 EL6 EL6 EL6 PIN NAME FUNCTION EQUIVALENT CIRCUIT, 6, NC Not connected, 8, 6 9,, 6 Inverting input Circuit, 7,,, 8 Noninverting input (See circuit ) Negative supply 6, 9, 7,, Output Circuit Positive supply 8, 6,, 7 CE Chip enable CE Circuit Applications Information Product Description The EL6, EL6, EL6, EL6, and EL6 are low power, currentfeedback operational amplifiers that offer a wide db bandwidth of MHz and a low supply current of.7ma per amplifier. The EL6, EL6, EL6, EL6, and EL6 work with supply voltages ranging from a single V to V and they are also capable of swinging to within V of either supply on the output. Because of their currentfeedback topology, the EL6, EL6, EL6, EL6, and EL6 do not have the normal gainbandwidth product associated with voltagefeedback operational amplifiers. Instead, their db bandwidth remains relatively constant as closedloop gain is increased. This combination of high bandwidth and low power, together with aggressive pricing make the EL6, EL6, EL6, EL6, and EL6 ideal choices for many lowpower/highbandwidth applications such as portable, handheld, or batterypowered equipment. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Low impedance ground plane construction is essential. Surface mount components are recommended, but if leaded components are used, lead lengths should be as short as possible. The power supply pins must be well bypassed to reduce the risk of oscillation. The combination of a.7µf tantalum capacitor in parallel with a.µf capacitor has been shown to work well when placed at each supply pin. For good AC performance, parasitic capacitance should be kept to a minimum, especially at the inverting input. (See the Capacitance at the Inverting Input section) Even when ground plane construction is used, it should be removed from the area near the inverting input to minimize any stray capacitance at that node. Carbon or MetalFilm resistors are acceptable with the MetalFilm resistors giving slightly less peaking and bandwidth because of additional series inductance. Use of sockets, particularly for the SO package, should be avoided if possible. Sockets add parasitic inductance and capacitance which results in additional peaking and overshoot. FN787 Rev. Page 8 of 7

9 Disable/PowerDown The EL6, EL6, EL6 amplifiers can be disabled, placing the output in a high impedance state. When disabled, the amplifier supply current reduces to <µa. The amplifiers disable when their CE pin is pulled up to within V of the positive supply. Similarly, the amplifier is enabled by floating or pulling its CE pin to at least V below the positive supply. For a ±V supply, this means that an amplifier is enabled when CE is V or less, and disabled when CE is above V. Although the logic levels are not standard TTL, this choice of logic voltages allows an amplifier to be enabled by tying CE to ground, even in V single supply applications. The CE pin can be driven from CMOS outputs. Capacitance at the Inverting Input Any manufacturer s highspeed voltage or currentfeedback amplifier can be affected by stray capacitance at the inverting input. For inverting gains, this parasitic capacitance has little effect because the inverting input is a virtual ground, but for noninverting gains, this capacitance (in conjunction with the feedback and gain resistors) creates a pole in the feedback path of the amplifier. This pole, if low enough in frequency, has the same destabilizing effect as a zero in the forward openloop response. The use of largevalue feedback and gain resistors exacerbates the problem by further lowering the pole frequency (increasing the possibility of oscillation.) The EL6, EL6, EL6, EL6, and EL6 are optimized for an 86Ω (A V = ) feedback resistor. With the high bandwidth of these amplifiers, these resistor values might cause stability problems when combined with parasitic capacitance, thus ground plane is not recommended around the inverting input pin of the amplifier. Feedback Resistor Values The EL6, EL6, EL6, EL6, and EL6 have been designed and specified at a gain of with R F approximately 86. This value of feedback resistor gives MHz of db bandwidth at A V = with db of peaking. Since the EL6, EL6, EL6, EL6, and EL6 are currentfeedback amplifiers, it is also possible to change the value of R F to get more bandwidth. As seen in the curve of Frequency Response for Various R F and R G on page, bandwidth and peaking can be easily modified by varying the value of the feedback resistor. Because the EL6, EL6, EL6, EL6, and EL6 are currentfeedback amplifiers, their gainbandwidth product is not a constant for different closedloop gains. This feature actually allows the EL6, EL6, EL6, EL6, and EL6 to maintain about the same db bandwidth. As gain is increased, bandwidth decreases slightly while stability increases. Since the loop stability is improving with higher closedloop gains, it becomes possible to reduce the value of R F below the specified 86Ω value and still retain stability, resulting in only a slight loss of bandwidth with increased closedloop gain. Supply Voltage Range and SingleSupply Operation The EL6, EL6, EL6, EL6, and EL6 have been designed to operate with supply voltages having a span of V to V. In practical terms, this means that they will operate on dual supplies ranging from ±.V to ±V. With singlesupply, the EL6, EL6, EL6, EL6, and EL6 will operate from V to V. As supply voltages continue to decrease, it becomes necessary to provide input and output voltage ranges that can get as close as possible to the supply voltages. The EL6, EL6, EL6, EL6, and EL6 have an input range which extends to within V of either supply. So, for example, with ±V supplies, the EL6, EL6, EL6, EL6, and EL6 have an input range which spans ±V. The output range of the EL6, EL6, EL6, EL6, and EL6 is also quite large, extending to within V of the supply rail. On a ±V supply, the output is therefore capable of swinging from V to V. Singlesupply output range is larger because of the increased negative swing due to the external pulldown resistor to ground. Video Performance For good video performance, an amplifier is required to maintain the same output impedance and the same frequency response as DC levels are changed at the output. This is especially difficult when driving a standard video load of Ω, because of the change in output current with DC level. Previously, good differential gain could only be achieved by running high idle currents through the output transistors (to reduce variations in output impedance.) These currents were typically comparable to the entire ma supply current of each EL6, EL6, EL6, EL6, and EL6 amplifier. Special circuitry has been incorporated in the EL6, EL6, EL6, EL6, and EL6 to reduce the variation of output impedance with current output. This results in dg and dp specifications of.% and., while driving Ω at a gain of. Video performance has also been measured with a load at a gain of. Under these conditions, the EL6 has dg and dp specifications of.% and.. Output Drive Capability In spite of their low ma per amplifier supply current, the EL6, EL6, EL6, EL6, and EL6 are capable of providing a minimum of ±ma of output current. With a minimum of ±ma of output drive, the EL6 is capable of driving Ω loads to both rails, making it an excellent choice for driving isolation transformers in telecommunications applications. FN787 Rev. Page 9 of 7

10 Driving Cables and Capacitive Loads When used as a cable driver, double termination is always recommended for reflectionfree performance. For those applications, the backtermination series resistor will decouple the EL6, EL6, EL6, EL6, and EL6 from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a backtermination resistor. In these applications, a small series resistor (usually between Ω and Ω) can be placed in series with the output to eliminate most peaking. The gain resistor (R G ) can then be chosen to make up for any gain loss which may be created by this additional resistor at the output. In many cases it is also possible to simply increase the value of the feedback resistor (R F ) to reduce the peaking. Current Limiting The EL6, EL6, EL6, EL6, and EL6 have no internal currentlimiting circuitry. If the output is shorted, it is possible to exceed the Absolute Maximum Rating for output current or power dissipation, potentially resulting in the destruction of the device. Power Dissipation With the high output drive capability of the EL6, EL6, EL6, EL6, and EL6, it is possible to exceed the C Absolute Maximum junction temperature under certain very high load current conditions. Generally speaking when R L falls below about Ω, it is important to calculate the maximum junction temperature (T JMAX ) for the application to determine if power supply voltages, load conditions, or package type need to be modified for the EL6, EL6, EL6, EL6, and EL6 to remain in the safe operating area. These parameters are calculated as follows: T JMAX = T MAX JA n PD MAX where: T MAX = Maximum ambient temperature JA = Thermal resistance of the package n = Number of amplifiers in the package PD MAX = Maximum power dissipation of each amplifier in the package PD MAX for each amplifier can be calculated as follows: Typical Application Circuits V IN V V V V Ω Ω V FIGURE. INVERTING ma PUT CURRENT DISTRIBUTION AMPLIFIER V IN V V V V V FIGURE. FASTSETTLING PRECISION AMPLIFIER V MAX PD MAX = V S I SMAX V S V MAX R L where: V S = Supply voltage I SMAX = Maximum supply current of.8ma V MAX = Maximum output voltage (required) R L = Load resistance FN787 Rev. Page of 7

11 V V V Ω V V V IN V V Ω V Ω kω kω V V V TRANSMITTER RECEIVER FIGURE. DIFFERENTIAL LINE DRIVER/RECEIVER Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE FN787. Updated Ordering Information table on page. Added Revision History and About Intersil sections. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and highend consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at FN787 Rev. Page of 7

12 Small Outline Package Family (SO) A D h X N (N/) E E PIN # I.D. MARK c A SEE DETAIL X B. M C A B (N/) L C e H A SEATING PLANE GAUGE PLANE.. C. M C A B b A DETAIL X L ± MDP7 SMALL LINE PACKAGE FAMILY (SO) INCHES SO6 SO6 (. ) SO SO SO8 SYMBOL SO8 SO (. ) (SOL6) (SOL) (SOL) (SOL8) TOLERANCE NOTES A MAX A A b c D , E E , e Basic L L Basic h Reference N Reference Rev. M /7 NOTES:. Plastic or metal protrusions of.6 maximum per side are not included.. Plastic interlead protrusions of. maximum per side are not included.. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.M99 FN787 Rev. Page of 7

13 Package Outline Drawing P6.6A 6 LEAD SMALL LINE TRANSISTOR PLASTIC PACKAGE Rev, /.9 A.9 D.8. 6 PIN INDEX AREA.8.6. C x D. C x (.6) B. ±. SEE DETAIL X. M C AB D END VIEW.9. C x AB TYP ( PLCS) H. ±. C. MAX SIDE VIEW... C SEATING PLANE (.) GAUGE PLANE DETAIL "X".±. (.6) (.) (.) NOTES:. Dimensions are in millimeters. Dimensions in ( ) for Reference Only.. Dimensioning and tolerancing conform to ASME Y.M99. (.9) Dimension is exclusive of mold flash, protrusions or gate burrs. Foot length is measured at reference to guage plane. This dimension is measured at Datum H. Package conforms to JEDEC MO78AA. (.9) TYPICAL RECOMMENDED LAND PATTERN FN787 Rev. Page of 7

14 Package Outline Drawing P.6A LEAD SMALL LINE TRANSISTOR PLASTIC PACKAGE Rev, / A.9 D.8. PIN INDEX AREA. C D x.9.8. C x.6 (.6) B. ±.. M C AB D SEE DETAIL X END VIEW TYP ( PLCS).9. C x AB H C. MAX. ±.. C SEATING PLANE (.) GAUGE PLANE SIDE VIEW...±. DETAIL "X" (.6) (.) NOTES: (.).. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to ASME Y.M99. (.9) (.9) TYPICAL RECOMMENDED LAND PATTERN Dimension is exclusive of mold flash, protrusions or gate burrs. Foot length is measured at reference to guage plane. This dimension is measured at Datum H. Package conforms to JEDEC MO78AA. FN787 Rev. Page of 7

15 Package Outline Drawing M8.E 8 LEAD NARROW BODY SMALL LINE PLASTIC PACKAGE Rev, 8/9.9 ±. A DETAIL "A". ±. B 6. ±..9 ±. PIN NO. ID MARK.7. ±.76 (.) x ±. MCAB SIDE VIEW B.7 MAX. ±..7 ±.7 SIDE VIEW A. GAUGE PLANE C SEATING PLANE. C.6 ±. (.7) (.6) DETAIL "A" (.) NOTES:. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. (.) Dimensioning and tolerancing conform to AMSE Y.m99. Unless otherwise specified, tolerance : Decimal ±. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed.mm per side. The pin # identifier may be either a mold or mark feature. Reference to JEDEC MS. TYPICAL RECOMMENDED LAND PATTERN FN787 Rev. Page of 7

16 Package Outline Drawing M.8A (JEDEC MO87BA) LEAD MINI SMALL LINE PLASTIC PACKAGE (MSOP) Rev, 9/9. ±. A. C A B DETAIL "X". Max. ±..9 ±. SIDE VIEW.8 ±. PIN# ID B. BSC.9 BSC Gauge H.86 ±.9 Plane. C..7/.8.8 CAB SEATING PLANE. ±.. C. ±. DETAIL "X" ± SIDE VIEW.8.. NOTES:. Dimensions are in millimeters.. Dimensioning and tolerancing conform to AMSE Y.m Plastic or metal protrusions of.mm max per side are not included. Plastic interlead protrusions of.mm max per side are not included. Dimensions D and E are measured at Datum Plane H. TYPICAL RECOMMENDED LAND PATTERN 6. This replaces existing drawing # MDP MSOPL. FN787 Rev. Page 6 of 7

17 Quarter Size Outline Plastic Packages Family (QSOP) A N D (N/) MDP QUARTER SIZE LINE PLASTIC PACKAGES FAMILY INCHES SYMBOL QSOP6 QSOP QSOP8 TOLERANCE NOTES E E PIN # I.D. MARK A Max. A ±. A ±. b... ±. B. C A B (N/) c ±. D.9..9 ±., E ±.8 C SEATING PLANE. C e.7 C A B b H E... ±., e... Basic L... ±.9 L... Basic N 6 8 Reference c L SEE DETAIL "X" A Rev. F /7 NOTES:. Plastic or metal protrusions of.6 maximum per side are not included.. Plastic interlead protrusions of. maximum per side are not included.. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.M99. A GAUGE PLANE. A DETAIL X L ± Copyright Intersil Americas LLC. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN787 Rev. Page 7 of 7