Agenda. FPGA Network Safety, Certification & Security. Thursday 19 th May University of Hertfordshire. Sponsored by

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1 FPGA Network Safety, Certification & Security Thursday 19 th May University of Hertfordshire Agenda 9:30 Registration & Coffee, Networking and Table-tops Sponsored by Welcome and introduction - Prof Sotudeh, University of Hertfordshire A Practical Guide to SEU Risks, Effects and Mitigation - Ken Chapman, Xilinx Four Simple Measures to Improve FPGA Testability - Matt Noonan, Resource Group Break Automated Traceability to Assist DO-254 Certification - Andy Nicol, Finnmeccanica Easing Functional Safety Certification with Pre-Certified FPGA Tool Flows (IEC 61508) - Roger May, Altera (now part of Intel) D0-254 Coding Checks for RTL Code - Graeme Jessiman, Mentor Graphics Lunch Special Host Presentation: FPGAs for Reconfigurable 5G and Beyond Wireless Communication - Dr. Milos Milosavljevic, University of Hertfordshire Preventing Overbuilding and Cloning of Electronic Systems Secure Production Programming - Peter Trott, Microsemi Corporation Implications of Code Coverage Verification Techniques for Designs Adhering to DO David Clift, First EDA Event Close Thank you to our Event Host and Exhibitors

2 About Us NMI is the trade association representing the UK Electronic Systems, Microelectronics and Semiconductor Communities. Our objective is to aid the development of a sustainable, world-leading industry by building a strong network and acting as a catalyst and facilitator for commercial and technological development. A not-for-profit organisation funded by its members, NMI is the home for a membership that spans the supply chain and includes Electronic Systems Design and Manufacturing Companies, Integrated Device Manufacturers, Fabless Semiconductor Manufacturers, Semiconductor Foundries, Semiconductor Suppliers, Electronic Design Services, Intellectual Property Providers, Research & Academic Institutions, National and Regional Government Agencies. NMI s work includes: Encouraging innovation, communication and collaboration through networking, funding, brokering and sign-posting activities. Representing the Electronic Systems, Micro & Nano-electronics sectors to government, policy makers and public funding bodies. Supporting skills development, education and training. Improving operational efficiency through benchmarking and best practice initiatives. Providing an industry specific information flow NMI welcomes collaborations on a national and global basis, ensuring we can deliver the very best service to members and partners. Contact Us Livingston - Head Office Tel: +44 (0) Fax: +44 (0) info@nmi.org.uk

3 Speaker Biographies Andy Nicol, Finnmeccanica Andy has a Master s degree in Electrical & Mechanical Engineering from The University of Edinburgh and now works for Selex ES, a leading defence, security and smart systems firm, at their Edinburgh site which specialises in radar, advanced targeting and other mission critical systems. His current primary role involves the rapid development and implementation of firmware algorithms for use in a next-generation infra-red countermeasure system. Graeme Jessiman, Mentor Graphics Graeme has a background in ASIC/FPGA design, having previously spent 10 years as a chip designer for a satellite manufacturer. He joined Mentor in 1997 and since 2001 he has worked in an Applications Engineering role, supporting Mentor s digital design and verification products to a wide spectrum of customer across many market segments. He has worked with several companies involved in design assurance projects (e.g. D0-254, ISO26262, IEC 61508) to adopt new verification methodologies into their design processes. Graeme has an Honour s Degree in Electrical & Electronic Engineering from the Robert Gordon University in Aberdeen. David Clift, FirstEDA Applications Specialist, Aldec Products, FirstEDA. David Clift has worked with and supported Aldec products for over 10 years as part of his 30-year career to date in ASIC and FPGA design. David started at GEC Marconi as an R&D engineer working on a range of projects including silicon on sapphire and radiation tolerant ICs. Moving into the EDA industry 20 years ago, he has provided support on HDL tools and methodologies for customers across Europe and developed great insight as a result. At FirstEDA, as well as having product specialism in mission- and safety-critical applications, David is also responsible for the creation and delivery of complimentary formal training.

4 Ken Chapman, Xilinx Ken left school at the age of 16 and initially worked in manufacturing, assembly, inspection and test environments whilst also attending Southend Technical College on a day release and evening basis to obtain TEC and HNC qualifications. At the ripe old age of 20, Ken returned to full time education to acquire a BSc in Electronic and Electrical Engineering from the University of Surrey. University was followed by 4 years at a large defence company. The design, testing and system integration of naval RADAR surveillance and counter measures equipment emphasized that there was far more involved in making large systems work reliably. During this time Xilinx XC3090 devices were used to implement circuits operating at the then phenomenal clock frequency of 20MHz. In 1991, Ken joined Xilinx where he has been an Applications Engineer ever since. Most known for his 8- bit PicoBlaze processor which reflects his passion for optimum FPGA design techniques, Ken also holds several patents relating to his pioneering implementation of DSP algorithms in FPGA devices. He has also written and taught courses around the world on these subjects as design techniques for lower cost of high volume products, design for reliability and SEU mitigation techniques. Outside of work, Ken is a private pilot and takes to the skies when the British weather allows. Matt Noonan, Resource Group Matt Noonan is a project manager for Resource Group Embedded Systems & Solutions. For the past 8 years he has worked on high integrity software and FPGA applications in aerospace, rail, energy and defence. Specialising in DO- 178, IEC and DO-254 certifications. Resource Group ESS works on behalf of many major UK companies on projects such as the A400-M and A380, the Boeing 787, the Thameslink rail extension and the DolWin3 offshore wind farm. Dr. Milos Milosavljevic, University of Hertfordshire Dr. Milos Milosavljevic is a Senior Lecturer in Digital Communications and Electronics, leading the research activities in smart back- and front-hauling networks for future wireless systems. His research has extended from radio over fibre transmission techniques, to the smarter digital solutions for back- and front-hauling of millimetre wave cellular radio access networks and the design of new spectral efficient waveforms on FPGAs as well as application of those for software defined networking. He has published over 30 peer-reviewed journals and conference papers, acted as a technical program committee member and sessions chair of a several conferences and was invited to present on workshops in optical and wireless access networks. He is currently supervising 6 PhD students in relevant research areas, has examined PhDs in Europe and at UH and has been reviewer of IEEE/OSA manuscripts. He has helped to secure and was working on several national and international research and consultancy based projects (FP7 ACCORDANCE, FP6 BONE, KTP, K4B, and Nuffield).

5 Pete Davy, NMI FPGA Network Director Pete Davy is an independent business consultant experienced in semiconductors and electronic system market segments gained in USA, Israel and Europe. He has held senior positions in marketing underpinned by roles in software development at: Mentor Graphics, Mars Electronics and NEI Parsons. With NMI Pete manages the FPGA professional network and is helping to construct the 2016 Future World conference. Pete is a graduate of Electronic Engineering from University of Nottingham Peter Trott, MicroSemi Peter Trott is a Senior FAE at Microsemi supporting the SOC and FPGA products and has been with the company for 8 years. He is a technical expert in programmable logic with over 25 years of industry experience with AMD, Vantis, Lattice and Mathstar before joining Actel prior to the acquisition. Before moving into the many application rolls, Peter was a design engineer at ICL and holds a BSc in Electronics from the University of Bristol. Roger May, Altera (now part of Intel)

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7 Presentation Abstracts Andy Nicol, Finmeccanica Automated Traceability to Assist DO-254 Certification Presents Finmeccanica s use of automated requirement-, design-, and test-traceability tools (particularly based around the Mentor Graphics ReqTracer tool) in order to aid in certification against the DO-254 standard. David Clift, FirstEDA Implications of Code Coverage Verification Techniques for Designs Adhering to DO-254 In DO-254, elemental analysis provides metrics on how much of the design was covered through the requirements-based verification of the associated functional elements - the goal is to show that there is no redundant or dead code in the design. Redundant code not only consumes device resources, it can also be a vector for a cyberattack or device operation outside of the design requirements, leading to potential system failure. In this presentation we will look at different code coverage techniques and discuss their potential limitations as well as introducing strategies to improve the verification and quality of your designs. Graeme Jessiman - Mentor Graphics D0-254 Coding Checks for RTL Code DO-254 discusses the need for Design Standards and Order takes this a step further, discussing the specific need for HDL coding standards. Because of this, many companies having to comply with DO-254 are either looking for examples of good standards to use, or recognize that they have insufficient or inconsistent standards and want to improve their approach. The DO-254 Users Group launched an initiative where they gathered information from 20+ companies on the HDL coding standards that were deemed most applicable for DO-254 design programs. This presentation will provide an overview of the generally accepted HDL design best practice coding guidelines that should be considered for any fail-safe design, including DO-254 programs. It also describes how to automate the checking of these HDL coding standards using the DesignChecker in HDL Designer. Ken Chapman, Xilinx A Practical Guide to SEU Risks, Effects and Mitigation NS&I have announced that from the 1st June the odds of winning a Premium Bond each month will reduce from 26,000:1 to 30,000:1. What hasn t changed is that you are still way more likely to win 25 than one of the two 1,000,000 prizes should ERNIE pick one of your numbers. Single Event Upsets (SEU) are unavoidable but what are the odds of one happening to the FPGA in your product and what impact will it have on the operation of your design if it does? This short practical guide will ensure that you know how to calculate the SEU FIT rate for different devices and to actually observe the effects SEU have on the operation of your design. Knowing the design SEU FIT rate empowers you to select a suitable mitigation strategy that meets the reliability targets of your system.

8 Matt Noonan, Resource Group Four Simple Measures to Improve FPGA Testability FPGA usage within high integrity systems is becoming both more popular and more complex. One of the challenges of putting an FPGA in a high integrity system is the cost of verifying its correct operation, and this is made significantly more difficult by the increasing complexity of FPGA applications. Analysis of several high integrity projects has identified a number of common testability issues and four simple measures can be used to mitigate these; reducing risk, cost and timescales. Dr. Milos Milosavljevic, University of Hertfordshire FPGAs for Reconfigurable 5G and Beyond Wireless Communication The next generation wireless communications system will not be used for human interactions alone. Instead a huge growth in machine type communications is expected. Therefore, new transceiver and networks need to be developed in order to meet these demands. The high processing power and software reconfigurability will be one of the key requirements of such systems. FPGAs appear to be effective solutions where new physical and network layer protocol and algorithms can be implemented in an efficient manner. This presentation will outline some of our developments in these areas. A few FPGA designs for next generation mobile communication as well as the use of FPGA to support a new paradigm shift in networking, called Software Defined Networking (SDN), will be presented. Peter Trott, MicroSemi Preventing Overbuilding and Cloning of Electronic Systems - Secure Production Programming Cloning or overbuilding is not new but it is a real problem in the global manufacturing of electronics. Preventing the theft of very valuable IP which is designed into FPGAs is both an engineering challenge as well as a business critical issue. This presentation fits into the security aspect of the day s meeting and shares technical solutions to secure your FPGA architecture from overbuilding. The speaker will describe a design flow, the software interface and Hardware Security Modules (HSM) made available in MicroSemi s SmartFusion and Igloo2 families. Roger May, Altera (now part of Intel) Easing Functional Safety Certification with Pre-Certified FPGA Tool Flows (IEC 61508)

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