Network Event Bulletin

Transcription

1 Network Event Bulletin FPGA Network Meeting : Moving Beyond RTL University of Hertfordshire, 21 st January 2015 The first FPGA Network meeting of the year was kindly hosted by the Engineering and Technology Faculty of the University of Hertfordshire in Hatfield. In their well-equipped auditorium around 50 NMI Members and invited guests heard a full day of talks and discussions, focussing on the question, Is High-Level Synthesis ready for the mainstream? This bulletin summarises the main discussions points and conclusions reached during the meeting. About NMI NMI is the champion for the UK Electronic Systems and Technology Industry Our mission is to help make the UK a leading location for electronic systems and technology businesses. We aim to support our members short-term priorities and our industry s long-term needs. Our work covers the skills agenda, operational excellence, innovation, investment, and representation. NMI believes the industry in the UK & Ireland needs outstanding engineering skills to succeed. Every event we do is aimed at providing valuable information for engineers and managers to learn from peers, build understanding of The state of the art and debate approaches to current challenges. We maintain Technical Networks of industry professionals and leading academics covering most of the common electronic engineering disciplines. All our Networks events are free to members and invited guests. We look forward to welcoming you as part of the growing NMI community for details see NOTE: All presentations are available as pdfs via the Members Only areas of All enquiries from non-members should be made to Doug Amos at doug.amos@nmi.org.uk

2 Moving Beyond RTL Since it burst onto the scene via a myriad of start-ups and ideas, Electronics System Level (ESL) design has coalesced into two distinct application domains, these being Modelling and Implementation, as shown on an old Synopsys slide I resurrected from a previous NMI event. ESL Modelling of systems for the purposes of test and verification has definitely reached mainstream and in most teams, chip verification employs high-level models at the transaction-level based on well-established standards. ESL Implementation, requires that the model itself becomes the golden source for the rest of the Synthesis and P&R flow. Whether that model is created in a block-based tool, such as Simulink from The Mathworks, or is created using a software language, often C or a derivative; High-Level Synthesis (or HLS) lies at the heart of that flow. Most would agree that ESL Implementation has not gained such wide acceptance as ESL Modelling, and the slow emergence of a mainstream HLS tool is often cited as the culprit; but is that fair, and is it finally an outmoded opinion? Our introductory discussion, very ably led by Alex Grove of FirstEDA and Dr. David Thomas of Imperial College, gave us a Short History of HLS and explained some of the fundamental concepts within HLS, and the path taken by HLS technology to reach today s state of the art. The first question tackled was What is HLS? and most presenters returned to that question during the day, however, Alex s slide below gives a succinct answer. Alex recommended the so-called Blue Book of HLS as a good guide, and details of this book are given on page 6 of this bulletin. 2

3 In addition, David and Alex highlighted that historically and even today, different HLS tools appear to target different types of user. For example, some tools might be useful for software teams who want to use FPGA to create bespoke hardware accelerators by retargeting their OpenCL inner loops. David in turn explained that although HLS has been developed for decades, it is still a subject of much academic research, as described on the slide below. _ 3

4 To give a current user s perspective, Andy Nicol came from Edinburgh to explain how HLS enables widespread use of a Model-Driven Engineering (MDE) flow at Selex ES. Andy explained that Selex ES have successfully employed an MDE approach for many years; modelling and implementing complex closed-loop control systems and signal processing algorithms. MDE allows Selex to implement digital electronics in FPGA via an HLS-based flow including tools from The Mathworks and Xilinx. However, this is part of a larger integrated MDE methodology which also includes mechanical, software and other constituents of highly integrated systems. Andy also raised the important point that HLS should not merely be seen as a stand-alone, push-button replacement for RTL synthesis, but as part of an integrated in-house workflow. 4

5 _ During the morning break, attendees were able to view demonstrations from sponsors Synopsys and Calypto, and to carry on discussions started during the first session. Then, back in the auditorium, we were welcomed by our host for the day; Prof. Reza Sotudeh, Dean of the faculty of Engineering and Technology at the University of Hertfordshire. Prof. Sotudeh kindly addressed us regarding the faculty s milestones to date, informing us that his was probably the largest engineering and technology faculty of any educational establishment in the country. _ Next, it was the turn of three leading HLS tool providers to give us technical details and demonstrations of the latest commercially available tools. Firstly, Richard Langridge of Calypto (re)introduced us to Catapult 8.0, giving insights into how an untimed behavioural description written in C, C++ or even SystemC can be synthesised into cycle-accurate and timed RTL, ready for the rest of the FPGA tool chain. The secret sauce of today s HLS is the powerful scheduling capability, and automated selection of optimum micro-architectures for a given behavioural requirement. Richard explained that scheduling breaks an operation over one or more clock cycles in order to meet timing and implementation constraints, as shown in the slide below. Richard also talked about how selecting a different architecture for a function can remove sub-optimal objects from the design to avoid these becoming performance bottlenecks. This sparked some interesting discussion around the presence (or not) of memory blocks in architectures having a significant effect that would make the HLS scheduler s work harder than necessary. Richard mentioned that over 1000 tape-outs had already occurred through Catapult, targeting either FPGA or SoC/ASIC implementations; sometimes both. Given this impressive number, it may be that the answer to the question about HLS being ready for mainstream is that it has already been ready for some time! 5

6 Reference was again made to the HLS Blue Book which gives some generic guidelines on how best to describe and constrain high-level behaviours, allowing tools such as Catapult the most freedom to optimise and schedule the implementation of the design. The blue book reference is as follows... Title: High-Level Synthesis Blue Book Author: Michael Fingeroff Publisher: Xlibris (21 May 2010) Language: English ISBN-10: ISBN-13: Available on amazon for around 22 _ HLS Scheduling was also apparent in the next presentation/demonstration from Sergei Storojev, who joined us from Xilinx in Grenoble. The recent addition of HLS to the Vivado tool suite has brought it within the reach of many new users, targeting solely Xilinx devices, of course. Sergei reiterated Richard s assertion that HLS is going mainstream by declaring that Vivado-HLS was already in use on over 1000 known FPGA design starts worldwide, across a wide variety of applications. Of particular note in Sergei s demonstration was Xilinx s use of the IP-XACT standard to provide tight integration between Vivado-HLS and the rest of the Vivado suite. This allows C to be used to quickly create IP for reuse within a larger design comprised of RTL and blocks from other sources. Perhaps this will engender a new surge in FPGA IP quality and availability. The advent of Zynq All-programmable Devices from Xilinx, with their embedded dual ARM Cortex-A9 System, has as increased the interest in having a single language for entry of both the hardware and embedded software, which raised again the idea of software people creating hardware. 6

7 There were some wry comments in the audience about the differences in approach between software engineers and hardware engineers at this point, with representatives of both communities in the audience, however, underlying this banter was the understanding that writing and optimising C++ to run in a multi-threaded multicore CPU subsystem required a somewhat different approach to writing and optimising C++ for implantation in FPGA. As was asserted by Cadence in a later presentation, the target algorithm may be the same, but the implementation has different priorities specifically regarding the Interface specification, memory/data flow, organization and storage. The verification methods are also significantly different. In fact, David Thomson, himself originally a computer scientist, educated many in the room by declaring that software engineers don t actually see C as a high-level programming language these days, many having moved on to Java and other high-level coding methods. Whatever the HLS language adopted, the need for training in how to write good C for FPGA was highlighted, and reference was made to online resources such as UG902 from Xilinx and training courses from third-party providers such as Doulos. After further networking and discussions through lunch, the first presentation after the break, the oft-shunned graveyard session, was taken by Doug Amos of NMI. Doug highlighted some of the results from NMI s recent FPGA Usage Survey of UK and Ireland. Of particular note here was the result (shown in the slide below) that RTL remains the dominant entry method, however, around a quarter of the respondents are also using Model-driven, or High-level methods. Doug pointed out that further analysis of the survey results could be found in New Electronics, in the NMI yearbook, and soon at the UK Verification Futures Conference, at which NMI would present a different subset of the results. For reference, the NMI Yearbook has just been released and is available to members and nonmembers at 7

8 The final state-of-the-art presentation was from Jan Jezek of Cadence, another of our international speakers. Jan reiterated the need for HLS and its core benefits over RTL-only approaches, whilst highlighting the demarcation between those tasks performed by the HLS tool, and those which the user is still required to do, as illustrated in the slide below. Jan also emphasised the importance of having correct characterisation of the target technology (in this case FPGA). For scheduling to work, the HLS tool needs to understand the performance possible in the target FPGA. Whereas this can be done by statistically modelling different elements of the FPGA and allowing a margin for the probable routing delays, in the case of Cadence s C2S tool, this is provided by calling the FPGA-specific P&R tool under-the-hood via the FPGA-vendor s own Application Programmers Interface (API). The last session of the day was an open discussion of how those present might move beyond RTL with some excellent ideas and insights from the assembled NMI members and guests; the main points being summarised as follows... We absolutely have to move beyond RTL, this is driven by design complexity. The dominant reason to use HLS is to reduce time taken to complete designs. Most (but not all) present would tolerate that their design consume more FPGA resources as a result of HLS but we did not explore by how much. It is not recommended to trial HLS by simply retargeting some existing C code, perhaps ones favourite.c file from a Raspberry Pi. In fact one of the dangers of more widespread access to HLS provided by Vivado- 8

9 HLS and other tools is that users may try exactly that, and be disappointed with the results, thus stifling some of the uptake of HLS. One should start small, perhaps with an algorithmic block, rather than try to write the whole design in C++ or model-based design. Explore different design architectures at the earliest stage of the design. The wrong choice of architecture is seldom overcome by any amount of button pushing in the HLS tool (as has always been the case RTL as well, of course). Seek training online, via the blue book or other sources. It was clear that many on the room would have liked to have continued the discussion but the Home-counties rush hour beckoned and the meeting was adjourned on time. Attendees and others are encouraged to keep the conversation going on the LinkedIn group FPGA-EIRE-UK. Next FPGA Network Meeting: What Next After Flicking the Switch? Wednesday May 20 th, Venue t.b.d. So, we ve got that great design entered into the tools; it s verified and passing though P&R without timing errors. Everything is running to schedule but now comes the really exciting part. We get to download our design into a live FPGA. We release Reset and hold our breath. Now what? There may well be as many different approaches to bringing up and debugging designs In-Lab and In-System as there are FPGA design teams. Each of those approaches may use a different combination of tools on the bench and each has its own advantages but also probably have areas that could be improved. By pooling our experiences in the NMI FPGA Network, we can each learn some new best-practises and accelerate this somewhat unpredictable stage of our FPGA projects. If your manager has ever asked you why it takes so long to get that (expletive deleted) FPGA working, then this might be the right session for you. 9