NLAS323. Dual SPST Analog Switch, Low Voltage, Single Supply A4 D

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1 Dual SPST Analog Switch, Low Voltage, Single Supply The NLAS323 is a dual SPST (Single Pole, Single Throw) switch, similar to /2 a standard 466. The device permits the independent selection of 2 analog/digital signals. Available in the US package. The use of advanced.6 micron CMOS process, improves the R ON resistance considerably compared to older higher voltage technologies. On Resistance is 2 Typical at 5. V Matching is <. Between Sections 2. to 6. V Operating Range Ultra Low < 5. pc Charge Injection Ultra Low Leakage <. na at 5. V, 25 C Wide Bandwidth > 2 MHz, 3. db 2 V ESD (Human Body Model) Ron Flatness 6. at 5. V US Package Independent, Positive Enable Pb Free Package is Available* US US SUFFIX CASE 493 A4 = Device Code D = Date Code MARKING DIAGRAM A4 D PIN ASSIGNMENT NO 2 COM 3 IN2 NO 4 GND 5 NO2 COM 2 7 IN 6 7 COM2 IN IN2 3 6 COM2 GND 4 5 NO2 FUNCTION TABLE On/Off Enable Input State of Analog Switch Figure. Pinout L H Off On ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 24 February, 24 Rev. 6 Publication Order Number: NLAS323/D

2 MAXIMUM RATINGS Symbol Parameter Value Unit DC Supply Voltage.5 to 7. V V I DC Input Voltage.5 to 7. V V O DC Output Voltage.5 to 7. V I IK DC Input Diode Current V I < GND 5 ma I OK DC Output Diode Current V O < GND 5 ma I O DC Output Sink Current 5 ma I CC DC Supply Current per Supply Pin ma I GND DC Ground Current per Ground Pin ma T STG Storage Temperature Range 65 to 5 C T L Lead Temperature, mm from Case for Seconds 26 C T J Junction Temperature under Bias 5 C JA Thermal Resistance (Note ) 25 C/W P D Power Dissipation in Still Air at 5 C 25 mw MSL Moisture Sensitivity Level F R Flammability Rating Oxygen Index: 2 to 34 UL 94 in V ESD ESD Withstand Voltage Human Body Model (Note 2) Machine Model (Note 3) Charged Device Model (Note 4) > 2 > 5 N/A V Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions.. Measured with minimum pad spacing on an FR4 board, using mm by inch, 2 ounce copper trace with no air flow. 2. Tested to EIA/JESD22 A4 A. 3. Tested to EIA/JESD22 A5 A. 4. Tested to JESD22 C A. RECOMMENDED OPERATING CONDITIONS Symbol Characteristics Min Max Unit Positive DC Supply Voltage 2. V V IN Digital Input Voltage (Enable) GND V V IO Static or Dynamic Voltage Across an Off Switch GND V V IS Analog Input Voltage (NO, COM) GND V T A Operating Temperature Range, All Package Types C t r, t f Input Rise or Fall Time, V cc = 3.3 V +.3 V (Enable Input) V cc = 5. V +.5 V 2 ns/v DEVICE JUNCTION TEMPERATURE VERSUS TIME TO.% BOND FAILURES Junction Temperature C Time, Hours Time, Years,32, , , , , , 2. 4,9. NORMALIZED FAILURE RATE FAILURE RATE OF PLASTIC = CERAMIC UNTIL INTERMETALLICS OCCUR T J = 3 C T J = 2 C T J = C T J = C TIME, YEARS Figure 2. Failure Rate vs. Time Junction Temperature T J = 9 C T J = C 2

3 DC CHARACTERISTICS Digital Section (Voltages Referenced to GND) Guaranteed Max Limit Symbol Parameter Condition 55 to 25 C <5 C <25 C Unit V IH V IL I IN Minimum High Level Input Voltage, Enable Inputs Maximum Low Level Input Voltage, Enable Inputs Maximum Input Leakage Current, Enable Inputs V IN = V or GND V to V A V V I CC Maximum Quiescent Supply Current (per package) Enable and VIS = or GND.. 2. A DC ELECTRICAL CHARACTERISTICS Analog Section Guaranteed Max Limit Symbol Parameter Condition 55 to 25 C <5 C <25 C Unit R ON Maximum On Resistance (Figures 2) V IN = V IH V IS = to GND I Is I = <.ma R FLAT(ON) On Resistance Flatness V IN = V IH I Is I = <. ma V IS = V, 2 V, 3.5 V I NO(OFF) Off Leakage Current, Pin 2 (Figure 3) I COM(OFF) Off Leakage Current, Pin (Figure 3) V IN = V IL V NO =. V, V COM = V or V COM =. V and V NO V V IN = V IL V NO = V or. V V COM =. V or V na. na AC ELECTRICAL CHARACTERISTICS (Input t r = t f = 3. ns) Guaranteed Max Limit 55 to 25 C <5 C <25 C Symbol Parameter Test Conditions (V) Min Typ Max Min Typ Max Min Typ Max Unit t ON Turn On Time R L = 3 C L = 35 pf (Figures 4, 5, and 3) t OFF Turn Off Time R L = 3 C L = 35 pf (Figures 4, 5, and 3) ns ns 25, VCC = 5. V C IN C NO or C NC C COM(OFF) C COM(ON) Maximum Input Capacitance, Select Input Analog I/O (switch off) Common I/O (switch off) Feedthrough (switch on). 2 pf 3

4 ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted) Limit Symbol Parameter Condition V 25 C Unit BW Maximum On Channel 3dB Bandwidth V IS = dbm 3. 9 MHz or Minimum Frequency Response V IS centered between and GND (Figures 6 and 4) 2 22 V ONL Maximum Feedthrough On Loss V IS = khz 3. 2 db V IS centered between and GND (Figure 6) 2 2 V ISO Off Channel Isolation f = khz; V IS =. V RMS db V IS centered between and GND (Figures 6 and 5) Q Charge Injection V IS = to GND, F IS = 2 khz 3..5 Enable Input to Common I/O t r = t f = 3. ns 3. pc R IS =, C L = pf Q = C L * VV OUT (Figures 6 and 6) THD Total Harmonic Distortion F IS = 2 Hz to MHz, R L = Rgen = 6, C L = 5 pf % THD + Noise V IS = 3. V PP sine wave.5 V IS = 5. VPP sine wave (Figure 7) LEAKAGE (pa).e+5.e+4.e+3.e+2.e+.e+.e.e 2.E 3.E 4.E 5.E 6.E 7 55 I COM(ON) I COM(OFF) I NO(OFF) TEMPERATURE ( C) Figure 3. Switch Leakage vs. Temperature 4

5 NO DUT COM Input V 5% 5%. F 3 V OUT 35 pf V OH 9% 9% Output Input V OL t ON t OFF Figure 4. t ON /t OFF NO DUT COM 3 V OUT Input V VOH 5% 5% 35 pf Output Input V OL t OFF % t ON % Figure 5. t ON /t OFF 5

6 Reference DUT 5 Generator COM NO Transmitted 5 Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth of an On switch. V ISO, Bandwidth and V ONL are independent of the input signal direction. V ISO = Off Channel Isolation = 2 Log V OUT for V IN at khz VIN V ONL = On Channel Loss = 2 Log V OUT for V IN at khz to 5 MHz VIN Bandwidth (BW) = the frequency 3. db below V ONL Figure 6. Off Channel Isolation/On Channel Loss (BW)/Crosstalk (On Channel to Off Channel)/V ONL DUT NO COM V IN GND C L V IN Output Off On Off V OUT Figure 7. Charge Injection: (Q) 6

7 7 6 = R ON ( ) = = 3. = V COM (VOLTS) R ON ( ) C 25 C C 5 C V IS (VOLTS) Figure. R ON vs. V COM and (@25 C) Figure 9. R ON vs. V COM and Temperature, = 2. V C 3 2 R ON ( ) C 25 C 25 C 5 C R ON ( ) C 25 C 5 C V COM (VOLTS) V COM (VOLTS) Figure. R ON vs. V COM and Temperature, = 2.5 V Figure. R ON vs. V COM and Temperature, = 3. V C 55 C R ON ( ) C 5 C TIME (ns) t ON V COM (VOLTS) t OFF (V) Figure 2. R ON vs. V COM and Temperature, = V Figure 3. Switching Time vs. Supply Voltage, T = 25 C 7

8 Bandwidth (On Loss) BANDWIDTH (db/div) Phase (Degrees) = 5. V T A = 25 C 5 PHASE (Degrees) OFF ISOLATION (db/div) 5 = 5. V T A = 25 C.. 3 FREQUENCY (MHz).. FREQUENCY (MHz) 3 Figure 4. ON Channel Bandwidth and Phase Shift Over Frequency Figure 5. Off Channel Isolation = 5. V Q (pc)...6 = 3. V THD (%) 3.3 V.4.2. V V COM (V). FREQUENCY (Hz) Figure 6. Charge Injection vs. V COM Figure 7. THD vs. Frequency DEVICE ORDERING INFORMATION Device Nomenclature Device Order Number Circuit Indicator Technology Device Function Package Suffix Package Shipping NLAS323US NL AS 323 US US 7 mm (7 ) 3 / Tape & Reel NLAS323USG NL AS 323 US US (Pb Free) 7 mm (7 ) 3 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD/D.

9 PACKAGE DIMENSIONS US US SUFFIX CASE ISSUE A X A 5 Y B L 4 G P C T K SEATING D PLANE. (.4) M T X Y R. (.4) V J DETAIL E S U T H N F DETAIL E R. TYP M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURR. MOLD FLASH. PROTRUSION AND GATE BURR SHALL NOT EXCEED.4 MM (.55 ) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTER LEAD FLASH OR PROTRUSION. INTER LEAD FLASH AND PROTRUSION SHALL NOT E3XCEED.4 (.55 ) PER SIDE. 5. LEAD FINISH IS SOLDER PLATING WITH THICKNESS OF MM. (3 ). 6. ALL TOLERANCE UNLESS OTHERWISE SPECIFIED ±.5 (.2 ). MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G.5 BSC.2 BSC H.4 REF.6 REF J K....4 L M 6 6 N 5 5 P R S U V.2 BSC.5 BSC 9

10 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 27 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2 9 Kamimeguro, Meguro ku, Tokyo, Japan 53 5 Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. NLAS323/D

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