Modular Performance Analysis

Transcription

1 Modular Performance Analysis Lothar Thiele Simon Perathoner, Ernesto Wandeler ETH Zurich, Switzerland 1

2 Embedded Systems Computation/Communication Resource Interaction 2

3 Models of Computation How can we classify and compare them? stepwise refinement concurrency hierarchy incremental design beauty modular simple safe accuracy expressive tools formal compositional easy to use efficient executable scope implementation scalable 3

4 Why is it difficult? Many aspects can not be quantified. Models cover different scenarios: B A C D 4

5 Intention Compare models and methods that analyze the timing properties of distributed systems. MAST SymTA TIMES MPA 5

6 Approach Define a set of benchmark examples that cover common area (obligatory) Define benchmark examples that show the power of each method (free style) Leiden Workshop on Distributed Embedded Systems: 6

7 MAST Wait another 20 minutes... 7

8 SymTA/S Based on classical RT analysis (periodic, jitter). Simplified relations and adaptors in order to achieve modularity. Computation and Communication 8

9 SymTA/S Based on classical RT analysis (periodic, jitter). Simplified relations and adaptors in order to achieve modularity. 9

10 TIMES/UPPAAL Models are based on Timed Automata. periodic stream fixed priority scheduling 10

11 Modular Performance Analysis (MPA) Processor Input Stream Concrete Instance Abstract Representation Task Service Model t D Load Model Abstract Component Model 11

12 Abstract Stream Model Event Stream events number of events in in t=[ ] ms 2.5 t [ms] t Arrival Curves D events a maximum / minimum arriving events in any interval of length 2.5 ms a 2.5 D [ms] 12

13 Load Model - Examples periodic periodic w/ jitter periodic w/ burst complex 13

14 Process Abstraction Formal Specification Program Analysis Data Sheets... b Task Cach e [b] [] e Functional Unit Automaton triggering event b/[15,15]/e * a/[10,10]/d min/max resource demand b/[5,5]/e b/[15,15]/e a/[5,5]/d produced event c/[3,20]/d a/[10,10]/d c/[3,20]/d 14

15 Service Model (Resources) Resource Availability availability available service in t=[ ] ms 2.5 t [ms] t Service Curves maximum/minimum available service in any interval of length 2.5 ms service b b D D [ms]

16 Service Model - Examples Load Model Service Model abstract component full resource bounded delay TDMA resource periodic resource 16

17 What kind of resources can be modeled? Memory (buffer space) Delay (end-to-end delay / processing and waiting) Computation Communication Energy 17

18 Processing Model (HW/SW) HW/SW Components Processing semantics and functionality of HW/SW tasks Abstract Components a HW/SW Task RTC b a t D 18 Predicate Ψ

19 Scheduling and Arbitration Components FP/RM EDF RR GPC EDF RR GPC GPS TDMA share TDMA GPC GPC GPC sum GPC 19

20 What kind of resource usage can be modeled? Different resource sharing strategies EDF TDMA Fixed Priority GPS Different processing semantics Greedy Processing Greedy Shaper Blocking 20

21 Complete System Composition CPU BUS DSP RM TDMA TDMA GPC GPC GSC GPC GPC GPC 21

22 Basic Concepts for Describing Activations AND OR 22

23 Free Style S1 S2 S3 S6 ECU1 CC1 BUS CC3 ECU3 6 Real-Time Input Streams - with jitter - with bursts - deadline > period 3 ECU s with own CC s S4 S5 ECU2 CC2 13 Tasks & 7 Messages - with different WCED 2 Scheduling Policies - Earliest Deadline First (ECU s) - Fixed Priority (ECU s & CC s) Total Utilization: - ECU1 59 % - ECU2 87 % - ECU3 67 % - BUS 56 % 23 Hierarchical Scheduling - Static & Dynamic Polling Servers Bus with TDMA - 4 time slots with different lengths (#1,#3 for and CC1, Networks #2 for Laboratory CC3, #4 for CC3

24 ... and its Abstract Component Model CPU ECU1 BUS PS S1 T1.1 C1.1 TDMA CC1 ECU3 T1.2 PS CPU T1.3 C1.2 S2 S3 T2.1 T3.1 C2.1 C3.1 CC3 PS T2.2 T3.3 C3.2 T3.2 S6 T6.1 EDF S4 CPU T4.1 ECU2 C4.1 CC2 T4.2 S5 T C5.1 T5.2

25 Buffer Requirements S1 S2 S3 S4 S5 CPU T2.1 T3.1 T3.3 CPU T4.1 T5.1 PS 3 T1.1 ECU1 C1.1 5 T ECU2 TDMA C2.1 C BUS CC C4.1 C5.1 C1.2 C3.2 CC2 3 CC ECU3 T1.2 T3.2 5 PS PS CPU T2.2 EDF T4.2 T5.2

26 Delay Guarantees CPU PS ECU1 BUS TDMA ECU3 PS CPU S T1.1 T1.3 C CC1 C1.2 T S2 S3 S4 T2.1 T T3.3 CPU T4.1 ECU C2.1 C3.1 C4.1 CC3 C3.2 CC2 T PS T2.2 EDF T4.2 S5 T C5.1 T5.2

27 Interface-Based Design MPA is suited for interface-based design Stepwise refinement Inverse relations because of min-+ algebra Assume/Guarantee by means of partial order 27

28 Intention Compare models and methods that analyze the timing properties of distributed systems. MAST SymTA TIMES MPA 28

29 Benchmarks Pay Burst Only Once Cyclic Dependencies Variable Feedback AND/OR task activation Intra-context information Workload Correlation Data Dependencies 29

30 Benchmark 1 Pay Bursts Only Once 0 J 70ms 30

31 Benchmark 1 100s < 1s simulation (10000 events) 31

32 Benchmark 2 Cyclic Dependencies 0 J 50ms T3 T3 32

33 Benchmark 2-1 : T1 high β 1 β 2 T1 T2 T3 33

34 Benchmark 2-2 : T3 high β 1 β 2 T3 T2 T1 34

35 Benchmark 3 Variable Feedback 4 J 30ms 35

36 Benchmark 3 : T1 high for each step in binary search: 50 minutes 36

37 (Expected) Results Understand the modeling power of different models and the relation between models and analysis accuracy. Improve methods by combining ideas and abstractions. Not: competition

38 In models for timed systems abstraction matters Knowledge about MoCCs that (also) talk about resource usage are far less understood 38