CHAPTER 5 DIGITAL REALIZATION OF PID CONTROLLER AND INVERSE PARK S TRANSFORMATION

Transcription

1 43 CHAPTER 5 DIGITAL REALIZATION OF PID CONTROLLER AND INVERSE PARK S TRANSFORMATION 5. INTRODUCTION Proportional Integral Derivative (PID) controller is one of the most common types of feedback controllers that are used in dynamic systems (Gopal 2003). This controller has been widely used in many different areas, such as aerospace, process control, manufacturing, robotics, automation and transportation systems. Implementation of PID controllers has gone through several stages of evolution from early mechanical and pneumatic designs to microprocessor-based systems. Recently, FPGAs have become an alternative solution for the realization of digital control systems. FPGA based controllers offer advantages such as high speed, complex functionality and low power consumption which were previously dominated by general-purpose microprocessor systems (Samet et al 998). These are attractive features from the embedded system design point of view. Previous work has reported the use of FPGAs in digital feedback control systems, such as Pulse Width Modulation (PWM) inverters (Jung et al 999), control of induction motors (Ferreira et al 2003), AC/DC converters (Zumel et al 2002) and variablespeed drives (Ricci and Le-Huy 2002). Another advantage of FPGA-based platforms is their capability to execute concurrent operations, allowing parallel architectural design of digital controllers (Zumel et al 2002).

2 44 Conventional implementation of FPGA-based controllers has not focused much on optimal use of hardware resources. These designs usually require a large number of multipliers and adders, and do not efficiently utilize the memory-rich characteristics of FPGAs. In the previous work (Chen et al 2000), the multiplier-based PID controller block takes up as much as 740 logic cells (LCs) or 64% utilization of the chip. Each LC contains a four-input Look-Up Table (LUT), a programmable flip-flop (FF) with a synchronous enable, a carry chain, and a cascade chain (Altera 2007). In the first part of this chapter, the design and digital realization of an efficient PID controller with anti-windup is presented. Based on the LUT scheme, the proposed PID controller reduces the cost of the FPGA design by enabling the chip to accommodate more logic and arithmetic functions while requiring less power consumption. Second part of the chapter discusses the digital realization of inverse Park s transformation using COordinate Rotation DIgital Computer (CORDIC) algorithm. 5.2 CONVENTIONAL PID CONTROLLER Controllers are often used to stabilize or improvise the response of a control system. The output of PID controllers will change the response of a system to a change in measurement or set point. A PID loop always adds its result to the current output, so that it effortlessly floats to a new steady output level. In digital control systems, simply increasing the number of bits can increase the accuracy of a digital compensator. The use of digital systems is cost effective even for small control systems. Another advantage offered by digital control is the flexibility of modifying the controller characteristics or of adapting the controller if plant dynamics change with operating conditions.

3 45 The general PID controller expression is, de( t) c( t) K e( t) K e( t) dt K (5.) p c r dt where c(t) = output of the controller, e(t) = error signal, K p = proportional gain, K c = K p /T i = integral gain, K r = K p.t d = derivative gain, T i = integral time constant and T d = derivative time constant. A proportional control (K p ) will have the effect of reducing the rise time. An integral control (K c ) will have the effect of eliminating the steadystate error, summing even a small error over time, produces a drive signal large enough to move the system towards a smaller error but it may make the transient response worse. A derivative control (K r ) will have the effect of increasing the stability of the system, reducing the overshoot and ringing and also improving the transient response. The PID controller, being a suitable combination, helps to get the output in a short time, with minimal overshoot and little error. Referring to Figure 5., the controller compares a measured value from a process (Vsensor) with a set point value (Vset). The error signal (Verror) is used to calculate a correction to the input variable of the process so that the correction will remove error in the output.

4 46 Figure 5. General block diagram of PID controller 5.2. Integrator wind up Integrator wind up is a phenomenon of interaction between integral action and saturation. For a control system with wide range of operating conditions, it may happen that the control variable may reach the actuator limits. When this happens, the feedback loop is broken and the system runs as an open loop system because the actuator will remain at its limit, independent of the process output. The integrator continually integrates the error signal, which may become very large or colloquially it winds up. If the controlled process has a positive gain and if a positive set-point change occurs, then controller will try to reduce the error between set point and the output, which is initially positive. The integral component will sum these positive errors to generate the necessary integral action. An overshoot occurs, whereupon the errors become negative. However, the direction of the control signal will not change to compensate if the sum of the positive errors occurred earlier, but dominates in which case the overshoot becomes prolonged. The direction of control action will change, only when the contribution of negative errors cancels the accumulated positive errors sufficiently. This phenomenon is known as integral windup or reset windup.

5 Concept of anti-windup Integrator windup can be avoided by making sure that the integral is kept at a proper value when the actuator saturates, so that the actuator avoids bouncing several times between high and low values and the controller is ready to resume action. This is accomplished by a technique called anti wind-up. There are four methods for dealing with windup in a controller:. Conditional Integration: If the controller output is saturated and input and output are of the same sign, then set integrator input to zero. 2. Limited Integration: If the integrator is saturated and controller input is of the same sign, then set integrator input to zero. 3. Tracking Anti Wind-up: If the controller output is saturated, reduce the integrator input by some constant times the difference between unsaturated and saturated controller output.

6 48 4. Modified Tracking Anti Wind-up: Limit integrator input by a constant times the sum of integral output (I(k)) and saturated proportional and derivative output (P(k) + D(k)) so that if either of those two components exceeds the limit, the integrator is off. In this work modified tracking anti-windup approach is followed. 5.3 DIGITAL PID CONTROLLER MODELING AND SIMULATION In a PID controller, the three different signal paths (P, I and D elements) are fed by input as shown in Figure 5.. To implement a continuous time control law given in Equation (5.) in a digital computer, the three paths are discretized as shown in Equations (5.2) to (5.4). The digital PID controller based on Equations (5.2) to (5.4) is shown in Figure 5.2. P(k) = K p.e(k) (5.2) I(k) = K i.(e(k)+e(k-)]+i(k-)) (5.3) D(k) = K d.(e(k) e(k -)) (5.4) T where K d = K r /T s, K i = K s c and T s is the sampling period. In Figure 5.2, 2 r(k) is the reference, f(k) is the feedback and c(k) is the output.

7 49 Figure 5.2 Block diagram of the proposed digital PID controller with anti-windup The anti-windup phenomenon in this controller is realized on the basis of actuator model. The actuator routes out the appropriate signal based on following criteria:. When the actuator reaches the saturation, the integral is cut off and the PD signal serves as the controller output. 2. When the input to the actuator goes below minimum, the controller output assumes the minimum value of zero. 3. When the actuator is in the linear region, the PID signal becomes the controller output. The controller output thus obtained is given to the process for further manipulations.

8 Derivation of controller constants The general PID controller expression in s domain is, G(s) K c K p K rs (5.5) s Equation (5.5) can be approximated as G(s) k(s a) s 2 (5.6) where K p = 2ak, K c = ka 2 and K r =k. The possible set of values of k and a, which satisfies maximum overshoot of less than 0% and above 5% and settling time (2% tolerance) of less than 2.6 seconds coupled with a plant having a transfer function,.2 g(s), are determined as 2.2 and 0.9 respectively s.86s 2.5s using Matlab script. Figure 5.3 shows these results and their corresponding overshoot and settling time as 7.72% and 2.29 seconds respectively. From these values of k and a, K p, K c and K r are calculated as 3.96,.782 and 2.2 respectively (Equation (5.6)). Further K p, K i and K d used in Equations (5.2) to (5.4) are calculated as 4, and 2200 (T s = ms) respectively. These values of K p, K i and K d are used to implement the digital PID controller. Figure 5.4 shows the step response of a system for three different cases namely, the system as uncompensated, compensated only for peak overshoot and compensated for peak overshoot and settling time constraints. The plant taken for this purpose is given in Equation (5.7), as

9 5.2 h(s) s.86s 2.5s (5.7) Figure 5.3 Result of Matlab script to calculate PID coefficients 5.4 DIGITAL REALIZATION OF PID CONTROLLER The rounded off controller constants determined from Matlab script are used to implement the PID controller in FPGA. Figure 5.5 shows the flowchart used for the digital realization of PID controller. The following points briefly discuss the algorithm adopted in the flowchart: The position of the motor is continuously monitored and taken as feedback signal. An optical encoder is used for this purpose.

10 52 The output of the optical encoder is read by the FPGA and by using suitable calibration the current speed of the motor will be calculated. The current speed will be compared with the reference speed using the comparator and the error will be found. Then the proportional and integral action will be calculated based on the error and the proportional and integral constants like K p and K i respectively. After the integral action is calculated, it will be checked for saturation. Here since a 6-bit PWM is proposed to be used if the value is exceeding or if it is negative then the integral output is reset. Then the PI action is calculated and again checked for saturation. If the value exceed then it will be saturated to 65536, otherwise if the value is negative the PI action is forced to zero. Figure 5.4 Step response of PID controller Simulink environment

11 53 Start read the output of the sensor and calculate the current speed read the reference speed False if ref_speed >= current_speed True error = current_speed - ref_speed dir = error = ref_speed - current_speed dir = 0 p_action = kp * error d_action = kd * (error - prev_error) i_action = ki * (error + prev_error) + prev_i_action prev_i_action = i_action prev_error = error i_action >= i_action <= 0 False Cont_ cont True Figure 5.5 Flowchart VHDL coding for the PID controller

12 54 cont cont_ i_action_mod = 0 i_action_mod = i_action control_action = p_action + d_action + i_action_mod False control_action >= True control_action <= 0 False flag = 0 True control_action_saturated = 0 flag = control_action_saturated = flag = flag == 0 False True control_action_saturated = control_action control_action_saturated to the next module end Figure 5.5 (contd.,) Flowchart VHDL coding for the PID controller The simulation result as obtained from Quartus II simulation is shown in Figure 5.6. In Figure 5.6, where control_action_saturated is the output variable. This will saturate to if the integrator gets into wind-up phenomenon. The signal max_hall_voltage (0 volts) is a constant used to store the maximum sensor voltage from the hall sensor when the machine is running at its rated speed which is given in the variable max_speed_srm

13 55 (4000 rpm). The current speed of the machine is calculated from the feed back signal namely fb_hall_voltage (7 volts). The speed at which the motor is expected to run is given in ref_speed (3000 rpm). The output of the PID controller is 0,836 which is to be fed as input to the next module of the complete control algorithm. The result is confirming to the analytical result as per the flowchart. Figure 5.6 PID controller simulation in Quartus II software 5.5 RESULT ANALYSIS The space, speed and power results obtained from the simulation and synthesis of digital anti-windup PID controller are compared with similar results proposed by Yuen Fong Chan et al (2007) in Table 5. and Samet et al (998) in Table 5.2. In Tables 5. and 5.2, the equivalent Logic Elements (LEs) are calculated based on the fact (Xilinx 2006) that each Xilinx s Configurable Logic Block (CLB) contains two Slices and Each Slice contains two 4 input LUTs (Logic Cells). The Logic Cell of Xilinx FPGA and Logic Element of Altera consists of one 4 input LUT each with minor difference in other logic. Hence the equation is each CLB is equivalent to 4.5 LEs (Altera 2007) and so each slice is equivalent to 2.25 LEs. A DPS block in an Altera

14 56 FPGA is a 9-bit by 9-bit multiplier. Figures 5.7 to 5.9 show the reports generated for the PID Controller program from the Quartus II software after the compilation, power analysis and timing analysis respectively. The space, power and speed results as can be found in Figures 5.7 to 5.9 are used for the comparison of the proposed architecture with earlier implementations. Figure 5.7 PID controller - Compilation report summary Figure 5.8 PID controller - Power analyzer report summary

15 57 Figure 5.9 PID controller Timing analyzer report summary Based on the comparison carried out in Table 5., the proposed architecture uses the lowest hardware resources and executes faster. This architecture which is inherently a parallel architecture was developed on a top-down modular approach using LUTs in the FPGA. Also this architecture was developed with structural style of modeling of the algorithm and was realized in an FPGA which has product-based logic. Due to these reasons, the proposed model could result in the best solution while the multiplier based architecture makes maximum use of hardware resources since it is based on the hardware multipliers present in the Spartan series of Xilinx FPGAs. Distributed Arithmatic (DA) based architecture is a bit serial computation algorithm that performs multiplication (using LUTs) has comparatively lower speed of execution due to the serial computation. For industrial control applications, speed and space demand suggests the proposed model with the added advantage of lowest power consumption. Table 5. Comparison of proposed PID controller with Yuen Fong Chan et al s proposals PID Controller Components Clock frequency Speed Power DA-based (6 bit) Multiplier-based (6 bit) Proposed model (32 bit) 437 Slices = 983 LEs 47 Slices = 258 LEs 47 ALUTs and nine 9-bit DSP blocks 47 MHz 36 ns 456 mw 5 MHz 67 ns 765 mw 50 MHz ns mw

16 58 Samet et al (998) have proposed three different architectures as listed in Table 5.2 for the digital realization of the PID controller without antiwindup compensation. They have used the form as given in Equation (5.8) while Yuen Fong Chan et al (2007) realized the PID controller in the same form as followed in this thesis work but in bit serial approach and multiplier based approach. The comparison of Samet et al proposals also suggests the proposed architecture to be a better solution for industrial control loop applications. C(k) C(k ) Ki Ki Kp Kd e(k) Kp 2Kd e(k ) Kde(k 2)) (5.8) 2 2 Table 5.2 Comparison of proposed PID controller with Samet et al s proposals PID Controller Components Hardware approach Speed Features Parallel architecture 52 CLBs = 2304 LEs Combinatorial operators 220 ns Faster execution Serial Architecture 76 CLBs = 792 LEs Two sequential logic operators 3360 ns Lower hardware resource Mixed Architecture 225 CLBs = 03 LEs Combinatorial operators with storage managed by FSM 660 ns Improved speed and cost reduction Proposed model 47 ALUTs and nine 9-bit DSP blocks Combinatorial operators in LUT approach ns High speed and lowest hardware resource

17 59 Masmoudi et al (997) have reported in their work, a PID controller that executes in.5 sec. This large time of execution is because the author tried out various approximations to obtain less space (with 3 multipliers and 7 adders). Another work reported by Jianyong Niu (2006) uses 383 LEs for a PI controller with 6-bit inputs and 32-bit output in an FPGA. The drawbacks of this work are, derivative action and anti wind-up phenomenon of the controller are not included. Lima et al (2006) have proposed a high end methodology for FPGA based PID controller implementation which offers advantages compared to custom-logic based designs. This methodology will be explored in the future works. The comparisons above conclude that the proposed architecture occupies less hardware resource, less power consumption and executes faster and is more suitable for control loops in industrial applications. 5.6 INVERSE PARK S TRANSFORMATION The Transformation of coordinates from the three phase balanced - - -q coordinate system (rotor reference frame). The inverse Park s transformation converts the two phase d-q - shows the transformation of d-q coordinate system into - system. These three transformations are used in the vector control of the AC machines such that the stator currents of the induction machine are separated into flux and torque-producing components and so facilitating the independent control of speed and torque as in DC motor control (Vas 998). Equations (5.9) and (5.0) are used for the inverse Park s transformation.

18 60 i = i d * cos - i q * sin (5.9) i = i d * sin + i q * cos (5.0) Figure 5.0 Transformation of d-q co-ordinate system into - co-ordinate system 5.7 CORDIC ALGORITHM CORDIC is an iterative algorithm for the calculation of rotation of two dimensional vectors in linear, circular and hyperbolic coordinate system, using only add and shift operations. The CORDIC algorithm has become a widely used approach for elementary functional evaluation when the silicon area is a primary constraint. Algorithm was written to calculate the sine and cosine values using shifts and adds, which was digitally implemented by Jack Volder called CORDIC. Through proper selection of scale factor, arc tangent radix and initial conditions, it is possible to determine the family of iterative equations involving shifts and adds to calculate trigonometric functions in a deterministic way (Andraka 998).

19 6 The trigonometric functions are based on vector rotations. CORDIC algorithm is of two operating modes, vectoring mode (VM) and rotation mode (RM). Its current applications are in the fields of digital signal processing, image processing, filtering, matrix algebra, etc.,. Different versions of CORDIC algorithm have been developed in order to increase the speed of computation of trigonometric functions. The speed enhancements in the algorithm have been achieved in diverse and creative ways (Jason Todd Arbaugh 2004). This work uses the classic CORDIC algorithm that utilizes small LUT and standard arithmetic functional units to perform calculations CORDIC algorithm for trigonometric functions Trigonometric functions are often used in embedded applications like filtering, motion control and waveform synthesis. For waveforms with few output points per cycle (for example one output point per degree), a lookup table will often suffice and indeed this method is optimal in that, it offers a reasonable compromise between speed and the need to use the microcontroller s memory efficiently. For waveforms with many output points per cycle (consider a waveform with 4096 points per cycle), the lookup table approach is often unfeasible because of the memory requirements. In the case of a waveform with 4096 output points per cycle, the lookup table alone would occupy at least 4kB of Flash and more often the table would take 8kB of memory. This precludes the use of such a lookup table approach on the lowest cost microcontrollers with their limited Flash memory.

20 62 It would appear from the above that, where many points are required on a waveform, it would be more practical to compute points on the waveform in real time when required and output them as they are computed. The CORDIC algorithm often offers the most elegant solution to the problem and it is astounding in its simplicity of implementation, efficiency and elegance. Inverse Park s Transformation involves the computations of sine and cosine values which is computed using CORDIC algorithm Mathematical background of CORDIC algorithm The CORDIC algorithm is used for finding out the position of the vector after rotation. With this basic principle of vector rotation, CORDIC algorithm can be efficiently used to calculate the values of sine and cosine functions. The unit vector, shown in Figure 5., y (Cos, Sin -x (, 0) x -y

21 63 Now consider a random unit vector with an initial rotation of angle i, y i ), then i (5.) i (5.2) the direction of rotation, the head of the vector will be at the summation (pos The new locations (x i+, y i+ ) are then found out from Equations (5.3) and (5.4). i + (5.3) i+ (5.4) Using the additive angle formulae for cosine and sine for rotating the vector in either direction and using Equations (5.) and (5.2), it is arrived that x y i i cos sin sin cos x y i i (5.5) Equation (5.5) is the standard two dimensional rotational equations which can be used to rotate any vector or group of vectors, with any initial rotation -2 ).

22 64 it becomes n, x y i i cos sin n n sin cos n n... cos sin sin cos. x y i i (5.6) The storage is reduced to a ROM table with n entries for sine and cosine values and makes the implementation of algorithm feasible. Now for each sub rotation Equation (5.6) involves 4 multiplications and 2 additions. The execution time is small for two additions when compared to four multiplications. Thereby Equation (5.6) could be rewritten to arrive at Equation (5.7) which reduces the number of multiplications to two. x y i i cos n tan n tan n... cos tan tan x y i i (5.7) The subsets of angles are to be selected for each sub rotation in order to minimize the calculation. In binary multiplication, multiplying by power of 2 is done easily by shifting the binary number to the correct number of positions to the left. It is possible to break the rotation into many steps, each of decreasing size and such that tan step) in each step The first eight steps of the set of rotations are shown in Table 5.3 to demonstrate the feasibility of this method. If the rotation steps are added up, it may be seen that the maximum total rotation is almost 00. Since the rotation

23 65 may be in a clockwise or counter clockwise direction, it is clear that these steps may be used to approximate any angle between (approximately) +00 and -00. Further, the decreasing size of the steps indicates that the approximation may be made arbitrarily accurate by increasing the number of steps of rotation. A small lookup table is used to store t step. The size of this table increases with log2 N where N is the number of steps of rotation. Table 5.3 The first eight rotational steps in the CORDIC algorithm ½ 0, ¼ / / / / / tan (2 -n ) so that a simple look up table as shown in Table 5.3 could be used and the value can be iteratively calculated with simple shift and add i is used to represent the sign of the current angle. For positive angle, the rotation is in negative direction while for negative angle, rotation i are {, 0,-}. With suitable substitution, Equation (5.7) becomes

24 66 x y i i n n cos(tan (2 ) n...cos(tan (2 ) n 2 2 n ) 2 2 ) x y i i (5.8) Let the scale factor K i = cos(tan - (2 -i i =0, K=. Equation (5.8) can now be written as i values x y i i K n... K n 2 n n 2 n ) ) x y i i (5.9) The value of K i in Equation (5.9) depends only on the number of steps used to approximate the total angle. If four steps are used to approximate the angle then K i is calculated as given in Equation (5.20). K i = cos( tan - (2-0 )) * cos(tan - (2 - )) * cos(tan - (2-2 )) * cos(tan - (2-3 )) = (5.20) number of steps. The same sequence may be used to calculate the value of K i for any To calculate the vector or angle iteratively, CORDIC algorithm uses the system of Equations (5.2) to (5.23) x i+ = x i i (2 -i ) y i (5.2) y i+ = y i + i (2 -i ) x i (5.22) z i+ = z i i (tan - (2 -i )) (5.23) i values are selected during each iteration of equations for values of residue angle z i i = for z i i = - for z i < 0.

25 67 As the rotation mode is used in this work, the value of angle z i is checked for each iteration. When z i becomes zero, the iteration is completed. In the case of vectoring mode, the value of y i is checked for each iteration and the iteration gets completed when y i becomes zero. 5.8 SIMULATION OF INVERSE PARK S TRANSFORMATION The following sections discuss the simulation procedures and results obtained from C coding, Matlab script and VHDL coding Simulation in C The realization of Inverse Park s Transformation using CORDIC algorithm is implemented using C language. The angle beta and the values of currents i d and i q are given - (2 -i ) is calculated and stored in an array of arctan table for every iteration. Then depending upon the sign of the residual angle, the values of sine and cosine are calculated. For normalization, the sine and cosine values are multiplied with a constant of K= (using 8 steps for the approximation of the angle).then the values of the currents i a and i b are calculated using the Equations (5.24) and (5.25). i a = x i+* i d - y i+* i q (5.24) i b =y i+* i d + x i+* i q (5.25) Figure 5.2 shows the flowchart for the implementation of inverse Park s transformation in C language.

26 68 START get the values of beta,id,iq initialize i=0 if i<000 False True arctantable[i]=atan(2 -i ) i=i+ False if i<000 True x i+ =x i +y i *2 -i y i+ =y i -x i *2 -i z i+=z i +arctantable[i] i=i+ True If beta<0 False x i+ =x i -y i *2 -i y i+ =y i +x i *2 -i z i+=z i -arctantable[i] i=i+ Normalize the result i a = x i+* i d - y i+* i q i b =y i+* i d + x i+* i q STOP Figure 5.2 Flowchart - Inverse Park s transformation in C

27 69 following: In Figure 5.2 the algorithm adopted is briefly described in the LUT for arctangent function is prepared with 000 values. The iterative algorithm given by Equations (5.2) to (5.23) is performed for 000 iterations with the input values of i d, i q and beta Simulation in Matlab Inverse Park s Transformation calculates i and i current values (stator reference frame) from the input currents i d and i q (rotor reference frame). The formula is implemented in Matlab script. The implemented algorithm for finding out the inverse Park s transformation is explained with the help of the block diagram as shown in Figure 5.3. The Matlab script includes the following functions for finding the inverse Park s transformation. InvPark, the main function takes i d, i q and theta as inputs. This main function calls cordic function which is used to carry out the CORDIC algorithm for the given theta value in 6 bits word length. The final values of this function as XD, YD and ZD which are respectively the cosine, sine and the residual angle are used to calculate the i and i values. CORDIC Cordic takes inputs as angle and i for iterations. It calls functions DtoB, RShift, BinSub, BinAdd and BtoD. K0 is the constant value calculated from K0=K0 *sqrt(+2 -(2i) ), with K0 initially assumed to be.0.

28 70 DtoB DtoB converts the decimal value to the binary value of 6 bits. X0, Y0, Z0 and Arctan values are calculated in binary from values.0/k0, 0.0, theta* /80 and atan(2 -i ) respectively. Rshift Rshift shifts the 6 bit data input to this function by i bits. This forms the binary shifting in the main equation. Xshift and Yshift are from the binary shifting of X i.2 -i and Y i.2 -i. Figure 5.3 Block diagram for inverse Park s transformation in Matlab

29 7 BinSub and BinAdd BinSub and BinAdd functions are used for subtracting and adding the X0, Y0, Z0, Yshift, Xshift and Arctan values as per the values of LSB of Z0. The values are stored in X, Y and Z respectively. When the number of iterations are completed the values are stored in X0,Y0 and Z0 from X,Y and Z respectively. BtoD BtoD function is used to convert the binary values into decimal. The X0,Y0 and Z0 values are converted into decimal and stored as XD,YD and ZD. i These functions are called by the main function InvPark and i and values are calculated using the formula given by i = XD.i d YD.i q i = YD.i d + XD.i q Simulation using VHDL Figure 5.4 shows the block diagram for inverse Park s transformation as realized using VHDL coding.

30 72 SC_CORPROC id iq X i P2R_CORDIC X i+ P2R_CORDIC Y i PIPE Y i+ X 0 Y 0 ia ib Figure 5.4 Block diagram for inverse Park s transformation in digital realization The whole algorithm is partitioned into three segments and each is coded in VHDL individually and finally integrated to get the complete algorithm. SC_CORPROC The angle program. The normalization constant is defined in this file. The sine and cosine values are calculated by the component P2R_CORDIC which takes angle as input. Then the inverse park s transformation is calculated and ia and ib values are found out. Table 5.4 lists the input and output ports used in the design.

31 73 P2R_CORDIC In this, a generate function is used which creates a shift register like structure to calculate the consecutive iterative values of sine and cosine functions. The current value obtained from P2R_CORDICPIPE is used in the calculation of the next value. P2R_CORDICPIPE This file stores the arctangent values in LUT form. The shifting and adding operations involved in CORDIC algorithm are performed in this file. Then the current value of sine and cosine is calculated and passed to P2R_CORDIC. Table 5.4 List of input/output ports for sine/cosine CORDIC core Port Width Direction Description CLK Input System Clock ENA Input Clock enable signal Ain 6 Input Angle input Sin 6 Output Sine output Cos 6 Output Cosine output All CORDIC Processor cores are built around three fundamental blocks, the pre-processor, the post-processor and the actual CORDIC core. The CORDIC core is built using a pipeline of CordicPipe blocks. Each CordicPipe block represents a single step in the iteration processes. Because of the arctan table used in the CORDIC algorithm, it converges in the range

32 74 of to + radians. To use the CORDIC algorithm over the entire 2 range, the input needs to be manipulated to fit in the to + radians range. This is handled by the pre-processor. The post-processor corrects this and places the CORDIC core s results in the correct quadrant. The CORDIC core is the heart of the CORDIC Processor Core. It performs the actual CORDIC algorithm. All iterations are performed in parallel, using a pipelined structure. Because of the pipelined structure, the core can perform a CORDIC transformation in each clock cycle. Thus ensures the highest throughput possible. Each pipe or iteration step is performed by the CordicPipe core. It contains the arctan table for each iteration and the logic needed to manipulate the X, Y and Z values. 5.9 SIMULATION RESULTS The following tables list the results obtained from the simulation of C, Matlab and VHDL codes Results of C Tables 5.5 and 5.6 show the results obtained for two sets of inputs. Figure 5.5 shows a sample snapshot of the result screen.

33 75 Table 5.5 Results from C for id=iq= id=iq= ia ib d e g r e e s Table 5.6 Results from C for id=iq=2 id=iq=2 sin cos ia ib d e g r e e s

34 76 Figure 5.5 Simulation result in C Results of Matlab Tables 5.7 and 5.8 show the results obtained for two sets of inputs. Figure 5.6 shows a sample snapshot of the result screen. Table 5.7 Results from Matlab for id=iq= id=iq= ia ib d e g r e e s

35 77 Table 5.8 Results from Matlab for id=iq=2 id=iq=2 sin cos ia ib d e g r e e s Figure 5.6 Simulation result in Matlab

36 Results of VHDL Table 5.9 shows the sine and cosine values obtained from CORDIC realization and Tables 5.0 and 5. list the results obtained for two sets of inputs. Table 5.9 sine and cosine values from VHDL 0 deg 30 deg 45 deg 60 deg 90 deg sin (hex format) cos (hex format) 0x0CC 0x3FFC 0x5A82 0x6EDC 0x8000 0x8000 0x6EDD 0x5A83 0x4000 0x0CC sin (decimal) cos (decimal) Table 5.0 Results from VHDL for id=iq= ia ib Angle Equi valent Actual Calcu lated Equi valent Actual Calculated

37 79 Table 5. Results from VHDL for id=iq=2 ia ib Angle Equi Calcu Actual valent lated Equivalent Actual Calculated Figures 5.7 to 5.9 display the simulation results obtained using Quartus II software for three different input angles. Figure 5.7 o

38 80 o o

39 8 5.0 COMPARATIVE ANALYSIS OF RESULTS The simulation results shown in Figures 5.7 to 5.9 handle the data in 6 bit format. To demonstrate the interpretation of results, sample calculation of the value of sin30 o is as explained below: 360 o 30 o o * (decimal) 555(hex format) Hence angle input is given as 555 in hexadecimal format. The core calculates the following value of sine for Zi=546: sin : 6380 (in decimal) = 3FFC (in hex format) The outputs represent values in the to + range. The results can be derived as follows: * Therefore the value of sin30 o obtained through the VHDL code is Similar interpretation is done for the cosine value and the output currents which are 6 bits wide. Table 5.2 lists a sample comparison of the results obtained from the three simulations with the theoretical values.

40 82 o Results Sine cosine ia ib Theory Matlab C VHDL Figures 5.20 to 5.22 show the compilation report summary, timing analyzer report summary and power analyzer report summary of the VHDL code. Figure 5.20 Compilation report Inverse Park s transformation

41 83 Figure 5.2 Timing analyzer report Inverse Park s transformation Figure 5.22 Power analyzer report Inverse Park s transformation From the compilation report, the total Logic Elements (LEs) used for the design is 907 with eight 9-bit DSP blocks. This is less compared to the conventional LUT based approach which normally requires large hardware resources, especially memory blocks, for the same accuracy (Chris Dick et al 2004, Kadam et al 2002). From the timing and power analyzer reports the design executes in 4.65 ns and dissipates mw. Ghariani et al (998) have reported in their work that CORDIC based Park s Transformation takes 3 sec for the execution. Hence the time of execution for the proposed design is less.

42 84 Results of FPGA based Park s transformation by Kharrat et al (2000), as shown in Table 5.3, reveal that the proposed architecture is a high speed and low cost design. Table 5.3 Results of Kharrat et al s (2000) proposals Approach Hardware resource Execution Time Remarks LUT based (28 points) 756 CLBs = 3402 LEs 520 ns Accuracy depends on the number of points LUT & Linear Interpolation method 092 CLBs = 494 LEs 782 ns Needs extra manipulation along with LUT for accuracy Mathematical Series based 648 CLBs = 296 LEs 52 ns Precision depends on the value of angle input and sine and cosine values are well defined only around zero CORDIC (rotation mode) 224 CLBs = 008 LEs 289 ns Minimum delay time and area with acceptable precision 5. CONCLUSION Resource savings are important in order to embed several PID controllers and other system components in the same FPGA. Resource savings are also an important factor in order to reduce the power dissipation and energy consumption which are important goals for embedded systems. In addition, due to the flexibility of using LUTs in FPGAs, the design method can be used to implement other algorithms such as adaptive control schemes. For the next generation of FPGAs in which A/D converters (ADCs) and D/A

43 85 converters (DACs) are built into the chip, the proposed PID controller architecture is more efficient in terms of hardware resources, power consumption and control performance when compared with the standard microcontroller Intellectual Property (IP) cores. This is due to the fact that custom-made logic can obviously outperform the general purpose microcontrollers. In the second part of this chapter, it is shown that VHDL results are as accurate as that of C and Matlab and it also confirms to the theoretical results with the major advantages of speed and space in digital realization of inverse Park s Transformation. Moreover, since the logic occupied compared to conventional LUT based approach is less the speed of execution is faster. In this work only inverse Park s transformation has been realized using CORDIC algorithm. The same may be extended to Park s transformation to make the optimal use of the limited hardware resources available in an FPGA for the complete vector control realization.