Keywords Double boost DC to DC Converter, integral-proportional control, PWM, ADC, FPGA. Fig1. Double Boost DC-DC converter Model

Transcription

1 Volume 3, Issue 9, September 2013 ISSN: X International Journal of Advanced Research in Computer Science and Software Engineering Research Paper Available online at: FPGA Implementation of Discrete IP+PWM Controller for Double Boost DC to DC Converter Swati Singh * Sandeep Gupta Neeraj Tiwari Sr. Lecturer, Dept. of ECE Asst.Prof, Dept. of ECE Prof.,Dept. of EE MIT,Meerut, India BIT,Meerut, India NIEM, Mathura, India Abstract The rising cost of electricity and environmental concerns have driven research in these renewable energy resources such as PV modules, fuel cells and wind energy etc. To get the stable and high output voltage from fuel cell or PV module, dc to dc boost converter is used. The output of this converter is then utilized by high voltage electric vehicles or to the inverter for grid and residential applications. To provide high voltages for HV electric vehicles, high step up dc to dc boost converter is required. In this paper, modelling, Simulation and implementation of discrete IP+PWM controller for double boost dc to dc converter are carried on FPGA. Keywords Double boost DC to DC Converter, integral-proportional control, PWM, ADC, FPGA I. INTRODUCTION The dc power is obtained from an existing power supply network or from a rotating alternator, a rectifier or a battery, fuel cell, photovoltaic array or magneto hydrodynamic generator. To control the output voltage or to get constant output voltage if input voltage is changing [1]. DC to DC converter is also used as an interface device between DC supply system and Load. There are a number of different topologies for DC-DC converters. These topologies are of three types: step down (buck), step up (boost), and step up & down (buck-boost). The buck topology is used for voltage step-down. The boost topology is used for stepping up the voltage. An increased boost factor suits the many emerging applications in the automotive industry, telecommunications industry, IT industry as well as power generation via fuel cells, photovoltaic arrays and wind turbines. The basic boost topology does not provide a high boost factor. This has led to many proposed topologies such as the tapped-inductor boost [2], cascaded boost and interleaved boost converters[3]-[5]. To control the duty cycle some methods such as fuzzy logic, sliding mode control and others [6] are available, a simple IP controller is used to verify the double -boost topology. To implement the control algorithm conventional digital controllers like microprocessor, microcontroller and DSP controller are used. The other hardware technique is FPGA based controllers[7]-[9]. In the proposed work, a discrete IP+PWM controller is implemented on FPGA for double boost dc to dc converter. II. DOUBLE BOOST CONVERTER MODEL Fig. 1 shows the Double Boost DC-DC converter. The inductors L1 &L2 have the same values, the diodes D1-D3 are the same type and the same assumption was for the transistors (Q1 &Q2). Each inductor has its own switch and thus is similar with the paralleling of two single/classic converters. Fig1. Double Boost DC-DC converter Model ON State: When the transistors Q1 & Q2 are in ON state, energy transfer from the dc source V b into the inductors L 1 & L 2 as shown in Fig , IJARCSSE All Rights Reserved Page 1007

2 Fig.2. Double Boost Converter in ON state Fig.3. Double Boost Converter in OFF state Where i 1 is the current through inductor/transistor 1, i 2 is the current through inductor/transistor 2, io is the output current through load RL and C is the smoothing capacitor. OFF State: During the OFF state, the two inductors are connected in series, as shown in fig.3 Due to high switching Frequency the differential equations governing the circuit could be linearized. For the charging interval (Q1 = Q2 = ON), the voltage across each inductor is Vb and the currents i 1 (t) and i 2 (t) could be written as: Where I L (0) is the initial current through inductor at t = 0 and the current i L (t) is the current at t =δt, and voltage across inductors is Vo Vb. Evaluating eq. (1) at t = δt and (2) at t = T, the system becomes: The converter is design to operate in continuous mode and I L (0) = I L ( T). From the system of (2) and (3) the boost factor Mp for the proposed circuit can be deducted: As can be seen that the boost factor of the proposed converter is double as regarded to the simple boost converter. III. INTEGRAL PROPORTIONAL CONTROL SYSTEM For this study, a simple IP controller has been used, as shown in Fig.4 Fig.4 Double Boost Converter Control System In the steady state, the power balance between input and output can be written as: 2013, IJARCSSE All Rights Reserved Page 1008

3 The closed-loop transfer function of this type of regulator has two zeros: For this study an integral/proportional Fig.5 has been chosen as voltage regulator, where ki, kp are the integral and proportional coefficients respectively and L 1 is the time constant of a noise-rejection low-pass filter. The close-loop transfer function of the system is: Fig.5 IP Controller The eq. 8 shows that the IP solution cancels a slow zero from the transfer function improving the dynamics of the regulator. If the poles of the system (s0, s1 and s2) are placed on the Butterworth circle with the radius ) such as: s o = - ωo, and then the coefficients kp & Ki are: If the load resistor is considered (R L ), then the coefficients become Where T = R L C. IV. DISCRETE IP CONTROLLER IMPLEMENTED ON FPGA In this section, we explain the hardware implementation of the discrete IP controller. For this purpose, Here we used Mission 10x-Unified Learning Kit R3.0 which include Spartan-6 FPGA XC6SLX25T FPGA. Now, we must define an efficient design methodology and the abstraction level to model the system, and choose an appropriate sampling period and the suitable format for coefficients and variables. The IP controller design is based on a hierarchical and modular approach using Top-Down methodology where the modules can be defined with diverse levels of abstraction. Thus, for this design the schematic description was chosen as top level and the controller components were modelled with the VHDL hardware description language (using a behaviour level modeling). Previous analysis and simulations showed that due to the range of results generated by the operations involved in the discrete controller is necessary to use a floating point format; for this intention, the IEEE Standard for Binary Floating-Point Arithmetic, IEEE Std (IEEE, 1985) was chosen. Now, based on top down methodology, an initial modular partitioning step is applied on the FPGAbased IP controller, this process generate four components, Clock manager, ADC control, Control law and PWM generator (see Fig.6). The IP controller work with a frequency of 50 MHz (Clk_IP). The Clk_main signal is generated from Clk_main signal by the Clock manager component. The principal element of this component is the Digital Clock Manager (DCM). The DCM is embedded on the Spartan6 FPGA s families and it provides flexible complete control over 2013, IJARCSSE All Rights Reserved Page 1009

4 clock frequency, maintaining its characteristics with a high degree of precision despite normal variations in operating temperature and voltage. The DCM provides a correction clock feature, ensuring a clean Clk_IP output clock with a 50% duty cycle. Fig.6 Block Diagram of ADC control element for the IP controller. Therefore, enable signals of pipeline registers (Stage_enable0.9) are required. These signals are also generated by the Clock manager component. In addition, the clock manager component generates the frequency required by the PWM for its operation (Clk_PWM). The Clk_PWM signal is derived from the Clk_main by a Digital Frequency Synthesizer (DFS) included in the DCM. The frequency of the Clk_PWM is 25 MHz and has a 50% duty cycle correction too. The Information from the sensor is analog source, so it must be discretized for that the FPGA can process. For this purpose on board Analog-Digital Converter (ADC) is used. This ADC is an 10 bits resolution converter, it offers a 2μs conversion time and it has a 0 to 2 Volts analog input voltage range. The element responsible for this task is the ADC control component. The ADC control component is composed of two modules, the ADC interface module, which is a simple finite-state machine (FSM) that implements the communications protocol to acquire data of the ADC, and the float-point encoder module, which converts the integer value into single-precision floating-point format. A block diagram of ADC interface module is shown in Fig.7 Fig.7 Block diagram of ADC interface module Now, the information generated by the ADC control component should be processed by the corresponding control law. The discrete IP controller was synthesized on a FPGA based on equations for the continuous IP. The proposed IP controller architecture is composed of 10 pipeline stages (see Fig.8) and each of them needs 100 cycles to fulfill its function (2 μs), this indicates that the processing time of one data is 20 μs (time between 2 consecutive data delivered by the controller to the next component, the PWM). The enable signals (Stage_enable0.9) have the control each one of the pipeline registers that composed the proposed architecture. 2013, IJARCSSE All Rights Reserved Page 1010

5 Fig.8. Architecture proposed for the discrete IP controller implemented into the Spartan-6 FPGA. In the last stage the IP controller output must be adequacy for the PWM module. This adequation consists of Float-point to 8 bit unsigned binary conversion. The last component of the proposed architecture is the PWM. The PWM component consists of single up-down counter unit and one magnitude comparator unit (Fig. 9(a)). (a) Fig. 9 (a) PWM component; (b) PWM outputs (b) The implementation result of the complete architecture for discrete PID controller is reported in Table 1. Table 1. Discrete PID controller implementation results. Mod. Slices Flip- Flops 4-input's- LUT's Max.Freq (MHz) (32%) 8233 (22%) 8247 (21%) 100 V. EXPERIMENTAL RESULTS The discrete IP control and the Pulse Width Modulator (PWM) actuator for the regulation of output voltage of the double boost dc to dc converter were implemented in a Spartan-6 XC6SLX25T FPGA. The only external hardware connected to the FPGA was the drivers for MOSFET s. Fig.10 illustrates the block diagram of the FPGA-based control system based on IP controller. 2013, IJARCSSE All Rights Reserved Page 1011

6 Fig.10 Block diagram of FPGA based control system for IP controller 5.1 Requirements of the IP controller Fig.11 shows the open-loop response of the double boost converter with the following specifications: L = 100µH, C = 10μF, R = 50Ω, E = 24V, f = 50 KHz, Δv0/v0 = 0.013%, ΔiL = and a duty cycle D = The output voltage response is a steady-state error of 5.56% and has a settling time of 15ms. On the other hand, we get that the diagram bode of the transfer function given by (4) with the same parameters, has a gain margin Gm = In f (at Inf rad/sec) and a phase margin Pm = 0.377deg (at rad/sec). Given that the double boost converter system has infinite gain margin, it can withstand greater changes in system parameters before becoming unstable in closed loop. Since the system has this characteristic, we will design our controllers in closed loop with the following requirements: Overshoot less than 4.32%, Setting time less than 5 milliseconds, Steady-state error less than 1%, and Maximum sampling time 40μs. Fig.11 Output voltage transient response of the double boost converter with IP scheme 5.2 IP controller into the FPGA Fig.12 shows the performance of the IP control law, in the stabilization task for the double boost converter output voltage. As before, we used a constant reference of 220 V. The continuous line corresponds to the IP controlled response. The settling time of the response of the converter output voltage through the IP controller, is ms. The IP controller tuning was done through a third order Hurwitz polynomial. Table 2 exhibits the performance of the synthesized controller. The main specifications of the transient response, the bandwidth of the IP controller (Table 2), and these frequencies are calculated in the closed-loop through the damping ratio and settling time.the damping coefficient value is 0.707, while the value of settling time is: ms. 2013, IJARCSSE All Rights Reserved Page 1012

7 Fig.12. Output voltage transient response of the double boost converter with IP control scheme. Table 2. Specifications of the controller transient response IP. Delay Time 2.52 ms Rise Time 2013, IJARCSSE All Rights Reserved Page ms Time of Peak 6.24 ms % of Overshoot 2.20% Settling time ms Bandwidth Hz VI. CONCLUSION In this work, we have applied the Integral Proportional control scheme, synthesized via a Field Programmable Gate Array implementation, for the output voltage regulation in a double boost dc to dc converter. The performance of the IP control action was synthesized via a FPGA. The each block is designed and modeled in VHDL, correcting some errors Also we conclude that the IP controller has a good transient response. Finally, the experimental results show the effectiveness of the FPGA realization of the IP controller, in this case, programmed into the FPGA. This methodology of design can be used to design switched mode power supplies with efficiency greater than 95%. REFERENCES [1] S. K. Changchien, T. J. Liang, J. F. Chen, and L. S. Yang, Novel high step-up DC DC converter for fuel cell energy conversion system, IEEE Trans. Ind.Electron., vol. 57, no. 6, pp , June [2] N. Vazquez, L. Estrada, C. Hernandez and E. Rodriguez, The Tapped-Inductor Boost Converter, IEEE International Conference on Industrial Electronics (ISIE), [3] Y. Bercovich, B. Axelrod, S. Tapuci and A. Ioinovici, A Family of Four-Quadrant DC-DC Converters, 38th IEEE Power ElectronicsSpecialists Conference, [4] G. Thiele and E. Bayer, Voltage Doubler/Tripler Current-Mode Charge Pump Topology with Simple Gear Box, 38th IEEE Power Electronics Specialists Conference, [5] R. J. Wai and R. Y. Duan, High step-up converter with coupled-inductor, IEEE Trans. Power Electron., vol. 20, no. 5, pp , Sep [6]. V.S.C.Raviraj, P.C.Sen Comparative study of Proportional-Integral, Sliding mode and Fuzzy Logic Controllers for Power,IEEE Trans on Industry Applications, Vol.33, No.2, March/April [7] Sumanth Donthi, and Roger L. Haggard, A survey of Dynamically reconfigurable FPGA devices, Proceedings of the 35th Southeastern Symposium on System Theory, pp , [8] Freeman and R. User-programmable gate arrays,ieee Spectrum, vol. 25, Issue: 13,Dec [9] Pelleri and D. Thibault, Practical FPGA Programming in C, Prentice Hall PTR, April 22, 2005 [10]. Lattice Semiconductor, Interfacing Analog to Digital Converters to FPGAs A Lattice Semiconductor White Paper October [11]. Geoffrey Walker, Digital PWM Waveform Generation Using Adders,Australasian Universities Power Engineering Conference,2004. [12] M. Veerachary, General Rules for Signal Flow Graph Modeling and Analysis of DC-DC Converters, vol. 59,IEEE Trans,2010. [13] Q. Zhou, Y. Huang, F. Zeng and Q-S. Chen, Dynamic analysis of DC-DC Converter Based on Its Nonlinear Characteristics, The 32 nd Annual Conference of the IEEE Industrial Electronics Society, [14]