STUDY ON THE REALIZATION WITH FPGA OF A MULTICARRIER MODEM

Transcription

1 STUDY ON THE REALIZATION WITH FPGA OF A MULTICARRIER MODEM Galia Marinova 1 and Claude Fernandes 2 1 Technical University of Sofia, Telecommunications Faculty, Sofia, Bulgaria, gim@tu-sofia.bg 2 CNAM-Paris, Department of Electronics, Paris, France, cfernand@cnam.fr ABSTRACT The paper presents the results from a study on the FPGA based realization of a multicarrier modem with modulation and filter banks in the transmitter and in the receiver. The approach followed for the multicarrier modem realization is presented in details and the caracteristics in time, surface and precision of the IP (intellectual property) blocks developed for the digital signal processing functions in the modem are presented. The verifications applied for the functionality and precision estimation are also considered. 1. INTRODUCTION The paper presents the approach and the results of a study on the realization with FPGA of a multicarrier modem. The modem is designed for transmission in a frequency band of 1MHz, typical for the cables of telephone subscribers. The modem has 240 sub-channels for transmission. The frequency of each sub-channel is 4kHz. The mathematical model of the modem is described in [1,2] and the IP (intellectual property)-oriented specification of the modem is presented in [3]. The main blocks of the modem are presented on Figure 1. Serial/Parallel DATA modulation Parallel/Serial DATA demodulation IFFT (512pts) + SYNTHESIS FILTER BANK RECEIVER Equalizer TRANSMITTER Serial/Parallel Interpolator DAC CHANNEL Decimator ANALYSIS FILTER BANK + FFT(512pts) ADC Synchronization Figure 1. Main blocks in the core of a multicarrier modem A DSP-based realization of the multicarrier modem is studied in [4,7] and it needs at least 4 DSPs TMS320C6701 from Texas Instruments. The Code Composer Studio software was used to simulate the performance of the modem on DSPs. The core of the transmitter is realized on one DSP, but timing performance is close to the limit for modem speed. The core of the receiver needs at least 2 DSPs working in parallel in order to meet the timing constraints. The realization of the additional blocks in the modem has to be implemented on an additional DSP. The research described in this paper was planned to estimate the advantages of the realization on FPGA in terms of surface and timing. The FPGA permits to put in evidence some specific advantages of the modem specification, as for example the use of similar structures in the trasmitter and in the receiver. 2. APPROACH FOLLOWED FOR THE MULTICARRIER MODEM REALIZATION ON FPGA The approach followed for the multicarrier modem realization on FPGA is presented on Figure 2. Two families of programmable circuits were studied the FPGA of ALTERA with the development tool QUARTUS II and the FPGA of XILINX with the development tool ISE WEBPACK. For reasons of reliability, the circuits and development tools of XILINX were selected for the realization of the multicarrier modem. The chosen strategy was to develop in VHDL all the IP blocks of the modem, because the IP cores for digital signal processing functions proposed by the FPGA companies in [8,9] are expensive and they are not suitable for reserch and optimization. Thus, all the specific simplifications in the modem blocks, as zeros in inputs, zeros in filter coefficients, combining the FFT with a SPLIT block, can be considered. All the basic functions adders, substracters and multipliers for real and complex numbers, were rewritten in VHDL. A data base with IP blocks for the basic and digital signal processing functions was developed. The structures of the IPs in the data base are presented in [5]. The precision verification of the IP blocks developped in VHDL was based on MATLAB simulations. Loop verifications for complementary functions in the transmitter and in the receiver were performed for

2 Performance of the multicarrier modem Frequency: 4kHz Sub-channels: 240 modulation Mathematical model of the multicarrier modem C code validation of the mathematical model Development of an IP-oriented specification for the multicarrier modem Design verification of the IP in MATLAB with predefined input signal Study of : ALTERA FPGA with QUARTUS II development tool XILINX FPGA with ISE WEBPACK development tool Existing IP cores proposed by XILINX and ALTERA Estimation of the surface and timing parameters for the IP blocks on XILINX FPGA from the family VIRTEX II Development of the VHDL code for the IP blocks from the specification in the development tool ISE WEBPACK Test for functionality of the IP blocks developed Test for precision of the IP blocks developed Data base with IPs for digital signal processing functions for multicarrier modem realization Data format: 16 bits two s complement Test Signals and Test vectors Precision estimation Loop verification with subsets of IP blocks in VHDL in the transmitter and receiver of the multicarrier modem Estimations for functionality, precision, surface and timing parameters of the VHDL code for the modem Tests on XILINX development board Integration of the different IP blocks in different modem configurations Performance estimation for the FPGA-based realization and comparison with the DSP-based realization of the modem Figure 2. Approach followed for the multicarrier modem realization on FPGA functionality and precision estimation. Data are coded with 16-bits, in two s complement form. 3. IP BLOCKS DEVELOPED IN VHDL FOR THE MULTICARRIER MODEM The specification of the transmitter and the receiver defined in [3] are presented on Figures 3a and 3b. The IP blocks which were developed in VHDL are: Basic blocks: Set of 16-bit adders for real and complex operations; 16bit multiplier, based on Booth encoding and Wallace tree; Multiplier for complex numbers; Digital signal processing blocks: Butterfly processor; FFT/IFFT 16, 32 points, extendable to 128, 256 and 512 points; SPLIT blocks before the IFFT and after the FFT; for the transmitter and for the receiver;

3 I-A 0 II-A 0 I-A 1 II-A 1 modulation transmitter I-A 255 II-A Blocks [A] with 256 real words in 16 bit are processed every 250µs, so one block [A] with 256 words is processed in 125µs RAM 256x2x16bits 8 blocks A are processed in one cycle at time moments:t 0, t -1=t 0-125µs, t- 2=t µs,..,t --7=t µs, Complete processing time for one cycle for the 8 blocks is 1 ms. Pass II is processed 125µs after pass I I-A I-A 1 I-A I-A 3 real imaginary 0 I-A 255 I RAM 2x256x16bit (256 complexes) 0 II-A 0 II-A II-A 2 0 II-A 254 II-A II RAM 2x256x16bits(256 complexes) I-C 0 (t -3) I-C 0 (t -2) I-C 0 (t -1) I-C 0 (t 0) I-C 1(t -3) I-C 1(t -2) I-C 1(t -1) I-C 1(t 0) I-C 511(t -3) I-C 511(t -2) I-C 511(t -1) I-C 511(t 0) II-C 0(t -3) II-C 0(t -2) II-C 0(t -1) II-C 0(t 0) II-C 1(t -3) II-C 1(t -2) II-C 1(t -1) II-C 1(t 0) II-C 511(t -3) II-C 511(t -2) II-C 511(t -1) II-C 511(t 0) Storage of the results for the 8 initial blocks A processed during the two passes () following the modulation. The 256 complex words in every part at the outputs of the IFFT are transformed in a block with 512 real data. RAM 4x2x512x16bit Each block is processed and stored in 250µs. MUX I SPLIT I, II B 0RE B 1RE Real 16bits B 255RE B 0IM B 1IM Imaginary 16bits B 255IM Block [B] with 256 complex words RAM 256x2x16bits [B] 256x2=[B RE,B IM] 256 =[B ire, B iim, I=0,255] IFFT 256 complex input points IFFT twiddle factors ROM I, II 2048 coefficients of the synthesis filter bank ROM 2048 x16bits D 0=k 0C 0 (t 0)+ k 1C 0 (t -1)+ k 2C 0 (t -2)+ k 3C 0 (t -3) MUX D 1=k 4C 1 (t 0)+ k 5C 1 (t -1)+ k 6C 1 (t -2)+ k 7C 1 (t -3) D 511=k 2044C 511 (t 0)+ k 2045C 511 (t -1)+ k 2046C 511 (t -2)+ k 2047C 511 (t -3) Synthesis Filter Bank with 2048 coefficients F 0 F 1 F 511 Serial output previous output data block from the filter bank RAM 512x16bits RAM ( )x16bits I-D 0 I-D 1 I- D 511 II-D 256() II-D 257() II-D 511() II-D 0 II-D 1 II-D 255 II-D 256 II- D 511 Figure 3a. Transmitter of the multicarrier modem (specification oriented forward realization on FPGA) Synthesis filter bank in the transmitter and Analysis filter bank in the receiver; Interpolator and decimator from figures 4a and 4b. The characteristics of the IP blocks developed for the modem are presented in Table 1. Simulations are realized in ISE WEBPACK environment The estimations for surface and delay are made for XILINX FPGA from the family VIRTEX II. A development kit with the device XC2V1000-4FG-256C is used. The blocks are accessible for future optimizations in other modem projects.

4 F 255 (t -9) F 1(t -9) F 0 (t -9) Block 9: t µs F 255 (t -8) F 1(t -8) F 0 (t -8) Block 8: t µs F 255 (t -6) F 1(t -6) F 0 (t -6) Block 6: t µs F 255 (t -7) F 1(t -7) F 0 (t -7) Block 7: t µs F 255 (t -5) F 1(t -5) F 0 (t -5) Block 5: t µs F 255 (t -4) F 1(t -4) F 0 (t -4) Block 4: t µs F 255 (t -2) F 1(t -2) F 0 (t -2) Block 2: t µs F 255 (t -3) F 1(t -3) F 0 (t -3) Block 3: t µs F 255 (t -1) F 1(t -1) F 0 (t -1) Block 1: t -1 I-D 0 (T -3 ) =F 0 (t -8 ) I-D 0 (T -2 ) =F 0 (t -6 ) I-D 0 (T -1 ) =F 0 (t -4 ) I- D 0 (T 0 ) =F 0 (t -2 ) I-D 1 (T -3) =F 1(t -8) I-D 1 (T -2)=F 1(t -6) I- D 1 (T -1)=F 1(t -4) I- D 1 (T 0)=F 1(t -2) I-D 255(T -3) =F 255(t -8) I-D 255(T -3) =F 255(t -6) I-D 255(T -3) =F 255(t -4) I-D 255(T -3) =F 255(t -2) I-D 256(T -3) =F 0(t -7) I-D 256(T -3) =F 0(t -5) I-D 256(T -3) =F 0(t -3) I-D 256(T -3) =F 0(t -1) I-D 511(T -3)=F 255(t -7) I-D 511(T -2)=F 255(t -5) I-D 511(T -1)=F 255(t -3) I-D 511(T 0)=F 255(t -1) II-D 0 (T -3)=F 0(t -9) II-D 0 (T -2)=F 0(t -7) II-D 0 (T -2)=F 0(t -5) II-D 0 (T -1)=F 0(t -3) II-D 1 (T -3) =F 1(t -9) II-D 1 (T -2) =F 1(t -7) II-D 1 (T -1) =F 1(t -5) II-D 1 (T 0) =F 1(t -3) II-D 255 (T -3) =F 255(t -9) II-D 255 (T -2) =F 255(t -7) II-D 255(T -1) =F 255(t -5) II-D 255 (T 0) =F 255(t -3) II-D 256 (T -3) =F 0 (t -8) II-D 256 (T -2) =F 0 (t -6) II-D 256 (T -1) =F 0 (t -4) II-D 256 (T 0) =F 0 (t -2) II-D 511 (T -3) =F 255(t -8) II-D 511 (T -2) =F 255(t -6) II-D 511(T -1) =F 255(t -4) II-D 511 (T 0) =F 255(t -2) Serial to parallel transformation RAM 4x2x512x16bits Calculation starts when the block [F(t -1)] is charged, and T 0>t -1; T -1=T 0-250µs; T -2= T µs; T -3= T µs; C 0=k 2047D 0(T 0)+k 2046D 0(T -1)+k 2045D 0(T -2)+k 2044D 0(T -3) I, II C 1=k 2043D 1(T 0)+k 2042D 1(T -1)+k 2041D 1(T -2)+k 2040D 1(T -3) C 511=k 3D 511(T 0)+k 2D 511(T -1)+k 1D 511(T -2)+k 0D 0(T -3) ROM 2048 coefficients MUX Analysis Filter Bank with 2048 coefficients C 0RE=C 0 C 0IM=C 1 C 1RE=C 2 C 1IM=C 3 C 255RE=C 510 C 255IM=C 511 RAM 512x16bits FFT 256 complex points B 0RE B 1RE B 255RE B 0IM B 1IM B 255IM RAM 512x16bits SPLIT2 Postprocessing I-B 0RE I-B 0IM I-A 0= I-B 0RE II-A 0= II-B 0IM I-B 1RE I-B 1IM I-B 255RE I-B 255IM RAM 512x16bits II-B 0RE II-B 0IM II-B 1RE II-B 1IM II-B 255RE II-B 255IM demodulation receiver I-A 1= I-B 1IM II-A 1= II-B 1RE I-A 2= I-B 2RE II-A 2= II-B 2IM I-A 3= I-B 3IM II-A 3= II-B 3RE I-A 4= I-B 4RE II-A 4= II-B 4IM I-A 5= I-B 5IM II-A 5= II-B 5RE I-A 254 =I-B 254RE II-A 254=II-B 254IM I-A 255 =I-B 255IM IIA 255=II-B 255RE RAM 2x256x16bits constructed from the two blocks with 256 real data outcoming from the RAM 512x16bits Figure 3b. Receiver of the multicarrier modem (specification oriented forward FPGA realization)

5 Set of 512 real data in 16 bit formatat the output of the trasmitter core F 511 F 1 F 0 INTERPOLATOR Set of 1024 real data in 16bit format 0 F F 1 0 F 0 0 F F 510 F h 20 h 19 h 18 h 1 h 0 Rolling window ROM with 21 coefficients for the filter in the interpolator 21x16bits Set of 1024 real data in 16bit format G 1023 G 1022=F 506 G 3 G 2=F 506 G 1 G 0=F 507 G 0=F 507() G 1= h h 19F 0+ h 180+ h 17F 511() + + h 1 F 503() + h 00 G 2= F 508() G 3= h h 19F 1+ h 180+ h 17F 0 + h 16F 511() + + h 20 + h 1F 504() + h 00 G 4=F 509() G 10=F 0 G 19= h 200+h 19F 9+ h 180+ h 8F h 20 + h 1F 0 + h 00 G 20=F 5 G 21= h 200+h 19F 10+ h 180+ h 17F h 20 + h 1F 1 + h 00 G 22=F 6 G 2k =F k-5, k=5,11 G 1023= h h 19F 511+ h 180+ h 17F h 20 + h 1F h 00 Figure 4a. Specification of the interpolator from figure 1 Set of 1024 rael data in 16bit format G 1023 G 1022 G 3 G 2 G 1 G 0 G 1023 G 1022 G 1005 G 1004 h 20 h 19 h 18 h 1 h 0 Rolling window Set of 1024 real numbers in 16bit format F 1023 F 1022 F 3 F 2 F 1 F 0 Data with odd index are taken ROM des 21 coefficients of the filter in the decimator 21x16bits Set of 512 real numbers on the input of the receiver s core F 511 F 1 F 0 DECIMATOR F 0= h 20G 0 + h 19 G 1023() + h 18G 1022() + + h 1 F 1005() + h 0F 1004() F 1= h 20G 1 + h 19G 0() + h 18G 1023() + + h 1 F 1006() + h 0F 1005() F 2= h 20G 2 + h 19G 1 + h 18G 0+ h 17 G 1023() ++ h 1G 1007() + h 0G 1006() F 3= h 20G 3 + h 19G 2+h 18 G 1+ h 17G 0 + h 16G 1023() + + h 1 G 1008() + h 0G 1007() F 20= h 20G 20 + h 19G 19+h 18 G 18+ h 17G 17 + h 16G h 1 G 1 + h 0G 0 F 1023= h 20G h 19G h 18G h 17F h 2G h 1G h 0G 1003 Figure 4b. Specification of the decimator in the receiver from figure 1

6 Table 1. Characteristics for structure, surface, delay and precision of the IP blocks developed for the modem, estimated on XILINX FPGA from the family VIRTEX II with the device XC2V1000-4FG-256C IP block Characteristics for structure, surface, delay and precision Adder for real numbers 16 bits Delay: 9ns Adder for complex numbers Structure: Two 16-bit adders for real numbers; Delay: 9ns Multiplier 16 bits Structure: Booth encoding and Wallace tree Delay: 50ns Butterfly processor Structure: Realized with 4 16-bit multipliers in parallel Surface*: 20k Delay: 59 ns FFT/IFFT Structure for the 32 points block: Realized with 1 butterfly processor and counters; The radix 2 algorithm is implemented; Structure for the 128 points block: Implements 4 times the 32 points block plus additional logic Structure for the 512 points block: Implements the 128 points block For the 512 points FFT: Surface:500k Delay: 51us Precision: 0.07% average error modulation in the Structure : Realization with one block RAM 256x16bits transmitter demodulation in the receiver Surface*: 12.5k Delay: 5.88ns SPLIT Before the IFFT After the FFT Optimized block +SPLIT before the IFFT SPLIT+ after the FFT Filter bank Synthesis filter bank in the transmitter (SFB) Analysis filter bank in the receiver (AFB) The implementation of the SPLIT permits to reduce twice the size of the FFT/IFFT block; Instead of 512 points FFT/IFFT, combined with the SPLIT a 256 points FFT/IFFT is used; The SPLIT-based realization of the multicarrier modem is considered in a separate paper. Structure: 512 filters with 4 coefficients; The analysis filter bank has the same structure as the synthesis filter bank with different order of the 2048 coefficients: h i,j [SFB]=h 513-i,j [AFB], i=1,512, j=1,4 Realization with 1 multiplier-accumulator and counters for the 2048 multiplications Surface*: 500k Delay:102us Precision 0-7% Interpolator Structure: Filter with 21 coefficients, 10 of them are zeros; Realization with 1 multiplier-accumulator and counters for the 10 multiplications; A set of 512 data is transformed in a set of 1024 data; Surface*: 100k Delay: 256us Precision:0.15% maximal error Decimator Structure: Filter with 21 coefficients, 10 of them are zeros; The coefficients of the filter in the decimator are those in the interpolator devided by 2: h i [DEC]=0.5h i [INT], i=1,21 Realization with 1 multiplier-accumulator and counters for the 11 multiplications; A set of 1024 data is transformed in a set of 512 data; Surface*: 100k Delay: 281us Precision: 0.155% maximal error * The surface is calculated on base of XILINX CLBs (complex logic blocks), blocks of data RAM and coefficients ROM. These data are given in details in [5]. The multicarrier modem considered has some advantages for realization because the IP blocks in the transmitter have similar structure to the IP blocks in the receiver: modulation in the transmitter and demodulation in the receiver; IFFT in the transmitter and FFT in the receiver; Synthesis filter bank in the transmitter and analysis filter bank in the receiver, differing each other by the order of the coefficients; Interpolator in the transmitter and decimator in the receiver, differing by the coefficient values. The coefficients of the filter bank are calculated as follows: h (1023+i) =cos(π(i-1)/256)/(1-((i-1)/128) 2 ), i=1,128 and i=130,1024 h 1152 =π/4 h (1024-i)= h (1024+i), i=1,1023 h 2048 =0 This fact permits the surface optimization by using twice the same structure and it permits the loop verification for the complementary blocks in the transmitter and the receiver.

7 A set of design solutions for each IP block is estimated in order to select the optimal one for the modem realization. For example on figures 5a and 5b are considered two realizations of the filters in the iterpolator and in the decimator. The design from figure 5a uses 10 or 11 multipliers in parallel to realize the specifications from figures 4a and 4b, and the design from figure 5b uses one multiplier and a clock for serial realization. The solution from figure 5a is prohibitive in terms of surface, so the structure from figure 5b was implemented both for the filters in the interpolator and in the decimator. F 1 h 1 F 2 h 3 F 3 h 5.. F 11 h 19 Figure 5a. Realization of decimation/interpolation with 11/10 multipliers in parallel RAM with non zero input data 11 for the decimator 10 for the interpolator Clock Adder accumulator ROM with non zero coefficients 11 for the decimator 10 for the interpolator output Gout Figure 5b Realization of decimation/interpolation with 1 multiplier The blocks to be developed are: the equalizer, the synchronization and the binary to symbol transform. Mathematical models of these blocks are presented in [2]. 4. DESIGN VERIFICATIONS OF THE MULTICARRIER MODEM REALIZATION Verifications for functionality and precision estimation of the different IP blocks are described in [5]. Here is presented a verification in loop of the modulation and demodulation in the transmitter and in the receiver in order to estimate the functionality and the precision of the design integrating the main blocks in the modem. The loop verification is presented on Figure 6. The modem core realization is verified with an unitary pulsation in the input of the transmitter. The 8 initial blocks [A] from figure 3a (at times t-7, t-6, t-5, t-4, t-3, t-2, t-1, t0) contain one data 1. All other data are 0. The purpose is to verify the loop formed from the following IP blocks: modulation in the transmitter, SPLIT and IFFT, Synthesis Filter Bank, final addition in the transmitter, demodulation in the receiver, Analysis Filter Bank in the receiver, FFT and SPLIT. The objective is to compare the data from the block in the input of the transmitter at the moment t0 and the data received at the output of the receiver, given the data from the 7 previous blocks from moments t-1, t-2, t- 3, t-4, t-5, t-6, t-7. The verification is first realized through MATLAB simulation, then verification is realized through VHDL simulation in XILINX ISE WEBPACK environment. Precision and verification loop for the filter bank blocks in the transmitter and the receiver is estimated through the maximal error which is 7% compared to MATLAB results and 7% from the comparison between transmitted and received data in the experience with the unitary pulse transmission and reception. 5. CONCLUSION A study on the realization with FPGA of a multicarrier modem was performed. The main IP blocks for the modem are developed in VHDL. The results from the test integrating the principal blocks in the transmitter and the receiver of the modem are sufficient in precision, timing and surface. The realization on FPGA could be a complement or a substitution to the DSP-based realization. The main drawback of the DSP-realization mentioned in [4,7] is that the core of the multicarrier modem from figure 1 needs at least 4 DSPs. At the other hand the timings obtained in the DSP realization are very close to constraints limits for modem performance. The FPGA-based modem realization is more compact and it provides a satisfactory timing rate. For example the IP block of the FFT(IFFT) with 256 complex points realized on FPGA is 5 times faster than the similar realization on DSP [7]. Further integration of the modem design is planned, adding blocks for coding, equalization and synchrozation. Some optimizations and additional tests are foreseen by simulation and on development kit.

8 I t- t- t- t- t- t IFFT 512pts Synthesis FB in the transmitt [DI]= t0 t-1 t-2 t-3 d 1 d 1 d 1 d 1 d 2 d 2 d 2 d 2 d 512 d 512 d 512 d 512 [DI] Unitary pulse Serial Input data II Modulation in the transmitter t- t- t- t- t- t [DII]= t0 t-1 t-2 t Delay 256 positions Analysis FB receiver ~0 ~0 ~0 ~0 1 ~0 ~0 ~ Output signal in the receiver FFT 512pts Figure 6. Loop verification of the modulation and demodulation in the transmitter and the receiver of the multicarrier modem design 6. ACKNOWLEDGEMENTS The authors acknowledge professor Maurice Bellanger for his contribution in the theoretical aspects of the modem design and the test vectors definitions. Thanks also to Mr. Didier Le Ruyet for his advices. Authors acknowledge the partial financial support from the NATO scientific project PST.CLG /16/3/01 and NSF I/1203/03 project. 7. REFERENCES [1] M. Bellanger, Digital Processing of Signals: Theoty and Practice (3 rd edition), John Wiley and Sons ed., UK, February 2000 [2] M. Khalfaoui, Contribution on the Study of a Multicarrier Transmition System, Ph.d. thesis CNAM- Paris, France, January 2001 (in French) [3] G. Marinova, C.Fernandes, M.Bellanger, Specification of a Multicarrier Modem Aimed to Intellectual Property and FPGA Implementation, Proceedings of the Int. Conf. BTEBIZ 2002, Albena, Bulgaria, September 2002, pp [4] M.Baudin, Ph.Tremblais, M. Bellanger, Implantation et optimisation d un algorithme multiporteuse sur DSP, Proceedings of the Int. Conf. BTEBIZ 2002, Albena, Bulgaria, September 2002, pp [5] G.Marinova, C.Fernandes, Data Base of IP blocks Developed in VHDL for Multicarrier Modem Realization on FPGA, Proceedings MELECON 2004, Volume I, Dubrovnik, May 2004, pp [6] St. Statev, G. Marinova, P. Daponte, C. Fernandès, Comparison of the Parallel and Serial Realizations of the IP Block of the FFT, Proceedings of the Int. Conf. BTEBIZ 2002, Albena, Bulgarie,16-18 September 2002, pp [7] Ph. Tremblais, Realization of a multicarrier modem applied on S/ADSL system, CNAM-Paris, France, June 2002 (in French) [8] [9]