IMPLEMENTATION OF G.726 ITU-T VOCODER ON A SINGLE CHIP USING VHDL

Transcription

1 IMPLEMENTATION OF G.726 ITU-T VOCODER ON A SINGLE CHIP USING VHDL G.Murugesan N. Ramadass Dr.J.Raja paul Perinbum School of ECE Anna University Chennai Gm1gm@rediffmail.com ramadassn@yahoo.com jrpp@annauniv.edu ABSTRACT The objective of the paper is to design a high density DECODER for handling multi-channels(256) of G.726. ADPCM Decoder in FPGA to convert 64 kbps digital streams in to 40 kpbs, 32 kbps, 24 kbps or 16 kbps using VHDL. It gives the high speed advantage because of parallel processing of DSP algorithm. The processing speed and granular architecture of ALTERA FPGA is better utilized. The complete multichannel decoder is implemented in ALTERA(EPF10K70RC240-4) FPGA. Two multi-channel architectures for the decoder are designed using single channel parallel and serial architecture. The parallel architecture is a high density, which is capable of handling 256 channels, but area intensive. In case of serial architecture 50% area saving is achieved, at the cost of reduction in number of channels(32). DPRAMs are implemented efficiently in the embedded array blocks(eab) and the processing blocks are implemented in the logic array blocks(lab) of ALTERA FLEX10K FPGA. Thus the available FPGA logic resources are utilized to the maximum possible extend. This paper describes simplified block diagram of ADPCM encoder and implementation of decoder in a single FPGA chip. 1. INTRODUCTION Programmable logic devices such as Field Programmable Gate arrays (FPGAs) offer an alternative solution for the computationally intensive functions performed traditionally by Programmable Digital Signal Processors (P-DSP). Programmable logic devices provide increased DSP system performance at reduced system cost. FPGAs with 1-3 million transistors in a single chip are available from a no. Of FPGA vendors like Altera (EP20K200E) and Xilinx (XC2S150)[5]. This Paper discusses the details of the implementation of Multi channel ADPCM decoder recommended by G.726 ITU-T[1] standard using Altera Flex10K FPGA. The Algorithm given in the ITU-T standard is implemented directly, which gives high speed, but, occupies more resource in FPGA. To efficiently use the chip area the entire architecture can be modified into serial architecture. 2. G.726 ADPCM VOCODER The Voice coder is one, which Compress & De-compress the voice samples for transmission & reception of voice with limited bandwidth. We use waveform coding for this purpose. Waveform Coding basically does compression of sample at the transmitting end and de-compression of sample at the receiving end[3]. In Waveform coding there is no latency, very good voice reproduction and less complexity in implementation when compared to Source coding 2.1 ADPCM encoder Simplified block diagrams of the ADPCM encoder is shown in Figure 1. From linear uniform PCM, a difference is obtained, by subtracting an estimate of the input from the input. An inverse produces a quantized difference from these

2 same five, four, three or two binary digits. The estimate is added to this quantized difference to produce the reconstructed version of the input. Both the reconstructed and the difference are operated upon by an adaptive predictor, which produces the estimate of the input, thereby completing the feedback loop. PC M inp Difference Adaptive Quantiz er Signal estimate AD- PCM output Reconstructed adaptive predictor will generate the estimate, and the difference and estimate are added and limited with an output limiter to get the actual input as in the encoder input. The reconstructed is actually a 16 bit, so the output limiter will limit the value to 14-bit linear PCM value. It is shown in fig 2. Inverse Adaptive Quantized version dq (k) of the difference is produced by scaling, using y (k), specific values selected from the normalized quantizing characteristic given in Table 1 then transforming the result to the logarithmic domain. Adaptiv e Predictor Quantized difference Inverse adapti ve Fig 1.Simplified block diagram of ADPCM encoder 2.2 ADPCM decoder The decoder includes a structure identical to the feedback portion of the encoder. The inverse Fig3 Inverse adaptive Operation at 16 kbit/s Two binary digits are used to specify the quantized level representing d(k) (one for the magnitude and one for i(k) Inverse adaptive dq(k) Reconstructed calculator Sr(k) Output Limiting So(k) Se(k) Adaptive Predictor Quantizer Scale factor adaptation y(k) a 1 (k) Adaptation speed control t d (k) t r (k) Tone & Transition Detector Fig.2 ADPCM decoder Adaptive gives the difference, from the difference the the sign). The 2-bit output I(k) forms the 16 Kbit/s output ; it is

3 also fed to the inverse adaptive, the adaptation speed control and the scale factor adaptation blocks. Normalized input range log 2 d (k) - y (k) I (k) Normalized Output log 2 d q (k) - y (k) 0[2.04, + )00 (-, -2.04) Table.1 Quantizer normalized input/ output Characteristic for 16 kbit/s operation Instead of 2 bits 3,4 5 bits are used for 24, 32, 40 kbps respectively [1]. Functional blocks in inverse adaptive Reconstruct Input: I (5/4/3/2 SM) Outputs: DQLN (12 TC S,3,..-7), DQS (1 TC) Function: Reconstruction of quantized difference in the logarithmic domain.[1] SM Signed Magnitude TC- Two s Complement Add A Inputs: DQLN(12TC S,3,..-7), Y(13SM 3, -9) Output: DQL(12 TC S,3,..-7) Function: Addition of logarithmic version of quantized difference and logarithmic version of step size (Y) and limit the output value to 12 bit TC (2 s complement) number. Antilog Inputs: DQL (12 TC S,3,..-7), DQS (I TC) Output:DQ (16 SM S,14,..0)/ DQ (15 SM S,13,..0) Function: Convert quantized difference (DQL) from the logarithmic to the linear domain[1]. It converts the logarithmic value to linear value and attaches the sign bit (DQS) generated from RECONST module as 16 bits /15 bit SM (DQ) for 40KBPS/Other bit rates. Functional blocks for all blocks in the decoder block diagram is developed as per the G.726 recommendation[1]. Quantizer scale factor adaptation This block computes y (k), the scaling factor for the and the inverse. The inputs are the 5- bit, 4-bit, 3-bit, 2-bit output I (k) and the adaptation speed control parameter al (k). yu (k) = ( ) y (k) W [I (k)], (2-2 ) ---(1) where yu (k) is limited by 1.06 yu (k) (2) Similarly we can use G.726 recommendation for 24,32 and 40kbps[1]. The slow (locked) scale factor yl (k) is derived from yu (k) with a low pass-filter operation: yl (k) = ( ) yl (k - 1) yu (k) (2-3 ) --(3) For 16 Kbit/s APDCM, the discrete function W(I) is defined as follows (infinite precision values): Fig4. Quantizer scale factor adaptation

4 Similarly all blocks are coded. The fast and slow scale factors are then combined to form the resultant scale factor: y (k) = al (k) yu (k - 1) + [1 - al (k)] yl (k - 1)-(4) where 0 al (k) 1 --(4) Adaptive predictor and reconstructed calculator The primary function of the adaptive predictor is to compute the estimate se (k) from the quantized difference dq (k).two adaptive predictor structures are used, a sixth order section that models zeros and a second order section that models poles in the input. This dual structure effectively caters for the variety of input s which might be encountered. Multichannel Implementation Of G.726 ADPCM Decoder The exisisting single channel decoder can be reconstructed into multichannel by simply duplicating the storage elements N times for N channels.the storage elements in the IIR filter are simply duplicated..a DPRAM is shown in the fig.6 To provide appropriate movement of history a read- write pointer is designed which provides read and write addresses for the DPRAM. Increase in Number of channel will increase EAB utilization only. Where -----(5) (6) and the reconstructed is defined as ----(7) Both sets of predictor coefficients are updated using a simplified gradient algorithm. Tone and transition detector In order to improve performance for s originating from frequency shift keying (FSK) modems operating in the character mode, a two-step detection process is defined. First, partial band (e.g. tone) detection is invoked so that the can be driven into the fast mode of adaptation. Fig.5 Tone and transition detector Fig 6 DPRAM representation of series of Latches Design Flow 1. Design Specification 2. Design entry 3. Design Simulation 4. Design synthesis 5. Synthesis simulation 6. Implementation a. Technology mapping b. Placement & Routing c. Back annotation 7. Timing Verification 8. Downloading configuration into FPGA

5 Testing The entire Parallel and Serial decoder has been tested using the input and output test Vectors given by the G.726 ITU-T recommendation[1]. There are two kinds of test vectors given as (i) Normal sequence and (ii) Overloaded sequence. The input and output sequences has been verified. Resource Utilization FPGA EPF10K100GC503 Number of Logic Elements 4288 Number of D Flip-Flops 287 Number of EAB bits 0 Maximum clock frequency 4.9 MHz Maximum sampling frequency 4.9 MHz 3. CONCLUSION The FPGA implementation of the ADPCM decoder in parallel structure has high density and which is capable Of handling 256 channels. Serial architecture can be used to save the area about 50% at the cost of reduction in number channels. 4. REFERENCES [1].ITU-T Recommendation G.726 General Aspects Of Digital Transmission Systems; Terminal Equipments- 40, 32, 24, 16 kbit/s ADAPTIVE DIFFERENTIAL PULSE CODE MODULATION (ADPCM). [2].ITU-T Recommendation G.711 General Aspects Of Digital Transmission Systems; Terminal Equipments- Pulse code Modulation (PCM) of Voice Frequencies. [3].Jayant,N.S., and Knoll., Digital Coding Of Waveforms,Printice Hall,Inc.,Engle wood Cliffs, N.J., [4].Texas Instruments, TMS320C54x DSP,Reference Guides [5].Altera Digital Library,Version 7,2000.