INSTITUTO SUPERIOR TÉCNICO. Architectures for Embedded Computing

Transcription

1 UNIVERSIDADE TÉCNICA DE LISBOA INSTITUTO SUPERIOR TÉCNICO Departamento de Engenharia Informática Architectures for Embedded Computing MEIC-A, MEIC-T, MERC Lecture Slides Version English Lecture 23 Title: Interface with Peripheral Devices Summary: input/output(memory mapped vs. input/output, pooling, interruptions); (real-time clocks, watchdog timers); control signal generators (Pulse Width Modulators (PWM)); Signal acquisition and conversion (-to-analog Converters (DAC), Analog-to- Converters (ADC), digital input and output). 2010/2011 Nuno.Roma@ist.utl.pt

2 Architectures for Embedded Computing Interface with Peripheral Devices Prof. Nuno Roma ACE 2010/11 - DEI-IST 1 / 54 Previous Class In the previous class... Dedicated architectures: Application Specific Instruction-set Processors (ASIPs) Architectures extensions: Instruction Set Architecture (ISA) extensions Prof. Nuno Roma ACE 2010/11 - DEI-IST 2 / 54

3 Road Map Prof. Nuno Roma ACE 2010/11 - DEI-IST 3 / 54 Summary Today: input/output: Memory mapped / Input & Output Pooling Interruptions : Real-time clocks Watchdog timers control signal generators: Pulse Width Modulators (PWM) Signal acquisition and conversion: -to-analog Converters (DAC) Analog-to- Converters (ADC) input and output Prof. Nuno Roma ACE 2010/11 - DEI-IST 4 / 54

4 Prof. Nuno Roma ACE 2010/11 - DEI-IST 5 / 54 Peripherals Devices Usual CPU interface: Two sets of peripheral registers give support to: Control and interface management; Data exchange between the CPU and the peripheral. Prof. Nuno Roma ACE 2010/11 - DEI-IST 6 / 54

5 Programming Inputs & Outputs (IO) are usually supported by two sets of operations: Memory mapped operations, issued through instructions of type load/store; Operations issued through dedicated IO instructions. Examples: Intel s x86: provides in and out IO dedicated instructions; Atmel s ARM: memory mapped IO. Prof. Nuno Roma ACE 2010/11 - DEI-IST 7 / 54 Example: Atmels ARM Memory mapped IO; The address corresponding to the desired IO device is defined in the program: DEV1 EQU 0x1000 Device read and write operations: LDR r1, #DEV1 ; r1 points to the device LDR r0, [r1] ; reads DEV1 LDR r0, #8 ; r1 holds the value to be written STR r0, [r1] ; writes value to DEV1 Prof. Nuno Roma ACE 2010/11 - DEI-IST 8 / 54

6 Example: Analog Devices SHARC Memory mapped IO; The device is mapped in an address higher than 0x400000; Usage of the DM instruction: IO = 0x400000; MO = 0; R1 = DM(IO,MO); Prof. Nuno Roma ACE 2010/11 - DEI-IST 9 / 54 Dedicated IO instructions Instructions adopted in BASIC programming language: Data read - PEEK: int peek(char *location) { return *location; } Data write - POKE: void poke(char *location, char newval) { (*location) = newval; } Prof. Nuno Roma ACE 2010/11 - DEI-IST 10 / 54

7 IO Control Using Pooling Most simple mechanism to read to or to write from a given device; Uses instructions that test if the device is available; Conducts to very inefficient programs. Write example: Read & Write example: current_char = mystring; while (*current_char!= \0 ) { poke(out_char,*current_char); while (peek(out_status)!= 0); current_char++; } while (TRUE) { /* read */ while (peek(in_status) == 0); achar = (char)peek(in_data); /* write */ poke(out_data,achar); poke(out_status,1); while (peek(out_status)!= 0); } Prof. Nuno Roma ACE 2010/11 - DEI-IST 11 / 54 IO Control Using Interruptions Pooling mechanisms tend to be very inefficient: The CPU cannot do any useful work while it is executing the test cycle; It is difficult to do simultaneous read/write operations. Interrupt based mechanisms allow the interactions with external devices to modify the processor s normal execution flow: Calls to interrupt service routines. Prof. Nuno Roma ACE 2010/11 - DEI-IST 12 / 54

8 IO Control Using Interruptions Interface between the CPU and the external device: The external devices are connected to the bus of the processor; A handshaking protocol is established: The device asserts the interrupt request line; The CPU activates the interrupt acknowledge line as soon as the interruption can be handled. Prof. Nuno Roma ACE 2010/11 - DEI-IST 13 / 54 IO Control Using Interruptions Based on interrupt handling routines; Upon the triggering of the interruption, the next instruction that will be executed will be a call to a specific interrupt handling routine: The returning address and the processor state are saved (e.g.: in stack), in order to allow the recovery of the former processor state. Prof. Nuno Roma ACE 2010/11 - DEI-IST 14 / 54

9 Interrupt Handling Routine Example: Main program: main() { while (TRUE) { if (gotchar) { poke(out_data,newchar); poke(out_status,1); gotchar = FALSE; } } } Interrupt handling routine: void input_handler() { newchar = peek(in_data); gotchar = TRUE; poke(in_status,0); } void output_handler() { } Prof. Nuno Roma ACE 2010/11 - DEI-IST 15 / 54 Control of Reads Using a Characters Queue void input_handler() { char newchar; if (full_buffer()) error = 1; else { newchar = peek(in_data); add_char(achar); } poke(in_status,0); if (nchars > 1){ poke(out_data,remove_char()); poke(out_status,1); } } Prof. Nuno Roma ACE 2010/11 - DEI-IST 16 / 54

10 Storage of Processor Registers Usually, general purpose registers are not automatically saved/restored; What happens if those registers that are modified inside the interrupt service routine are not saved/restored? The main program may present an undesirable behaviour, with a rather unpredictable pattern, which will conduct to a difficult identification of the problem; When programming the interrupt handling routines, it is the programmer responsibility to save the former values of the processor registers; such register values should then be restored, when the handler finishes its operation. Prof. Nuno Roma ACE 2010/11 - DEI-IST 17 / 54 Priority and Vector of Interruptions Two mechanisms are usually applied to define each interruption: The priority determines the interruption processing order; The vector determines which code should be executed for each interruption. Prof. Nuno Roma ACE 2010/11 - DEI-IST 18 / 54

11 Interruptions Priority Maskable interruptions: All lower priority interruptions are not recognized while pending interruptions, with higher priority, haven t still been handled. Non-maskable interruptions: Present the highest priority level; as such, they must be always immediately handled. Example: power loss. Prof. Nuno Roma ACE 2010/11 - DEI-IST 19 / 54 Interrupt Vector Allow that several peripherals may be handled with different code sequences; It is the device (or the interrupt controller) duty to provide the interrupt vector corresponding to the asserted interruption. Prof. Nuno Roma ACE 2010/11 - DEI-IST 20 / 54

12 Interrupt Controller Implements the handshake protocol in lines INT and INTA; Manages the interruptions that were triggered by the several devices: Management and manipulation of the interrupt mask; Priorities resolution; Sends the interrupt vector to the CPU (data bus). Prof. Nuno Roma ACE 2010/11 - DEI-IST 21 / 54 Operations Sequence Required steps, in order to handle a given interruption: 1. CPU acknowledges the request; 2. Device sends the vector; 3. CPU calls the handling routine: (a) Inhibits the handling of other interruptions (DSI); (b) Saves the state register (stack); (c) Saves the PC (stack); (d) INTERRUPT HANDLING; (e) Recovers the PC (stack) (RETI); (f) Recovers the state register (stack); (g) Activates the interruption handling (ENI). 4. CPU recovers the former state of the main program. Prof. Nuno Roma ACE 2010/11 - DEI-IST 22 / 54

13 Congestion Problems Possible congestion sources related with interruption handling: Execution time of the interrupt handling routine; Imposed time overhead, by the handling mechanism; Store and recovery of the registers; Penalties related with the processor s own architecture (e.g.: pipeline); Penalties related with the memory hierarchy architecture (e.g.: caches). Prof. Nuno Roma ACE 2010/11 - DEI-IST 23 / 54 Exceptions and Traps Exceptions: Generated upon an internal processor error; Synchronous; Cannot be predictable; Greater priority than the interruption mechanism; Implemented with they own priority system and based on a vector of exceptions. Traps: Exception that is explicitly triggered by an instruction (INT 15). Prof. Nuno Roma ACE 2010/11 - DEI-IST 24 / 54

14 Prof. Nuno Roma ACE 2010/11 - DEI-IST 25 / 54 : Alarms; Real-time clocks; Watchdog timers. Prof. Nuno Roma ACE 2010/11 - DEI-IST 26 / 54

15 Precise count of time intervals; Counting circuit: Given a signal with frequency f, its period is T = 1/f; If the counter counts up to N, the time interval will be t = T N. 8-bit or 16-bit counters; The clock signal may be either internal or external; A programmable prescaler may also be included; When the counter reaches the end, it activates a flag and may generate an interruption. Prof. Nuno Roma ACE 2010/11 - DEI-IST 27 / 54 Example: Prof. Nuno Roma ACE 2010/11 - DEI-IST 28 / 54

16 Repetitive precise counting of time-intervals: Auto-reload mechanism: The counting value is stored in an auxiliary register; When the counter reaches the end, a pulse is generated and the initial counting value is automatically re-loaded. Much more precise than software solutions: Interruption and interrupt handling routine execute the desired action and reload the counter ( delay...). The delay, although very small, will accumulate along the time... Prof. Nuno Roma ACE 2010/11 - DEI-IST 29 / 54 Example: Down counter; N-1 pulse counter. Prof. Nuno Roma ACE 2010/11 - DEI-IST 30 / 54

17 Repetitive count of the time: Cyclic counter, whose value is compared with a given register content. Operation: The counter is always counting (0, 1,..., FFFE, FFFF, 0, 1,...); Read the counter (e.g.: 1230); To mark 720 time units, the value 1950 is written in R1; Upon the assertion of T1, if more 720 time units are needed to be counted, the value 2670 should be written in R1; Software related delays do not affect the time count (the counter is always counting!!!) The required time interval must be greater than the time that is required to write the new value in the register. Prof. Nuno Roma ACE 2010/11 - DEI-IST 31 / 54 Required precautions that should be taken when reading a 16-bits register in an 8-bits microprocessor: When the counter is read while it is counting, it may be obtained an incorrect value: Read of the higher byte 05; Read of the lower byte 01 (the counter advanced from 05 FF to 06 01) Read value = (Wrong!) Alternative: repeatedly read several times and discard incoherent values; in this example, the value would be obtained upon a new read; The HW solution makes use of two auxiliary registers: Upon the read of the higher byte, the content of the counter is transferred into auxiliary registers; When the lower byte is read, it is provided the value that was stored in the auxiliary register Read value = 05 FF (OK!) By the time the lower byte would be read, the counter value would be 06 01; The difference between these values ( FF=2) corresponds to the time that was required to execute the instructions. Prof. Nuno Roma ACE 2010/11 - DEI-IST 32 / 54

18 Real-Time Clocks Count the real time (our time: seconds, minutes, hours,..., day of the month, year); It is necessary to permanently count the time, even when the system is powered-down: Uses a battery; Must consume very little energy. Usually, a KHz crystal is adopted: By dividing this frequency by an integer power of 2, it is possible to mark 1 second; Since it is a low frequency value, the circuit provides a low-energy consumption. Prof. Nuno Roma ACE 2010/11 - DEI-IST 33 / 54 Real-Time Clocks Many microcontrollers already include an internal Real Time Clock (RTC); Example: DS1307 (Dallas Semiconductor) Counts seconds, minutes, hours, day of the month, month, day of the week and year, with leap year compensation, until 2100; 56 bytes of RAM memory, powered by a battery; 2-wire I2C interface: SDA e SCL; Programmable SQW/OUT output signal: can be used to generate a periodic interruption; Power-loss detection; Consumes less than 500 na (with battery) when the oscillator is operating. Prof. Nuno Roma ACE 2010/11 - DEI-IST 34 / 54

19 Watchdog Timer circuit used to monitor the operation state of a microprocessor; Operation principle: Watchdog counts a given time interval; Before such time interval expires, the CPU should notify that it is operating correctly (by pulsing a pin). If the pin is activated, the watchdog re-starts the time count; If the pin is NOT activated, the watchdog asserts the CPU reset pin. There exist several watchdog circuits that also monitor the power voltage (act whenever the power voltage is outside the allowed range). Prof. Nuno Roma ACE 2010/11 - DEI-IST 35 / 54 Watchdog Many microcontrollers already include an internal watchdog; Example: DS1232 (Dallas Semiconductor) Functions: Microprocessor supervision; Manual reset; Power monitoring. Prof. Nuno Roma ACE 2010/11 - DEI-IST 36 / 54

20 Watchdog External watchdogs: Normally, they are always active; The pulse operation implies two signal transitions (avoids that a fixed value may be regarded as a pulse ). Internal watchdogs: Normally, they are inactive; The activation process is usually simple (write into a register); The deactivation process is complex, in order to avoid unwanted deactivations upon a failure (typically, requires two writes in registers, by a specific order, within a defined time interval); The pulse in the watchdog also requires a specific sequence of operations (to minimize any unwanted activation). Prof. Nuno Roma ACE 2010/11 - DEI-IST 37 / 54 Watchdog Efficiency assurance of the watchdog devices: Objective: Minimize the number of times that the reset code of the watchdog is activated; The code that pulses the watchdog should assure, in the best possible way, that the remaining system software is operating correctly (it should monitor the evolution of the several threads or the execution of the vital system operations); The efficiency of the watchdog directly depends on the intelligence of its activation circuit; a systematic mechanical activation may become useless its existence. Prof. Nuno Roma ACE 2010/11 - DEI-IST 38 / 54

21 Prof. Nuno Roma ACE 2010/11 - DEI-IST 39 / 54 Pulse Width Modulators (PWM) PWM - Pulse Width Modulation Periodic digital signal with a variable relation between the time the signal is active (high) and the time the signal is inactive (low) - duty-cycle. Application examples: Motor speed control; Oven temperature control; LEDs light intensity control; to analog conversion (by using a low-pass filter, it is possible to continuously vary the output voltage). Prof. Nuno Roma ACE 2010/11 - DEI-IST 40 / 54

22 Pulse Width Modulators (PWM) Example of a PWM signal generation: Relevant parameters: The counter is incremented between 0 and a given maximum value; it is reset, afterwards; The counter is compared with the sample value, previously stored in a register; As soon as the counter is greater or equal than the sample value, the output signal is reset to zero. Signal period (depends on the counter frequency); Precision (depends on the number of bits used by the counter / comparison register). Prof. Nuno Roma ACE 2010/11 - DEI-IST 41 / 54 Prof. Nuno Roma ACE 2010/11 - DEI-IST 42 / 54

23 signal conversion: Analog to Converters (ADC); to Analog Converters (DAC); inputs and outputs. Prof. Nuno Roma ACE 2010/11 - DEI-IST 43 / 54 Processing of Analog Signals Processing steps: Signal sampling (Sample & Hold); Analog to Conversion (ADC); signal processing; to Analog Conversion (DAC); Filtering. Prof. Nuno Roma ACE 2010/11 - DEI-IST 44 / 54

24 Analog to Converter (ADC) Converts the signal from the analog to the digital domain. Relevant parameters: Resolution (number of bits: 8, 10, 12); Precision ( 1LSB); Conversion speed (100ksps, 400Ksps, 1Msps,...); Number of channels/inputs (1, 2, 4, 8). Prof. Nuno Roma ACE 2010/11 - DEI-IST 45 / 54 Analog to Converter (ADC) Transfer function: Prof. Nuno Roma ACE 2010/11 - DEI-IST 46 / 54

25 to Analog Converter (DAC) Converts the signal from the digital to the analog domain. Example: R-2R resistive chains: Prof. Nuno Roma ACE 2010/11 - DEI-IST 47 / 54 Inputs and Outputs outputs: Usually, they only allow the connection of very low-power consumption circuits; Solution: insolation and current amplifier circuits, which allow the interaction with the outside world, without a direct electric coupling (insolation of thousands of volts): Magnetic (relays) Optical (opto-couplers) Prof. Nuno Roma ACE 2010/11 - DEI-IST 48 / 54

26 Inputs and Outputs inputs with hysteresis: Schmitt-Trigger circuits; Useful when the input signals voltage presents slow variations in particularly noisy conditions. Prof. Nuno Roma ACE 2010/11 - DEI-IST 49 / 54 Inputs and Outputs Example: Read of a pressure switch/button/key: Problem: Mechanical vibration in the electric contact (bouncing) The vibration time depends on the quality of the switch, and may vary between a few milliseconds and tens of milliseconds. Prof. Nuno Roma ACE 2010/11 - DEI-IST 50 / 54

27 Inputs and Outputs Removal of contact vibration (debouncing) by HW: Using a capacitor and Schmitt-Trigger input: Using a SR latch: Prof. Nuno Roma ACE 2010/11 - DEI-IST 51 / 54 Inputs and Outputs Removal of contact vibration (debouncing) by SW: Counting the reads: The code is periodically executed, at a fast sampling frequency: counter=0; for (i=0;i<maxreads;i++) if(read == HIGH) ++counter; else --counter; if(counter >= 0) key = HIGH; Solution is immune to the noise (spurious and short pulses). Usage of a sampling period greater than the vibration time (thus avoiding multiple reads inside such period of time): Accepts what is read (assume no noise): If the sampling occurs inside the vibration time, it can either read L or H. But the value of the next read will be deterministic. Prof. Nuno Roma ACE 2010/11 - DEI-IST 52 / 54

28 Prof. Nuno Roma ACE 2010/11 - DEI-IST 53 / 54 User interfaces Communication Examples of embedded platforms: Single Board Computers Prof. Nuno Roma ACE 2010/11 - DEI-IST 54 / 54