Timer A. Last updated 8/7/18

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Willa Beryl Jennings
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1 Last updated 8/7/18

2 Advanced Timer Functions Output Compare Sets a flag and/or creates an interrupt when the counter value matches a value programmed into a separate register Input Capture Captures the counter value when a trigger event occurs Sets a flag and/or creates an interrupt Pulse Width Modulation (PWM) Creates an automated PWM signal 2 tj

3 Advanced Timer Function Output Compare Sets a flag and/or creates an interrupt when the counter value matches a value programmed into a separate register Delay Counter in Periodic Mode Count up or down - to or from the Max Value Compare Register Holds the value to compare with the counter value When matched create a flag/interrupt 3 tj

4 count Advanced Timer Function Output Compare Compare Register up/down clock Programmable Up/Down Counter Overflow Flag Action Interrupt (Max Value) Flag Flag Flag compare value time 4 tj

5 Advanced Timer Function Input Capture Captures the timer count when an input event occurs Sets a flag and/or creates an interrupt Delay Counter in Periodic Mode Count up or down - to or from the Max Value Capture Register Holds the value of the counter when an input event occurs 5 tj

6 count Advanced Timer Function Input Capture event Capture Register up/down clock Programmable Up/Down Counter Overflow Flag Action Interrupt (Max Value) Input Event Flag/Interrupt Count stored in register time 6 tj

7 Advanced Timer Function Pulse Width Modulation (PWM) Create an output waveform based on two counter values Many variations Delay Counter in Periodic Mode Count up or down - to or from the Max Value Compare Register(s) Holds the value to compare with the counter value When matched create a flag/interrupt Waveform Generator Creates output transitions based on timer events 7 tj

8 output count Advanced Timer Function PWM Compare Register up/down clock Programmable Up/Down Counter Overflow Flag Event Interrupt (Max Value) Waveform Generator Output Signal Flag Flag Flag compare value set on wrap many variations clear on flag 8 tj

9 MSP432 9 tj

10 MSP432 ARM (AMBA Compliant) timer 4 16 bit timers 3 Timer Modes Up Continuous Up/Down 4 Capture/Compare Modes Timer Capture Compare PWM 10 tj

11 MSP432 4 Timers - each with 5 capture/compare blocks Timer 1 of 5 Capture/Compare Blocks 11 tj

12 count MSP432 Timer - Up mode Max count value is 2 16 TAxCCR0 register holds the upper limit for the count 2 Flags CCIFG set when counter reaches TAxCCR0value TAIFG set when the counter wraps around to 0 TAxCCR0 value CCIFG Flag CCIFG Flag CCIFG Flag 1 clock separation between the two flags TAIFG Flag TAIFG Flag TAIFG Flag 12 tj

13 count MSP432 Timer - Continuous mode Count value is 2 16 TAIFG set when the counter wraps around to 0 Count Value 2 16 TAIFG Flag TAIFG Flag TAIFG Flag 13 tj

14 count MSP432 Timer - Up/Down mode Max count value is 2 16 Allows for 2x period TAxCCR0 register holds the upper limit for the count 2 Flags CCIFG set when counter reaches TAxCCR0value TAIFG set when the counter reaches 0 TAxCCR0 value CCIFG Flag CCIFG Flag TAIFG Flag TAIFG Flag 14 tj

15 MSP432 Capture/Compare Block Capture Mode 5 Capture blocks in each timer 2 trigger inputs CCIxA, CCIxB Can be tied to internal or external signals (pins) Can select rising edge trigger, falling edge trigger or both Captured timer value stored in TAxCCRn CCIFG flag is set Input value is visible as the CCI bit Overflow bit (COV) to indicate a second trigger has been received prior to clearing the first trigger 15 tj

16 MSP432 Capture/Compare Block Compare Mode/PWM Mode 5 Compare blocks in each timer Desired Compare values stored in TAxCCRn (n = 0:4) CCIFG flag is set Internal signal EQUn is set modifies output modes Input signal CCI is latched into SCCI Used to create periodic interrupts or PWM signals 16 tj

17 MSP432 Timer Output Block Automatically create output signals 8 modes set by OUTMODx bits Outputs based on EQU0 (count matches CCR0) and EQUn (count matches CCRn) 17 tj

18 MSP432 n Timer in UP mode 18 tj

19 MSP432 n Timer in Continuous mode 19 tj

20 MSP432 n Timer in Up/Down mode 20 tj

21 MSP432 Interrupts 2 interrupt vectors TAxCCR0 vector Used for the CCIFG flag for TAxCCR0 only TAxIV vector CCIFG flag set in capture mode on TAxCCRn CCIFG flag set in compare mode on TAxCCRn TAIFG flag 21 tj

22 MSP432 Interrupts TAxIV vector generator CCIFG and TAIFG flags are combined into a single interrupt vector The highest priority enabled interrupt generator is stored in the TAxIV register Can be evaluated or added to PC to execute the ISR Reading TAxIV clears the current interrupt flag and activates the next highest pending interrupt 22 tj

23 MSP432 Calculation examples Desire a 1KHz 50% duty cycle square wave Timer in UP mode Tclk = 12MHz 12MHz clk 83.33ns/clk 1KHz 1ms period 12,000 12MHz clks / 1KHz period for a square wave MHz clks low, MHz clks high 12,000 clks is well within our 65,536 maximum limit 23 tj

24 MSP432 Calculation examples for a square wave MHz clks low, MHz clks high Choose set/reset mode Max = 12,000 clks Target = 6000 clks n Up mode Fcounter = 12MHz TA0CCR0 = TA0CCR1 = KHz Square wave 24 tj

25 MSP432 Calculation examples Timer in UP mode Tclk = 12MHz Desire a 1KHz 25% duty cycle square wave Solution 25 tj

26 MSP432 Calculation examples Timer in UP mode Tclk = 12MHz Desire a 100Hz 75% duty cycle square wave Solution 26 tj

27 MSP432 Registers 27 tj

28 MSP432 Control Register 28 tj

29 MSP432 Control Register Fclk = CLK src / 2 ID / TAIDEX 29 tj

30 MSP432 Counter Register 30 tj

31 MSP432 Capture/Compare Control Register tj

32 MSP432 Capture/Compare Control Register 32 tj

33 MSP432 Capture/Compare Control Register 33 tj

34 MSP432 Capture/Compare Register tj

35 MSP432 Interrupt Register 35 tj

36 MSP432 Clock Divider Register Fclk = CLK src / 2 ID / TAIDEX 36 tj

Lab 5 Timer Module PWM ReadMeFirst

Lab 5 Timer Module PWM ReadMeFirst Lab Folder Content 1) ReadMeFirst 2) Interrupt Vector Table 3) Pin out Summary 4) DriverLib API 5) SineTable Overview In this lab, we are going to use the output hardware