SSDCI3128AF SSDCI3128AF. Spread Spectrum Clock Generator. Ultra Low Power Mobile EMI Reduction IC. Spectrum Device. Application DESCRIPTION FEATURE
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1 Spread Spectrum Clock Generator Ultra Low Power Mobile EMI Reduction IC DESCRIPTION The is a versatile 1x spread spectrum frequency modulator designed to reduce electromagnetic interference (EMI) clock and data source, allowing system wide reduction of EMI of down stream clock and data dependent signals. The EMI management. allows significant system cost savings 3128 by reducing the number of circuit board layers, ferrite beads, shielding and other passive components that are traditionally required to pass EMI regulations. The family of mobile active EMI management ICs are unique in their design by elimiating the use of conventional PLLs. This allows operation on aperiodic as well periodic signals. The peak energy is distributed over a wider and controlled energy band thereby significantly lowering system EMI compared to the typical narrow band signal produced by oscillators and most frequency generators. Lowering EMI by increasing a signal s bandwidth is known as Spread Spectrum or active has an input frequency range of 1 MHZ to 40 MHz over a wide voltage range of 1.65V to 3.6V and generates a 1x spread spectrum coutput. The device can be placed in power save mode by setting the PDB pin to GND where in it draws typically 0.1uA and also stes the MODOUT pin to a High-Z state. The device has to deviation control pins SS1 and SS0 to allow flexibility and optimization of both EMI compliance as well in system design. FEATURE FCC approved method of EMI attenuation. Generates a 1X low EMI spread spectrum clock of the input frequency. Input / Output frequency o VDD 1.65V -3.6V 1 MHz to 40 MHz Multiple Deviation Selections (Refer product table) Power save mode 8-pin TDFN package Operating Temperature -40 to 85 Application 3128 is targeted for consumer electronics application such as MFP, STB, DSC, MID, HDMI,LCD panel Camcorder,and other timing sensitive analog video imaging applications Applications of HDMI, RJ45 port has good compatibility 1/10
2 BLOCK DIAGRAM VDD 8 XIN / CKIN 1 Clock input SSON 2 3 Clock out 3128 Modulation clock output 5 ModCK OUT ADS1 7 Refer FRE table setting ADS0 6 Refer FRE table setting 4 GND Reference clock LPF Phase Comparator Loop Filter VOC LPF SSC Out SSC Modulator ADS Modulation enable setting SSDC13128AF block 2/10
3 PIN ASSIGNMENT TOP VIEW XIN / CKIN 1 8 VDD 2 7 ADS1 SSON 3 6 ADS0 GND 4 5 ModCK OUT TDFN-8P PIN DESCRIPTION Pin name I/O Pin no. Description XIN / CKIN Ι 1 Clock input pin (or External reference clock input). O 2 Crystal connection( external reference, this pin should be left open) SSON Ι 3 ModCK OUT ON/OFF 1=ON 0=OFF GND GND pin ModCK OUT O 5 Modulation clock output ADS Ι 6 Analog Deviation Selection(refer Functionality Table) ADS Ι 7 VDD Power supply voltage pin Analog Deviation Selection(refer Functionality Table) 3/10
4 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Rating Min Max Unit Power supply voltage* VDD V Input voltage* VI VSS 0.5 VDD 0.5 V Output voltage* VO VSS 0.5 VDD 0.5 V Storage temperature TST C Operation junction temperature TJ C Output current IO 2 4 ma Overshoot VIOVER VDD 1.0 (tover 4 ns ) V Undershoot VIUNDER VSS 1.0 (tunder 4ns) V * : The parameter is based on VSS 0.0 V. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Overshoot/Undershoot VIOVER VDD 1.0 V tunder 4 ns VDD Input pin VSS tover 4 ns VIUNDER VSS 1.0 V 4/10
5 ELECTRICAL CHARACTERISTICS DC Characteristics Parameter Symbol Pin Conditions Output voltage VOH H level output IOH 4 ma (Ta -40 C to 85 C, VDD 3.3 V 0.3 V, VSS 0.0 V) Value Min Typ Max Unit 0.66VDD VDD V VOL L level output IOL 4 ma VSS 0.33VDD V Output impedance ZO 1 MHz to 40 MHz 30 Input capacitance CIN CKIN, Ta 25 C, VDD VI 0.0 V, f 1 MHz 16 pf Load capacitance CL 1 MHz to 40 MHz 10 pf Power supply current ICC VDD No load capacitance at 27 MHz ma Power down current Ipd VDD Input clock stopping 4 A AC Characteristics (Ta -40 C to 85 C, VDD 3.3 V 0.3 V, VSS 0.0 V) Parameter Symbol Pin Conditions Value Min Typ Max Unit Input frequency fin CKIN MHz Output frequency fout MHz Output slew rate SR Load capacitance 15 pf 0.4 V to 2.4 V V/ns Output clock duty cycle tdcc 1.5 V Output Rise Time between 20% to 80% 0.9 ns Output Fall Time between 80% to 20% 0.9 ns Cycle-cycle jitter tjc No load capacitance, Ta 25 C, VDD 3.3 V 40 ps-rms Note : The modulation clock stabilization wait time is required after the power is turned on, the IC recovers from power saving, or after ENS (modulation ON/OFF) setting is changed. For the modulation clock stabilization wait time, assign the maximum value for lock-up time. 5/10
6 OUTPUT CLOCK DUTY CYCLE (tdcc tb/ta) ta tb 1.5 V INPUT FREQUENCY (fin 1/tin) tin 0.8 VDD CKIN OUTPUT SLEW RATE (SR) 2.4 V 0.4 V tr tf Note : SR ( ) /tr, SR ( ) /tf 6/10
7 Functional Table Deviation (%) Vdd(V) Freq. Range Freq(MHz) ADS1 ADS0 ADS1 ADS0 ADS1 ADS0 ADS1 ADS ±0.06 ±0.12 ±0.18 ± ~40 24 ±0.10 ±0.19 ±0.26 ± ±0.12 ±0.23 ±0.31 ± ±0.11 ±0.23 ±0.29 ±0.33 Note: Frequency deviation can vary over voltage and temperature by 5% Center spread Spectrum is spread (modulated) by centering on the input frequency. Radiation level 0.4 modulation width 0.2% +0.2% Frequency Input frequency Center spread example of 0.2 modulation rate 7/11 7/10 /
8 Diagram of CLK spread IC1 CLK IC2 CLK LCD CLK 3128AF MCU SDRAM CLK HDMI-CSI CLK 8/10/
9 Marking Information 304X:Specific Device Code Y:Year WW:Work Week A:Assembly House TDFN-2 2-8L 9/10/
10 Ordering Code Part Number Package Temperature -08-CT 8- pin 2-mm TDFN COL - TAPE & REEL, Green -40 C to +85 C Device Ordering Information S S D C I A F C T T = Tape & Reel, R = Tube or Tray O = TSOT23 U = MSOP J=TSOT26 S = SOIC E = TQFP C=TDFN (2X2) COL T = TSSOP L = LQFP A = SSOP U = MSOP V = TVSOP P = PDIP B = BGA D = QSOP Q = QFN X = SC-70 DEVICE PIN COUNT F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE, LEAD FREE, and RoHS PART NUMBER P or n/c = Commercial I=Industrial ( 0 C to +70 C) ( -40 C to +85 C) A = Clock Generator B = Non PLL based C = EMI Reduction D = DDR support products E = STD Zero Delay Buffer F = Power Management G = Power Management H = Power Management I = Hi Performance J = Reserved Spread Spectrum Device CO.,LTD REV:1.0 10/10
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19MHz to 800MHz Low Phase-Noise XO PIN CONFIGURATION
PL685-XX FEATURES < 0.5ps RMS phase jitter (12kHz to 20MHz) at 622.08MHz 30ps max peak to peak period jitter Ultra Low-Power Consumption о < 90 ma @622MHz PECL output о
FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER. Features VDD PLL1 PLL2 GND
DATASHEET ICS252 Description The ICS252 is a low cost, dual-output, field programmable clock synthesizer. The ICS252 can generate two output frequencies from 314 khz to 200 MHz using up to two independently
Spread Spectrum Clock Generator
Spread Spectrum Clock Generator Features 4 to 32 MHz Input Frequency Range 4 to 128 MHz Output Frequency Range Accepts Clock, Crystal, and Resonator Inputs 1x, 2x, and 4x frequency multiplication: CY25811:
Spread Spectrum Clock Generator
ASAHI KASEI EMD CORPORATION Features Output Frequency Range: 90MHz 128MHz 1X or Convert 27MHz to 100MHz (3.7X) Configurable Spread Spectrum Modulation: - AKEMD s Original Spread Spectrum Profile - Modulation
Description. Benefits CONTROL LOGIC. Rev 1.2, December 21, 2010 Page 1 of 12
3-Channel Clock Distribution Buffer Key Features Low current consumption: - 2.7mA-typ (VDD=1.8V, CL=0) 1.70V to 3.65V power supply operation MHz to 52MHz CLKIN range Supports LVCMOS or Sine Inputs Supports
SiT9003 Low Power Spread Spectrum Oscillator
Features Frequency range from 1 MHz to 110 MHz LVCMOS/LVTTL compatible output Standby current as low as 0.4 µa Fast resume time of 3 ms (Typ)
Single Output Clock Generator
Single Output Clock Generator IDT5V926A DATA SHEET FEATURES: 3V to 3.6V operating voltage 48MHz to 160MHz output frequency range Input from fundamental crystal oscillator or external source Internal PLL
ICS QUAD PLL CLOCK SYNTHESIZER. Description. Features. Block Diagram PRELIMINARY DATASHEET
PRELIMINARY DATASHEET ICS348-22 Description The ICS348-22 synthesizer generates up to 9 high-quality, high-frequency clock outputs including multiple reference clocks from a low frequency crystal or clock
ICS97U2A845A Advance Information
Integrated Circuit Systems, Inc. ICS97U2A845A 1.8V Low-Power Wide-Range Frequency Clock Driver Recommended Application: DDR2 Memory Modules / Zero Delay Board Fan Out Provides complete DDR DIMM logic solution
ICS660 DIGITAL VIDEO CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DATASHEET ICS660 Description The ICS660 provides clock generation and conversion for clock rates commonly needed in digital video equipment, including rates for MPEG, NTSC, PAL, and HDTV. The ICS660 uses
ICS9112A-16. Low Skew Output Buffer. General Description. Pin Configuration. Block Diagram. 8 pin SOIC, TSSOP
Low Skew Output Buffer General Description The ICS92A-6 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF
ICS542 CLOCK DIVIDER. Features. Description. Block Diagram DATASHEET. NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01
DATASHEET ICS542 Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide
MK LOW PHASE NOISE T1/E1 CLOCK GENERATOR. Features. Description. Block Diagram DATASHEET. Pullable Crystal
DATASHEET LOW PHASE NOISE T1/E1 CLOCK ENERATOR MK1581-01 Description The MK1581-01 provides synchronization and timing control for T1 and E1 based network access or multitrunk telecommunication systems.
ICS Pentium/Pro TM System Clock Chip. General Description. Pin Configuration. Block Diagram. Power Groups. Ground Groups. 28 pin SOIC and SSOP
Integrated Circuit Systems, Inc. ICS948-60 Pentium/Pro TM System Clock Chip General Description The ICS948-60 is part of a reduced pin count two-chip clock solution for designs using an Intel BX style
Frequency Timing Generator for Pentium II Systems
Integrated Circuit Systems, Inc. ICS9248-6 Frequency Timing Generator for Pentium II Systems General Description The ICS9248-6 is the Main clock solution for Notebook designs using the Intel 440BX style
SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SN54LS373, SN54LS374, SN54S373, SN54S374, Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving s Full Parallel Access for Loading Buffered Control s Clock-Enable Has
ICS511 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS511 Description The ICS511 LOCO TM is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands
Features. Applications
PCIe Octal, Ultra-Low Jitter, HCSL Frequency Synthesizer General Description The PL607081 and PL607082 are members of the PCI Express family of devices from Micrel and provide extremely low-noise spread-spectrum
Quad PLL Programmable Clock Generator with Spread Spectrum
Quad PLL Programmable Clock Generator with Spread Spectrum Features Four fully integrated phase-locked loops (PLLs) Input Frequency range: External crystal: 8 to 48 MHz External reference: 8 to 166 MHz
Phase Detector. Charge Pump. F out = F VCO / (4*P)
PL611-30 FEATURES Advanced programmable PLL design Very low Jitter and Phase Noise (< 40ps Pk -Pk typ.) Supports complementary LVCMOS outputs to drive LVPECL and LVDS i nputs. Output Frequencies: o < 400MHz