N - CHANNEL 600V Ω A TO-220/TO-220FP PowerMESH ΙΙ MOSFET 4.2 A 4.2 A. Symbol Parameter Value Unit
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1 STP4NC60 STP4NC60FP N - CHNNEL 600V Ω TO-220/TO-220FP PowerMESH ΙΙ MOSFET PRELIMINRY DT TYPE VDSS RDS(on) ID STP4NC60 STP4NC60FP 600 V 600 V <2.2 Ω <2.2 Ω TYPICL RDS(on) = 1.8 Ω EXTREMELY HIGH dv/dt CPBILITY 100% VLNCHE TESTED NEW HIGH VOLTGE BENCHMRK GTE CHRGE MINIMIZED DESCRIPTION The PowerMESH ΙΙ is the evolution of the first generation of MESH OVERLY. The layout refinements introduced greatly improve the Ron*area figure of merit while keeping the device at the leading edge for what concer switching speed, gate charge and ruggedness. TO T0-220FP PPLICTIONS HIGH CURRENT, HIGH SPEED SWITCHING SWITH MODE POWER SUPPLIES (SMPS) DC-C CONVERTERS FOR WELDING EQUIPMENT ND UNINTERRUPTIBLE POWER SUPPLIES ND MOTOR DRIVER INTERNL SCHEMTIC DIGRM BSOLUTE MXIMUM RTINGS Symbol Parameter Value Unit STP4NC60 STP4NC60FP V DS Drain-source Voltage (V GS = 0) 600 V V DGR Drain- gate Voltage (R GS =20kΩ) 600 V V GS Gate-source Voltage ± 30 V I D Drain Current (continuous) at T c =25 o C (*) I D Drain Current (continuous) at T c =100 o C (*) I DM ( ) Drain Current (pulsed) P tot Total Dissipation at T c =25 o C W Derating Factor W/ o C dv/dt(1) Peak Diode Recovery voltage slope 3 3 V/ V ISO Iulation Withstand Voltage (DC) 2000 V T stg Storage Temperature -65 to 150 T j Max. Operating Junction Temperature 150 ( ) Pulse width limited by safe operating area ( 1) ISD 4.2, di/dt 200 /µs, VDD V(BR)DSS, Tj TJMX (*) Limited only by maximum temperature allowed October 1999 o C o C 1/9
2 THERML DT TO-220 TO-220FP Rthj-case Thermal Resistance Junction-case Max Rthj-amb R thc-sink T l Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature For Soldering Purpose o C/W o C/W o C/W o C VLNCHE CHRCTERISTICS Symbol Parameter Max Value Unit I R valanche Current, Repetitive or Not-Repetitive (pulse width limited by T j max) 4.2 E S Single Pulse valanche Energy (starting T j =25 o C, I D =I R,V DD =50V) 160 mj ELECTRICL CHRCTERISTICS (Tcase =25 o C unless otherwise specified) OFF V (BR)DSS Drain-source Breakdown Voltage I D =250µ V GS = V I DSS I GSS Zero Gate Voltage Drain Current (V GS =0) Gate-body Leakage Current (VDS =0) V DS =MaxRating V DS =MaxRating T c =125 o C V GS = ± 30 V ± 100 n 1 50 µ µ ON ( ) V GS(th) Gate Threshold Voltage V DS =V GS I D = 250 µ V R DS(on) Static Drain-source On Resistance V GS =10V I D = Ω I D(on) On State Drain Current V DS >I D(on) xr DS(on )max V GS =10V 4.2 DYNMIC g fs ( ) Forward Traconductance V DS >I D(on) xr DS(on )max I D =2 3 S C iss C oss C rss Input Capacitance Output Capacitance Reverse Trafer Capacitance V DS =25V f=1mhz V GS = pf pf pf 2/9
3 ELECTRICL CHRCTERISTICS (continued) SWITCHING ON td(on) t r Q g Q gs Q gd Turn-on Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDD =300V ID=2 R G =4.7 Ω V GS =10V (see test circuit, figure 3) V DD = 480 V I D =4.2 V GS =10V nc nc nc SWITCHING OFF t r(voff) tf t c Off-voltage Rise Time Fall Time Cross-over Time V DD =480V I D = 4.2 RG =4.7 Ω VGS =10V (see test circuit, figure 5) SOURCE DRIN DIODE I SD I SDM ( ) Source-drain Current Source-drain Current (pulsed) V SD ( ) Forward On Voltage I SD =4.2 V GS =0 1.6 V t rr Reverse Recovery I SD = 4.2 di/dt = 100 /µs 550 Time V DD = 100 V T j =150 o C Q rr I RRM Reverse Recovery Charge Reverse Recovery Current (see test circuit, figure 5) 3 11 µc ( ) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 % ( ) Pulse width limited by safe operating area Safe Operating rea Safe Operating rea for TO-220FP 3/9
4 Thermal Impedance Thermal Impedance for TO-220FP Output Characteristics Trafer Characteristics Traconductance Static Drain-source On Resistance 4/9
5 Gate Charge vs Gate-source Voltage Capacitance Variatio Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/9
6 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching nd Diode Recovery Times 6/9
7 TO-220 MECHNICL DT DIM. mm inch MIN. TYP. MX. MIN. TYP. MX C D D E F F F G G H L L L L L L DI D1 F G C D E L2 G1 H2 F1 Dia. L5 L7 L9 F2 L6 L4 P011C 7/9
8 TO-220FP MECHNICL DT DIM. mm inch MIN. TYP. MX. MIN. TYP. MX B D E F F F G G H L L L L L Ø H G B D E L6 L7 L3 F1 F F2 G L2 L4 8/9
9 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no respoibility for the coequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licee is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics 1999 STMicroelectronics Printed in Italy ll Rights Reserved STMicroelectronics GROUP OF COMPNIES ustralia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.. 9/9
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