W78LE51 8-BIT MICROCONTROLLER GENERAL DESCRIPTION FEATURES

Transcription

1 W78LE5 8-BIT MICROCONTROLLER GENERL ESCRITION The W78LE5 is an 8-bit microcontroller which can accommodate a wide supply voltage range with low power consumption The instruction set for the W78LE5 is fully compatible with the standard 85 The W78LE5 contains an K bytes Flash EROM; a 8 bytes RM; four 8-bit bi-directional and bit-addressable I/O ports; an additional -bit I/O port ; two 6-bit timer/counters; a hardware watchdog timer and a serial port These peripherals are supported by seven sources two-level interrupt capability To facilitate programming and verification the Flash EROM inside the W78LE5 allows the program memory to be programmed and read electronically Once the code is confirmed the user can protect the code for security The W78LE5 microcontroller has two power reduction modes idle mode and power-down mode both of which are software selectable The idle mode turns off the processor clock but allows for continued peripheral operation The power-down mode stops the crystal oscillator for minimum power consumption The external clock can be stopped at any time and in any state without affecting the processor FETURES Fully static design 8-bit CMOS microcontroller Wide supply voltage of V to 55V 8 bytes of on-chip scratchpad RM KB electrically erasable/programmable Flash EROM 6 KB program memory address space 6 KB data memory address space Four 8-bit bi-directional ports One extra -bit bit-addressable I/O port additional INT / INT (available on -pin LCC/QF package) Two 6-bit timer/counters One full duplex serial port (URT) Watchdog Timer seven sources two-level interrupt capability EMI reduction mode Built-in power management Code protection mechanism ackages: I : W78LE5- LCC : W78LE5- QF : W78LE5F- ublication Release ate: ecember - - Revision

2 W78LE5 IN CONFIGURTIONS -in I (W78LE5) RST RX TX INT INT T T 5 WR 6 R 7 XTL XTL VSS V E LE SEN in LCC (W78LE5) / I N T V -in QF (W78LE5F) / I N T V RST RX INT TX INT INT T T E LE SEN RST RX INT TX INT INT T T E LE SEN / W R 7 / R X T L X T L V S S / W R 7 / R X T L X T L V S S

3 W78LE5 IN ESCRITION E SYMBOL ESCRITIONS EXTERNL CCESS ENBLE: This pin forces the processor to execute out of external ROM It should be kept high to access internal ROM The ROM address and data will not be presented on the bus if E pin is high and the program counter is within on-chip ROM area SEN ROGRM STORE ENBLE: SEN enables the external ROM data onto the ort address/ data bus during fetch and MOVC operations When internal ROM access is performed no SEN strobe signal outputs from this pin LE RST XTL XTL VSS V RESS LTCH ENBLE: LE is used to enable the address latch that separates the address from the data on ort RESET: high on this pin for two machine cycles while the oscillator is running resets the device CRYSTL: This is the crystal oscillator input This pin may be driven by an external clock CRYSTL: This is the crystal oscillator output It is the inversion of XTL GROUN: Ground potential OWER SULY: Supply voltage for operation ORT : ort is a bi-directional I/O port which also provides a multiplexed low order address/data bus during accesses to external memory The ort is also an open-drain port and external pull-ups need to be connected while in programming ORT : ort is a bi-directional I/O port with internal pull-ups The bits have alternate functions which are described below: T(): Timer/Counter external count input TEX(): Timer/Counter Reload/Capture control ORT : ort is a bi-directional I/O port with internal pull-ups This port also provides the upper address bits for accesses to external memory ORT : ort is a bi-directional I/O port with internal pull-ups ll bits have alternate functions which are described below: RX() : Serial ort receiver input TX() : Serial ort transmitter output INT () : External Interrupt INT() : External Interrupt T() : Timer External Input T(5) : Timer External Input WR (6) :External ata Memory Write Strobe R (7) : External ata Memory Read Strobe ORT : nother bit-addressable bidirectional I/O port and are alternative function pins It can be used as general I/O port or external interrupt input sources (INT /INT ) ublication Release ate: ecember - - Revision

4 W78LE5 BLOCK IGRM ~ 7 ort ort Latch INT INT Interrupt CC T T B ort Latch ort ~ 7 Timer Timer SW LU Stack ointer TR Temp Reg C URT Incrementor ddr Reg ~ 7 ~ ort ort ort Latch ort Latch Instruction ecoder & Sequencer Bus & Clock Controller SFR RM ddress 8 bytes RM & SFR ROM Watchdog Timer ort Latch ort ~ 7 Oscillator Reset Block ower control XTL XTL LE SEN RST V Vss FUNCTIONL ESCRITION The W78LE5 architecture consists of a core controller surrounded by various registers five general purpose I/O ports 8 bytes of RM two timer/counters and a serial port The processor supports different opcodes and references both a 6K program address space and a 6K data storage space New efined eripheral In order to be more suitable for I/O an extra -bit bit-addressable port and two external interrupt INT INT has been added to either the LCC or QF pin package nd description follows: INT / INT Two additional external interrupts INT and INT whose functions are similar to those of external interrupt and in the standard 8C5 The functions/status of these interrupts are determined/shown by the bits in the XICON (External Interrupt Control) register The XICON register is bit-addressable - -

5 W78LE5 but is not a standard register in the standard 8C5 Its address is at CH To set/clear bits in the XICON register one can use the "SETB (/CLR) bit" instruction For example "SETB CH" sets the EX bit of XICON XICON - external interrupt control (CH) X EX IE IT X EX IE IT X: External interrupt priority high if set EX: External interrupt enable if set IE: If IT = IE is set/cleared automatically by hardware when interrupt is detected/serviced IT: External interrupt is falling-edge/low-level triggered when this bit is set/cleared by software X: External interrupt priority high if set EX: External interrupt enable if set IE: If IT = IE is set/cleared automatically by hardware when interrupt is detected/serviced IT: External interrupt is falling-edge/low-level triggered when this bit is set/cleared by software Eight-source interrupt informations: INTERRUT SOURCE VECTOR RESS OLLING SEQUENCE WITHIN RIORITY LEVEL ENBLE REQUIRE SETTINGS INTERRUT TYE EGE/LEVEL External Interrupt H (highest) IE TCON Timer/Counter BH IE - External Interrupt H IE TCON Timer/Counter BH IE - Serial ort H IE - External Interrupt H 5 XICON XICON External Interrupt BH 6 (lowest) XICON6 XICON ORT nother bit-addressable port is also available and only bits (<:>) can be used This port address is located at 8H with the same function as that of port except the and are alternative function pins It can be used as general I/O pins or external interrupt input sources (INT INT ) Example: REG 8H MOV #H ; Output data "" through MOV ; Read status to ccumulator ORL #B NL #B ublication Release ate: ecember Revision

6 W78LE5 Reduce EMI Emission Because of on-chip Flash EROM when a program is running in internal ROM space the LE will be unused The transition of LE will cause noise so it can be turned off to reduce the EMI emission if it is useless Turning off the LE signal transition only requires setting the bit of the UXR SFR which is located at 8Eh When LE is turned off it will be reactivated when the program accesses external ROM/RM data or jumps to execute an external ROM code The LE signal will turn off again after it has been completely accessed or the program returns to internal ROM code space The O bit in the UXR register when set disables the LE output In order to reduce EMI emission from oscillation circuitry W78LE5 allows user to diminish the gain of on-chip oscillator amplifiers by using programmer to clear the B7 bit of security register Once B7 is set to a half of gain will be decreased Care must be taken if user attempts to diminish the gain of oscillator amplifier reducing a half of gain may effect to external crystal operating improperly at high frequency above MHz The value of R and C C may need some adjustment while running at lower gain ***UXR - uxiliary register (8EH) O O: Turn off LE output ower-off Flag ***CON - ower control (87H) OF GF GF IL OF: ower off flag Bit is set by hardware when power on reset It can be cleared by software to determine chip reset is a warm boot or cold boot GF GF: These two bits are general-purpose flag bits for the user : ower down mode bit Set it to enter power down mode IL: Idle mode bit Set it to enter idle mode The power-off flag is located at CON This bit is set when V has been applied to the part It can be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software Watchdog Timer The Watchdog timer is a free-running timer which can be programmed by the user to serve as a system monitor a time-base generator or an event timer It is basically a set of dividers that divide the system clock The divider output is selectable and determines the time-out interval When the time-out occurs a system reset can also be caused if it is enabled The main use of the Watchdog timer is as a system monitor This is important in real-time control applications In case of power glitches or electromagnetic interference the processor may begin to execute errant code If this is left unchecked the entire system may crash The watchdog time-out selection will result in different time-out values depending on the clock speed The Watchdog timer will de disabled on reset In general software should restart the Watchdog timer to put it into a known state The control bits that support the Watchdog timer are discussed below Watchdog Timer Control Register Bit: ENW CLRW WIL - - S S S Mnemonic: WTC ddress: 8FH - 6 -

7 W78LE5 ENW : Enable watch-dog if set CLRW: Clear watch-dog timer and prescaler if set This flag will be cleared automatically WIL : If this bit is set watch-dog is enabled under ILE mode If cleared watch-dog is disabled under ILE mode efault is cleared S S S: Watch-dog prescaler timer select rescaler is selected when set S as follows: S S S RESCLER SELECT The time-out period is obtained using the following equation: RESCLER ms OSC Before Watchdog time-out occurs the program must clear the -bit timer by writing to WTC6 (CLRW) fter is written to this bit the -bit timer prescaler and this bit will be reset on the next instruction cycle The Watchdog timer is cleared on reset WIL ILE ENW OSC / RESCLER EXTERNL RESET -BIT TIMER CLER INTERNL RESET Watchdog Timer Block iagram CLRW Typical Watch-og time-out period when OSC = MHz S S S WTCHOG TIME-OUT ERIO 966 ms 9 ms 786 ms 578 ms ublication Release ate: ecember Revision

8 W78LE5 Continued Clock S S S WTCHOG TIME-OUT ERIO 57mS 69 ms 5 S 5 S The W78LE5 is designed to be used with either a crystal oscillator or an external clock Internally the clock is divided by two before it is used This makes the W78LE5 relatively insensitive to duty cycle variations in the clock The W78LE5 incorporates a built-in crystal oscillator To make the oscillator work a crystal must be connected across pins XTL and XTL In addition a load capacitor must be connected from each pin to ground n external clock source should be connected to pin XTL in XTL should be left unconnected The XTL input is a CMOS-type input as required by the crystal oscillator ower Management Idle Mode The idle mode is entered by setting the IL bit in the CON register In the idle mode the internal clock to the processor is stopped The peripherals and the interrupt logic continue to be clocked The processor will exit idle mode when either an interrupt or a reset occurs ower-down Mode When the bit of the CON register is set the processor enters the power-down mode In this mode all of the clocks are stopped including the oscillator The only way to exit power-down mode is by a reset Reset The external RESET signal is sampled at S5 To take effect it must be held high for at least two machine cycles while the oscillator is running n internal trigger circuit in the reset line is used to deglitch the reset line when the W78LE5 is used with an external RC network The reset logic also has a special glitch removal circuit that ignores glitches on the reset line uring reset the ports are initialized to FFH the stack pointer to 7H CON (with the exception of bit ) to H and all of the other SFR registers except SBUF to H SBUF is not reset ON-CHI FLSH EROM CHRCTERISTICS The W78LE5 has several modes to program the on-chip Flash EROM ll these operations are configured by the pins RST LE SEN 9CTRL() CTRL() CTRL() OECTRL() CE (6) OE (7) () and V(E ) Moreover the 5 (7 7 ) and the 7 (7 ) serve as the address and data bus respectively for these operations Read Operation This operation is supported for customer to read their code and the Security bits The data will not be valid if the Lock bit is programmed to low - 8 -

9 W78LE5 Output isable Condition When the OE is set to high no data output appears on the 7 rogram Operation This operation is used to program the data to Flash EROM and the security bits rogram operation is done when the V is reach to VC (5V) level CE set to low and OE set to high rogram Verify Operation ll the programming data must be checked after program operations This operation should be performed after each byte is programmed; it will ensure a substantial program margin Erase Operation n erase operation is the only way to change data from to This operation will erase all the Flash EROM cells and the security bits from to This erase operation is done when the V is reach to VE level CE set to low and OE set to high Erase Verify Operation fter an erase operation all of the bytes in the chip must be verified to check whether they have been successfully erased to or not The erase verify operation automatically ensures a substantial erase margin This operation will be done after the erase operation if V = VE (5V) CE is high and OE is low rogram/erase Inhibit Operation This operation allows parallel erasing or programming of multiple chips with different data When 6( CE ) = VIH 7( OE ) = VIH erasing or programming of non-targeted chips is inhibited So except for the 6 and 7 pins the individual chips may have common inputs OERTIONS (9 CTRL) ( CTRL) ( CTRL) (OE CTRL) 6 ( CE ) 7 ( OE ) E (V) (5) (7) Read ddress ata Out Output isable X Hi-Z rogram VC ddress ata In rogram Verify VC ddress ata Erase VE : others: X ata In FFH NOTE Erase Verify VE ddress ublication Release ate: ecember Revision

10 W78LE5 Continued OERTIONS rogram/erase Inhibit Notes: (9 CTRL) ( CTRL) ( CTRL) (OE CTRL) 6 ( CE ) 7 ( OE ) E (V) X VC/ VE ll these operations happen in RST = VIH LE = VIL and SEN = VIH VC = 5V VE = 5V VIH = V VIL = Vss The program verify operation follows behind the program operation This erase operation will erase all the on-chip Flash EROM cells and the Security bits 5 The erase verify operation follows behind the erase operation (5) X (7) X NOTE SECURITY BITS uring the on-chip Flash EROM operation mode the Flash EROM can be programmed and verified repeatedly Until the code inside the Flash EROM is confirmed OK the code can be protected The protection of Flash EROM and those operations on it are described below The W78LE5 has a Special Setting Register the Security Register which can not be accessed in normal mode The Security register can only be accessed from the Flash EROM operation mode Those bits of the Security Registers can not be changed once they have been programmed from high to low They can only be reset through erase-all operation The Security Register is addressed in the Flash EROM operation mode by address #FFFFh B7 Reserved B B B Security Bits KB Flash EROM h B : Lock bit logic : active B : MOVC inhibit logic : the MOVC instruction in external memory cannot access the code in internal memory logic : no restriction B : Encryption logic : the encryption logic enable logic : the encryption logic disable B7 : Osillator Control logic : / gain logic : Full gain efault for all security bits Reserved bits must be kept in logic rogram Memory Reserved Security Register FFFh FFFFh Special Setting Register - -

11 W78LE5 Lock bit This bit is used to protect the customer's program code in the W78LE5 It may be set after the programmer finishes the programming and verifies sequence Once this bit is set to logic both the Flash EROM data and Special Setting Registers can not be accessed again MOVC Inhibit This bit is used to restrict the accessible region of the MOVC instruction It can prevent the MOVC instruction in external program memory from reading the internal program code When this bit is set to logic a MOVC instruction in external program memory space will be able to access code only in the external memory not in the internal memory MOVC instruction in internal program memory space will always be able to access the ROM data in both internal and external memory If this bit is logic there are no restrictions on the MOVC instruction Encryption This bit is used to enable/disable the encryption logic for code protection Once encryption feature is enabled the data presented on port will be encoded via encryption logic Only whole chip erase will reset this bit +5V +5V V V to 7 GM T to 7 GM T V IL VIL VIL VIL V IL VIH 6 7 E/Vpp LE RST SEN V C VIL V IH V IH V IL VIL VIL V IL VIH VIL 6 7 E/Vpp LE RST SEN V C VIL VIH V IH X'tal X'tal 8 to 5 X'tal X'tal 8 to 5 Vss Vss rogramming Configuration rogramming Verification BSOLUTE MXIMUM RTINGS RMETER SYMBOL MIN MX UNIT C ower Supply V VSS - +7 V Input Voltage VIN VSS - V + V Operating Temperature T 7 C Storage Temperature TST C Note: Exposure to conditions beyond those listed under bsolute Maximum Ratings may adversely affect the life and reliability of the device ublication Release ate: ecember - - Revision

12 W78LE5 C CHRCTERISTICS VSS = V T = 5 C unless otherwise specified RMETER SYM SECIFICTION UNIT TEST CONITIONS MIN MX Operating Voltage V 55 V Operating Current I - m No load V = 55V - m No load V = V Idle Current IILE - 6 m V = 55V FOSC = MHz - 5 m V = V FOSC = MHz ower own Current IWN - 5 µ V = 55V FOSC = MHz Input Current Input Current RST Input Leakage Current E Logic to Transition Current - µ V = V FOSC = MHz IIN -5 + µ V = 55V VIN = V or V IIN - + µ V = 55V < VIN < V ILK - + µ V = 55V V < VIN < V ITL [*] -5 - µ V = 55V VIN = V Input Low Voltage VIL 8 V V = 5V E 5 V V = V Input Low Voltage VIL 8 V V = 5V RST[*] V V = V Input Low Voltage VIL 8 V V = 5V XTL [*] 6 V V = V Input High Voltage VIH V + V V = 55V E V + V V = V Input High Voltage VIH 5 V + V V = 55V RST[*] 7 V + V V = V Input High Voltage VIH 5 V + V V = 55V XTL [*] 6 V + V V = V Output Low Voltage VOL - 5 V V = 5V IOL = + m - 5 V V = V IOL = + m Output Low Voltage VOL - 5 V V = 5V IOL = + m LE SEN [*] - 5 V V = V IOL = + m Sink Current ISK m V = 5V Vin = 5V 8 5 m V = V Vin = 5V - -

13 W78LE5 C Characteristics continued RMETER SYM SECIFICTION UNIT TEST CONITIONS MIN MX Sink Current ISK 8 6 m V = 5V Vin = 5V LE SEN 5 9 m V = V Vin = 5V Output High Voltage VOH - V V = 5V IOH = - µ - V V = V IOH = -8 µ Output High Voltage VOH - V V = 5V IOH = - µ LE SEN [*] - V V = V IOH = - µ Source Current ISR - -5 µ V = 5V Vin = V - -5 µ V = V Vin = V Source Current ISR -8 - m V = 5V Vin = V LE SEN -9-8 m V = V Vin = V Notes: * RST pin is a Schmitt trigger input * LE and /SEN are tested in the external access mode * XTL is a CMOS input * ins of can source a transition current when they are being externally driven from to C CHRCTERISTICS The C specifications are a function of the particular process used to manufacture the part the ratings of the I/O buffers the capacitive load and the internal routing capacitance Most of the specifications can be expressed in terms of multiple input clock periods (TC) and actual parts will usually experience less than a ± ns variation The numbers below represent the performance expected from a 6micron CMOS process when using and m output buffers Clock Input Waveform XTL TCH TCL F O T C RMETER SYMBOL MIN TY MX UNIT NOTES Operating Speed FO - MHz Clock eriod TC ns Clock High TCH - - ns Clock Low TCL - - ns Notes: The clock may be stopped indefinitely in either state The TC specification is used as a reference in other specifications There are no duty cycle requirements on the XTL input ublication Release ate: ecember - - Revision

14 W78LE5 rogram Fetch Cycle RMETER SYMBOL MIN TY MX UNIT NOTES ddress Valid to LE Low TS TC ns ddress Hold from LE Low TH TC ns LE Low to SEN Low TL TC ns SEN Low to ata Valid T - - TC ns ata Hold after SEN High TH - TC ns ata Float after SEN High TZ - TC ns LE ulse Width TLW TC - TC - ns SEN ulse Width TSW TC - TC - ns Notes: 7 7 remain stable throughout entire memory cycle Memory access time is TC ata have been latched internally prior to SEN going high " " (due to buffer driving delay and wire loading) is ns ata Read Cycle RMETER SYMBOL MIN TY MX UNIT NOTES LE Low to R Low TR TC - - TC + ns R Low to ata Valid T - - TC ns ata Hold from R High TH - TC ns ata Float from R High TZ - TC ns R ulse Width TR 6 TC - 6 TC - ns Notes: ata memory access time is 8 TC " " (due to buffer driving delay and wire loading) is ns ata Write Cycle RMETER SYMBOL MIN TY MX UNIT LE Low to WR Low TW TC - - TC + ns ata Valid to WR Low T TC ns ata Hold from WR High TW TC ns WR ulse Width TWR 6 TC - 6 TC - ns Note: " " (due to buffer driving delay and wire loading) is ns - -

15 W78LE5 ort ccess Cycle RMETER SYMBOL MIN TY MX UNIT ort Input Setup to LE Low TS TC - - ns ort Input Hold from LE Low TH - - ns ort Output to LE T TC - - ns Note: orts are read during S5 and output data becomes available at the end of S6 The timing data are referenced to LE since it provides a convenient reference rogram Operation RMETER SYMBOL MIN TY MX UNIT V Setup Time TVS - - µs ata Setup Time TS - - µs ata Hold Time TH - - µs ddress Setup Time TS - - µs ddress Hold Time TH - - µs CE rogram ulse Width for rogram Operation TW 9 µs OECTRL Setup Time TOCS - - µs OECTRL Hold Time TOCH - - µs OE Setup Time TOES - - µs OE High to Output Float TF - ns ata Valid from OE TOEV ns Note: Flash data can be accessed only in flash mode The RST pin must pull in VIH status the LE pin must pull in VIL status and the SEN pin must pull in VIH status TIMING WVEFORMS rogram Fetch Cycle S S S S S5 S6 S S S S S5 S6 XTL T LW LE T L SEN T S T SW ORT T H T TH T Z ORT Code -7 ata -7 Code -7 ata -7 ublication Release ate: ecember Revision

16 W78LE5 Timing Waveforms continued ata Read Cycle XTL S S5 S6 S S S S S5 S6 S S S LE SEN ORT T ORT R T R T T H T Z T R ata Write Cycle S S5 S6 S S S S S5 S6 S S S XTL LE SEN ORT 8-5 ORT -7 T OUT WR T T W T W T WR ort ccess Cycle S5 S6 S XTL LE TS TH T ORT T OUT INUT SMLE - 6 -

17 W78LE5 Timing Waveforms continued rogram Operation rogram rogram Verify Read Verify (5 ) V IH V IL ddress Stable ddress Valid 6 (CE) V IH V IL T S T W (OECTRL) 7 (OE) (7 ) Vpp V IH T H TOCS V IL TOCH V IH T OES V IL T T F H V IH V ata In OUT ata Out IL T S Vcp T OEV V IH T VS ublication Release ate: ecember Revision

18 W78LE5 TYICL LICTION CIRCUITS Expanded External rogram Memory and Crystal V V u 8 K C CRYSTL C R E XTL XTL RST INT INT T T R 7 WR 6 SEN 9 LE TX RX Q Q Q Q 9 7 Q Q Q Q GN 8 OC 9 9 G GN CE OE 75 O O O O 5 O 6 O5 7 O6 8 O W78LE5 Figure CRYSTL C C R 6 MHz - MHz bove table shows the reference values for crystal applications (full gain) Note: C C R components refer to Figure - 8 -

19 W78LE5 Typical pplication Circuits continued Expanded External ata Memory and Oscillator V 8 K V u OSCILLTOR E XTL XTL RST INT INT T T R 7 WR 6 9 SEN LE TX RX Q Q 5 7 Q 6 8 Q 9 Q 5 5 Q Q Q7 9 GN OC G GN CE OE WR W78LE5 Figure B ublication Release ate: ecember Revision

20 W78LE5 CKGE IMENSIONS -pin I E L S B e B Base lane Seating lane a E e c Symbol B c E e L B E a e S imension in inch imension in mm Min Nom Max Min Nom Max Notes: imension Max & S include mold flash or tie bar burrs imension E does not include interlead flash imension & E include mold mismatch and are determined at the mold parting line imension B does not include dambar protrusion/intrusion 5 Controlling dimension: Inches 6 General appearance spec should be based on final visual inspection spec pin LCC H L θ e Seating lane G 8 b b 9 E H E 9 y c G E Symbol imension in inch imension in mm Min Nom Max Min Nom Max b b c E e 5 BSC 7 BSC G G E H HE L y Notes: imension & E do not include interlead flash imension b does not include dambar protrusion/intrusion Controlling dimension: Inches General appearance spec should be based on final visual inspection spec - -

21 W78LE5 ackage imensions continued -pin QF H E HE Symbol b c E e imension in inch imension in mm Min Nom Max Min Nom Max Seating lane e b See etail F y L c L θ etail F H H E L L y θ Notes: imension & E do not include interlead flash imension b does not include dambar protrusion/intrusion Controlling dimension: Millimeter General appearance spec should be based on final visual inspection spec Headquarters Winbond Electronics (HK) Ltd No Creation Rd III Unit 9-5 F Millennium City Science-Based Industrial ark No 78 Kwun Tong Rd; Hsinchu Taiwan Kowloon Hong Kong TEL: TEL: FX: FX: Voice & Fax-on-demand: Taipei Office F No 5 Sec Min -Sheng East Rd Taipei Taiwan TEL: FX: Winbond Electronics North merica Corp Winbond Memory Lab Winbond Microelectronics Corp Winbond Systems Lab 77 N First Street San Jose C 95 US TEL: FX: Note: ll data and specifications are subject to change withou t notice ublication Release ate: ecember - - Revision