W27C512 64K 8 ELECTRICALLY ERASABLE EPROM. Table of Contents-
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1 64K 8 ELECTRICLLY ERSBLE EPROM Table of Contents-. GENERL DESCRIPTION FETURES PIN CONFIGURTIONS BLOCK DIGRM PIN DESCRIPTION FUNCTIONL DESCRIPTION TBLE OF OPERTING MODES DC CHRCTERISTICS CPCITNCE C CHRCTERISTICS RED OPERTION DC CHRCTERISTICS RED OPERTION C CHRCTERISTICS DC PROGRMMING CHRCTERISTICS C PROGRMMING/ERSE CHRCTERISTICS TIMING WVEFORMS SMRT PROGRMMING LGORITHM SMRT PROGRMMING LGORITHM SMRT ERSE LGORITHM ORDERING INFORMTION PCKGE DIMENSIONS VERSION HISTORY Publication Release Date: January 9, Revision 6
2 . GENERL DESCRIPTION The W27C52 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as bits that operates on a single 5 volt power supply. The W27C52 provides an electrical chip erase function. 2. FETURES High speed access time: 45/70/90/20 ns (max.) Read operating current: 30 m (max.) Erase/Programming operating current: 30 m (max.) Standby current: m (max.) Single 5V power supply +4V erase/+2v programming voltage Fully static operation ll inputs and outputs directly TTL/CMOS compatible Three-state outputs vailable packages: 28-pin 600 mil DIP, 330 mil 32-pin PLCC - 2 -
3 3. PIN CONFIGURTIONS Q0 Q Q2 GND pin DIP Q5 3 6 Q4 4 5 Q V CC OE/Vpp 0 CE Q7 Q N C V C C NC Q pin PLCC NC OE/Vpp 0 CE Q7 Q6 Q Q G N Q Q Q 2 N C D Publication Release Date: January 9, Revision 6
4 4. BLOCK DIGRM OE/V CE PP CONTROL OUTPUT BUFFER Q0.. Q7 0.. DECODER CORE RRY 5 V CC GND 5. PIN DESCRIPTION SYMBOL 0 5 Q0 Q7 CE OE/VPP VCC GND NC DESCRIPTION ddress Inputs Data Inputs/Outputs Chip Enable Output Enable, Program/Erase Supply Voltage Power Supply Ground No Connection - 4 -
5 6. FUNCTIONL DESCRIPTION Read Mode Like conventional UVEPROMs, the W27C52 has two control functions, both of which produce data at the outputs. CE is for power control and chip select. OE/VPP controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TCC) is equal to the delay from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE/VPP, if TCC and TCE timings are met. Erase Mode The erase operation is the only way to change data from "0" to "." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27C52 uses electrical erasure. Generally, the chip can be erased within 00 ms by using an EPROM writer with a special erase algorithm. Erase mode is entered when OE/VPP is raised to VPE (4V), VCC = VCE (5V), 9 = VPE (4V), 0 low, and all other address pins low and data input pins high. Pulsing CE low starts the erase operation. Erase Verify Mode fter an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "" or not. The erase verify mode ensures a substantial erase margin if VCC = VCE (3.75V), CE low, and OE/VPP low. Program Mode Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "" to "0." The program mode is entered when OE/VPP is raised to VPP (2V), VCC = VCP (5V), the address pins equal the desired addresses, and the input pins equal the desired inputs. Pulsing CE low starts the programming operation. Program Verify Mode ll of the bytes in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each byte is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial program margin. This mode will be entered after the program operation if OE/VPP low and CE low. Erase/Program Inhibit Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE high, erasing or programming of non-target chips is inhibited, so that except for the CE and OE/VPP pins, the W27C52 may have common inputs. Publication Release Date: January 9, Revision 6
6 Standby Mode The standby mode significantly reduces VCC current. This mode is entered when CE high. In standby mode, all outputs are in a high impedance state, independent of OE/VPP. Two-line Output Control Since EPROMs are often used in large memory arrays, the W27C52 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur. System Considerations n EPROM's power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels (ISB), active current levels (ICC), and transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0. μ F ceramic capacitor connected between its VCC and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. dditionally, for every eight devices, a 4.7 μf electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances
7 7. TBLE OF OPERTING MODES (VPP = 2V, VPE = 4V, VHH = 2V, VCP = 5V, VCE = 5V, X = or VIL) MODE PINS CE OE/VPP 0 9 VCC OUTPUTS Read VIL VIL X X VCC DOUT Output Disable VIL X X VCC High Z Standby (TTL) X X X VCC High Z Standby (CMOS) VCC ±0.3V X X X VCC High Z Program VIL VPP X X VCP DIN Program Verify VIL VIL X X VCC DOUT Program Inhibit VPP X X VCP High Z Erase VIL VPE VIL VPE VCE DIH Erase Verify VIL VIL X X 3.75 DOUT Erase Inhibit VPE X X VCE High Z Product Identifier-manufacturer VIL VIL VIL VHH VCC D (Hex) Product Identifier-device VIL VIL VHH VCC 08 (Hex) Publication Release Date: January 9, Revision 6
8 8. DC CHRCTERISTICS bsolute Maximum Ratings PRMETER RTING UNIT Operation Temperature 0 to +70 C Storage Temperature -65 to +25 C Voltage on all Pins with Respect to Ground Except OE/VPP, 9 and VCC Pins -0.5 to VCC +0.5 V Voltage on OE/VPP Pin with Respect to Ground -0.5 to +4.5 V Voltage on 9 Pin with Respect to Ground -0.5 to +4.5 V Voltage VCC Pin with Respect to Ground -0.5 to +7 V Note: Exposure to conditions beyond those listed under bsolute Maximum Ratings may adversely affect the life and reliability of the device. DC Erase Characteristics (T = 25 C ±5 C, VCC = 5.0V ±5%) PRMETER SYM. CONDITIONS LIMITS MIN. TYP. MX. Input Load Current ILI VIN = VIL or -0-0 μ VCC Erase Current ICP CE = VIL, OE/VPP = VPE VPP Erase Current IPP CE = VIL, OE/VPP = VPE UNIT m m Input Low Voltage VIL V Input High Voltage V Output Low Voltage (Verify) VOL IOL = 2. m V Output High Voltage (Verify) VOH IOH = -0.4 m Erase Voltage VID V VPP Erase Voltage VPE V VCC Supply Voltage (Erase) VCE V VCC Supply Voltage (Erase Verify) VCE V Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP
9 9. CPCITNCE (VCC = 5V, T = 25 C, f = MHz) PRMETER SYMBOL CONDITIONS MX. UNIT Input Capacitance CIN VIN = 0V 6 pf Output Capacitance COUT VOUT = 0V 2 pf 0. C CHRCTERISTICS C Test Conditions PRMETER CONDITIONS 45/70 NS 90/20 NS Input Pulse Levels 0 to 3.0V 0.45V to 2.4V Input Rise and Fall Times 5 ns 0 ns Input and Output Timing Reference Level.5V/.5V 0.8V/2.0V Output Load C Test Load and Waveforms CL = 30 pf, IOH/IOL = -0.4 m/2. m CL = 00 pf, IOH/IOL = -0.4 m/2. m +.3V (IN94) 3.3K ohm D OUT 00 pf for 90/20 ns (Including Jig and Scope) 30 pf for 45/70 ns (Including Jig and Scope) Input Output For 90/20 ns 2.4V 0.45V Test Points 2.0V 0.8V 2.0V 0.8V Test Points Input Output For 45/70 ns 3.0V 0V Test Point.5V.5V Test Point Publication Release Date: January 9, Revision 6
10 . RED OPERTION DC CHRCTERISTICS (VCC = 5.0V ±5%, T = 0 to 70 C) PRMETER SYM. CONDITIONS LIMITS MIN. TYP. MX. Input Load Current ILI VIN = 0V to VCC -5-5 μ Output Leakage Current ILO VOUT = 0V to VCC -0-0 μ Standby VCC Current ISB CE = m (TTL input) Standby VCC Current ISB CE = VCC ±0.3V (CMOS input) μ VCC Operating Current ICC CE = VIL m IOUT = 0 m, f = 5 MHz Input Low Voltage VIL V Input High Voltage VCC +0.5 V Output Low Voltage VOL IOL = 2. m V Output High Voltage VOH IOH = -0.4 m V UNIT 2. RED OPERTION C CHRCTERISTICS (VCC = 5.0V ±5%, T = 0 to 70 C) PRMETER SYM. W27C52-45 W27C52-70 W27C52-90 W27C52-2 UNIT MIN. MX. MIN. MX. MIN. MX. MIN. MX. Read Cycle Time TRC ns Chip Enable ccess Time TCE ns ddress ccess Time TCC ns Output Enable ccess Time TOE ns OE /VPP High to High-Z Output TDF ns Output Hold from ddress Change TOH ns Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP
11 3. DC PROGRMMING CHRCTERISTICS (VCC = 5.0V ±5%, T = 25 C ±5 C) PRMETER SYM. CONDITIONS LIMITS UNIT MIN. TYP. MX. Input Load Current ILI VIN = VIL or -0-0 μ VCC Program Current VPP Program Current ICP IPP CE = VIL, OE / VPP = VPP m CE = VIL, OE / VPP = VPP m Input Low Voltage VIL V Input High Voltage V Output Low Voltage (Verify) VOL IOL = 2. m V Output High Voltage (Verify) VOH IOH = -0.4 m V 9 Silicon I.D. Voltage VID V VPP Program Voltage VPP V VCC Supply Voltage (Program) VCP V Publication Release Date: January 9, Revision 6
12 4. C PROGRMMING/ERSE CHRCTERISTICS (VCC = 5.0V ±5%, T = 25 C ±5 C) PRMETER SYM. LIMITS MIN. TYP. MX. OE /VPP Pulse Rise Time TPRT ns Data Setup Time TDS μs CE Program Pulse Width TPWP μs CE Erase Pulse Width TPWE ms Data Hold Time TDH μs OE /VPP Setup Time TOES μs OE /VPP Hold Time TOEH μs Data Valid from CE TDV 25 - μs Data Valid from ddress Change TDV μs CE High to Output High Z TDFP 0-30 ns ddress Setup Time TS μs ddress Hold Time TH μs ddress Hold Time after CE High (Erase) THC μs OE /VPP Valid after CE High TVS μs OE /VPP Recovery Time TVR μs ddress ccess Time During Erase Verify (VCC = 3.75V) TCV ns Output Enable ccess Time during Erase Verify TOEV ns (VCC = 3.75V) Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. UNIT - 2 -
13 5. TIMING WVEFORMS C Read Waveform ddress VIL ddress Valid CE OE/Vpp VIL TCE TDF Outputs VIL High Z TCC TOE Valid Output TOH High Z Erase Waveform Read Company SID 9 = 2.0V Read Device SID Chip Erase 9 = 4.0V Erase Verify Blank Check Read Verify ddress VIL Others = IL V 0 = VI 0 = L Others = IL V TCC TCC Others = VIL T S THC ddress Valid ddress Valid ddress Valid ddress Valid T CV =250 ns TCV =250 ns TCC Data D 08 Data ll One D OUT D OUT D OUT Vcc 5V T DS T DH T VCS 3.75V 4.0V T OES OE/Vpp VIL TOE TOE TOEH TOEV = 50 ns TOE CE V IL TCE TVS TPRT lways = IL V TPWE TVR Publication Release Date: January 9, Revision 6
14 Timing Waveforms, continued Programming Waveform Program Program Verify Read Verify ddress ddress Stable ddress Stable ddress Stable ddress Valid ddress Valid V IL T S T H TS TH T OH T DFP Data V IL Data In Stable Data In Stable Data Out Data Out 2.0V T DS T DH TDS T DH TDV TDV2 TCC T OH OE/Vpp V IH TOES T OEH VIL VIL T PRT T PWP T VR TOE CE VIL TCE VIL CE should not be toggled during program verify period - 4 -
15 6. SMRT PROGRMMING LGORITHM Start ddress = First Location Vcc = 5.0V OE/Vpp = 2V Program One 00 μs Pulse Increment ddress No Last ddress? Yes ddress = First Location Increment ddress X = 0 No Last ddress? Pass Verify Byte Fail Increment X Yes Program One 00 μs Pulse No X = 25? Vcc = 5.0V OE/Vpp = VIL Yes Compare ll Bytes to Original Data Fail Device Failed Device Passed Pass Publication Release Date: January 9, Revision 6
16 7. SMRT PROGRMMING LGORITHM 2 Start ddress = First Location Vcc = 5.0V X = 0 Program One 00 μs Pulse OE/V PP = 2V Increment X X = 25? Yes No Fail Verify One Byte OE/V = VIL PP Verify One Byte OE/V = VIL PP Fail Pass Pass Increment ddress No Last ddress? Yes Compare ll Bytes to Original Data Fail Pass Device Passed Device Failed - 6 -
17 8. SMRT ERSE LGORITHM Start X = 0 Vcc = 5V OE/Vpp = 4V 9 = 4V; 0 = VIL Chip Erase 00 ms Pulse ddress = First Location Increment X Vcc = 3.75V OE/Vpp = VIL Erase Verify Fail No X = 20? Increment ddress No Pass Last ddress? Yes Yes Vcc = 5V OE/Vpp = VIL Compare ll Bytes to FFs (HEX) Fail Pass Pass Device Fail Device Publication Release Date: January 9, Revision 6
18 9. ORDERING INFORMTION PRT NO. CCESS TIME (ns) OPERTING CURRENT MX. (m) STNDBY CURRENT MX. (μ) PCKGE W27C mil DIP W27C mil DIP W27C mil DIP W27C mil DIP W27C52P pin PLCC W27C52P pin PLCC W27C52P pin PLCC W27C52P pin PLCC W27C52-45Z mil DIP Lead Free W27C52P-45Z pin PLCC Lead Free Notes:. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure
19 20. PCKGE DIMENSIONS 28-pin P-DIP E 2 L 28 S B B D e 5 4 Base Plane Seating Plane a E e c Symbol B 2 B c D E E e L a e S Dimension in Inches Dimension in mm Min. Nom. Max. Min. Nom. Max Notes:. Dimensions D Max. & S include mold flash or tie bar burrs. 2. Dimension E does not include interlead flash. 3. Dimensions D & E include mold mismatch and are determined at the mold parting line. 4. Dimension B does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec. 32-pin PLCC H E E D HD GD Symbol 2 b b c D E e Dimension in Inches Dimension in mm Min. Nom. Max. Min. Nom. Max G D G E H D c H E L y θ L θ Seating Plane e G E b b 2 y Notes:. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection spec. Publication Release Date: January 9, Revision 6
20 2. VERSION HISTORY VERSION DTE PGE DESCRIPTION Mar. 998 Initial Issued 2 Sep Correct Imput High Voltage () from 2.0 (min) to 2.2 (max) 4, 6 Correct VCC from 5.0 ±0% to 5.0 ±5% 3 ug. 999, 5, 6, 3 dd 45 ns bining 2, 3 Modify function description (VIL and ): VIL Low; High 4 Nov Typo correction 5 pril 4, dding important notice 6 Jan. 9, Ordering Information:dd W27C52-45Z and W27C52P-45Z Lead free part Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales
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32K x 8 LOW VOLTAGE CMOS STATIC RAM MAY 2012 FEATURES High-speed access time: 20, 45 ns Automatic power-down when chip is deselected CMOS low power operation 17 µw (typical) CMOS standby 50 mw (typical)
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
IS62C64 8K x 8 LOW POR CMOS STATIC RAM FEATURES CMOS low power operation 400 mw (max.) operating 25 mw (max.) standby Automatic power-down when chip is deselected TTL compatible interface levels Single
DECODER I/O DATA CONTROL CIRCUIT
1M x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2006 FEATURES High-speed access time: 55ns, 70ns CMOS low power operation: 36 mw (typical) operating 12 µw (typical) CMOS standby TTL compatible
IS62WV20488FALL/BLL IS65WV20488FALL/BLL. 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM NOVEMBER 2018
/BLL IS65WV20488FALL/BLL 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current:
IS62C10248AL IS65C10248AL
IS62C10248AL IS65C10248AL 1M x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES High-speed access time: 45ns, 55ns CMOS low power operation 36 mw (typical) operating 12 µw (typical) CMOS standby
IS62WV102416FALL/BLL IS65WV102416FALL/BLL. 1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM MARCH 2018
1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current: 5.5uA (typ.)
NM27P Bit (256k x 8) POP Processor Oriented CMOS EPROM
NM27P020 2 097 152-Bit (256k x 8) POPTM Processor Oriented CMOS EPROM General Description The NM27P020 is a 2 Mbit POP EPROM configured as 256k x 8 It s designed to simplify microprocessor interfacing
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
64K x 16 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V CMOS low power operation: 50 mw (typical) operating 25 µw (typical) standby TTL compatible
8-Megabit (1M x 8) OTP EPROM AT27C080. Features. Description. Pin Configurations
Features Fast Read Access Time 90 ns Low Power CMOS Operation 100 µa Max Standby 40 ma Max Active at 5 MHz JEDEC Standard Packages 32-lead PLCC 32-lead 600-mil PDIP 32-lead TSOP 5V ± 10% Supply High-Reliability
Battery-Voltage. 1-Megabit (128K x 8) Unregulated OTP EPROM AT27BV010. Features. Description. Pin Configurations
Features Fast Read Access Time - 90 ns Dual Voltage Range Operation Unregulated Battery Power Supply Range, 2.7V to 3.6V or Standard 5V ± 10% Supply Range Compatible with JEDEC Standard AT27C010 Low Power
IS64WV3216BLL IS61WV3216BLL
32K x 16 HIGH-SPEED CMOS STATIC RAM NOVEMBER 2005 FEATURES High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V CMOS low power operation: 50 mw (typical) operating 25 µw (typical) standby TTL compatible
IS63LV1024 IS63LV1024L 128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT
128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT FEATURES High-speed access times: 8, 10, 12 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise
Battery-Voltage. 1-Megabit (64K x 16) Unregulated. High-Speed OTP EPROM AT27BV1024. Features. Description. Pin Configurations
Features Fast Read Access Time - 90 ns Dual Voltage Range Operation Unregulated Battery Power Supply Range, 2.7V to 3.6V or Standard 5V ± 10% Supply Range Pin Compatible with JEDEC Standard AT27C1024 Low
64K x 16 HIGH-SPEED CMOS STATIC RAM JUNE 2005
64K x 16 HIGH-SPEED CMOS STATIC RAM JUNE 2005 FEATURES IS61C6416AL and High-speed access time: 12 ns, 15ns Low Active Power: 175 mw (typical) Low Standby Power: 1 mw (typical) CMOS standby and High-speed
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY JULY 2006 FEATURES High-speed access time: 10, 12 ns CMOS low power operation Low stand-by power: Less than 5 ma (typ.) CMOS stand-by
4-Megabit (256K x 16) OTP EPROM AT27C4096
Features Fast Read Access Time 55 ns Low Power CMOS Operation 100 µa Maximum Standby 40 ma Maximum Active at 5 MHz JEDEC Standard Packages 40-lead PDIP 44-lead PLCC 40-lead VSOP Direct Upgrade from 512-Kbit,
IS62WV2568ALL IS62WV2568BLL
IS62WV2568ALL IS62WV2568BLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM DECEMBER 2008 FEATURES High-speed access time: 55ns, 70ns CMOS low power operation 36 mw (typical) operating 9 µw (typical)
27C Bit ( x 8) UV Erasable CMOS PROM Military Qualified
27C256 262 144-Bit (32 768 x 8) UV Erasable CMOS PROM Military Qualified General Description The 27C256 is a high-speed 256K UV erasable and electrically reprogrammable CMOS EPROM ideally suited for applications
4-Megabit (512K x 8) OTP EPROM AT27C040. Features. Description. Pin Configurations
Features Fast Read Access Time - 70 ns Low Power CMOS Operation 100 µa max. Standby 30 ma max. Active at 5 MHz JEDEC Standard Packages 32-Lead 600-mil PDIP 32-Lead 450-mil SOIC (SOP) 32-Lead PLCC 32-Lead
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
8K x 8 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 0 ns CMOS low power operation mw (typical) CMOS standby 25 mw (typical) operating TTL compatible interface levels Single
256K (32K x 8) Unregulated Battery. Programmable, Read-only Memory
Features Fast read access time 70ns Dual voltage range operation Unregulated battery power supply range, 2.7V to 3.6V, or Standard power supply range, 5V 10% Pin compatible with JEDEC standard Atmel AT27C256R
4-megabit (512K x 8) Single 2.7-volt Battery-Voltage Flash Memory AT29BV040A
Features Single Supply Voltage, Range 2.7V to 3.6V Single Supply for Read and Write Software Protected Programming Fast Read Access Time 200 ns Low Power Dissipation 15 ma Active Current 50 µa CMOS Standby
1Mb (128K x 8) Low Voltage, One-time Programmable, Read-only Memory
Features Fast read access time 70ns Dual voltage range operation Low voltage power supply range, 3.0V to 3.6V, or Standard power supply range, 5V 10% Compatible with JEDEC standard Atmel AT27C010 Low-power
IS62WV20488ALL IS62WV20488BLL
2M x 8 HIGH-SPEED LOW POWER CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity
IS62WV102416GALL/BLL IS65WV102416GALL/BLL. 1024Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM. FUNCTIONAL Block Diagram NOVEMBER 2017
1024Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM NOVEMBER 2017 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current: 5.5uA (typ.)
IS61WV25616ALL/ALS IS61WV25616BLL/BLS IS64WV25616BLL/BLS
IS61WV25616ALL/ALS IS61WV25616BLL/BLS 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64WV25616ALL/BLL) High-speed access time: 8, 10, 20 ns Low Active Power: 85 mw (typical)
UM61512A Series 64K X 8 BIT HIGH SPEED CMOS SRAM. Features. General Description. Pin Configurations UM61512AV UM61512A
Series 64K X 8 BIT HIGH SPEE CMOS SRAM Features Single +5V power supply Access times: 15/20/25ns (max.) Current: Operating: 160mA (max.) Standby: 10mA (max.) Full static operation, no clock or refreshing
GLS27SF / 1 / 2 / GLS27SF010 / GLS27SF020
512 Kbit / 1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash FEATURES: GLS27SF512 / 010 / 0205.0V-Read 512Kb / 1Mb / 2Mb (x8) MTP flash memories Organized as 64K x8 / 128K x8 / 256K x8 4.5-5.5V Read Operation
1Mb (64K x 16) Unregulated Battery Voltage, High-speed, One-time Programmable, Read-only Memory
Features Fast read access time 90ns Dual voltage range operation Unregulated battery power supply range, 2.7V to 3.6V, or Standard power supply range, 5V 10% Pin compatible with JEDEC standard Atmel AT27C1024
IS66WV51216DALL IS66/67WV51216DBLL
8Mb LOW VOLTAGE, ULTRA LOW POWER PSEUDO CMOS STATIC RAM FEATURES High-speed access time: 70ns (IS66WV51216DALL, ) 55ns () CMOS low power operation Single power supply Vdd = 1.7V-1.95V (IS66WV51216DALL)
IS62WV25616DALL/DBLL, IS65WV25616DBLL 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM
256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM FEATURES High-speed access time: 35, 45, 55 ns CMOS low power operation 30 mw (typical) operating 6 µw (typical) CMOS standby TTL compatible interface
TMS27C BY 16-BIT UV ERASABLE TMS27PC BY 16-BIT PROGRAMMABLE READ-ONLY MEMORIES
Organization... 262144 by 16 Bits Single 5-V Power Supply All Inputs/ Outputs Fully TTL Compatible Static Operations (No Clocks, No Refresh) Max Access/Min Cycle Time V CC ± 10% 27C/ PC240-10 100 ns 27C/
IS62WV102416ALL IS62WV102416BLL IS65WV102416BLL
1M x 16 HIGH-SPEED LOW POR ASYNCHRONOUS CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater
IS62WV5128EHALL/BLL IS65WV5128EHALL/BLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JULY 2018 DESCRIPTION
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 25 ma (max.) CMOS Standby Current: 3.2 ua (typ., 25 C) TTL
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 10, 12 ns CMOS Low Power Operation 1 mw (typical) CMOS standby 125 mw (typical) operating Fully static operation: no clock
IS61/64WV25616FALL IS61/64WV25616FBLL. 256Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES DESCRIPTION
256Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM APRIL 2018 KEY FEATURES High-speed access time: 8, 10ns, 12ns Low Active Current: 35mA (Max., 10ns, I-temp) Low Standby Current: 10 ma (Max., I-temp) Single
IS65C256AL IS62C256AL
32K x 8 LOW POR CMOS STATIC RAM JULY 2007 FEATURES Access time: 25 ns, 45 ns Low active power: 200 mw (typical) Low standby power 150 µw (typical) CMOS standby 15 mw (typical) operating Fully static operation:
DESCRIPTION DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
IS62C1024 128K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES High-speed access time: 35, 45, 55, 70 ns Low active power: 450 mw (typical) Low standby power: 500 µw (typical) CMOS standby Output Enable () and
IS62WV25616ALL IS62WV25616BLL
IS62WV25616ALL IS62WV25616BLL 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM MARCH 2008 FEATURES High-speed access time: 55ns, 70ns CMOS low power operation 36 mw (typical) operating 9 µw (typical)
IS62WV6416ALL IS62WV6416BLL
IS62WV6416ALL IS62WV6416BLL 64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access time: 45ns, 55ns CMOS low power operation: 30 mw (typical) operating 15 µw (typical)
1Mb (128K x 8) Unregulated Battery Voltage, One-time Programmable, Read-only Memory
Features Fast read access time 90ns Dual voltage range operation Unregulated battery power supply range, 2.7V to 3.6V, or Standard power supply range, 5V 10% Compatible with JEDEC standard Atmel AT27C010
IS62WV20488ALL IS62WV20488BLL
2M x 8 HIGH-SPEED LOW POWER CMOS STATIC RAM August 2016 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity
DESCRIPTION DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY FEATURES High-speed access time: 8, 10 ns High-performance, low-power CMOS process TTL compatible interface levels Single power supply VDD 3.3V ± 5%
256K (32K x 8) Unregulated Battery-Voltage High-Speed OTP EPROM AT27BV256
Features Fast Read Access Time 70 ns Dual Voltage Range Operation Unregulated Battery Power Supply Range, 2.7V to 3.6V or Standard 5V ± 10% Supply Range Pin Compatible with JEDEC Standard AT27C256R Low
IS61WV2568EDBLL IS64WV2568EDBLL
ISWVEDBLL ISWVEDBLL K x HIGH SPEED ASYHRONOUS CMOS STATIC RAM WITH ECC FEATURES High-speed access time:, ns Low Active Power: mw (typical) Low Standby Power: mw (typical) CMOS standby Single power supply
IS61C25616AL IS61C25616AS IS64C25616AL IS64C25616AS
256K x 16 HIGH-SPEED CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64C25616AL) High-speed access time: 10ns, 12 ns Low Active Power: 150 mw (typical) Low Standby Power: 10 mw (typical) CMOS standby LOW POR:
IS62C25616EL, IS65C25616EL
256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM AUGUST 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current: 5.0uA
JANUARY/2008, V 1.0 Alliance Memory Inc. Page 1 of 11
1024K X 8 BIT SUPER 512K LOW POWER X8BITCMOS LOW SRAM FEATURES Fast access time : 55ns Low power consumption: Operating current : 30mA (TYP.) Standby current : 6µA (TYP.) LL-version Single 2.7V ~ 5.5V
IS61WV10248ALL IS61WV10248BLL IS64WV10248BLL
1M x 8 HIGH-SPEED CMOS STATIC RAM MARCH 2017 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity Easy
2Mx32 5V NOR FLASH MODULE
2Mx32 5V NOR FLASH MODULE WF2M32-XXX5 FEATURES Access Time of 90, 120, 150ns Packaging: 66 pin, PGA Type, 1.15" square, Hermetic Ceramic HIP (Package 401). 6 lead, Hermetic CQFP (G2U), 22.4mm (0.0") square
IS61/64WV12816EFALL IS61/64WV12816EFBLL. 128Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES
128Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC KEY FEATURES A0 A17 A16 High-speed access time: 8ns, 10ns, 12ns Single power supply 1.65V-2.2V (IS61/64WV12816EFALL) 2.4V-3.6V () Error Detection
IS61WV102416FALL IS61/64WV102416FBLL. 1Mx16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY FUNCTIONAL BLOCK DIAGRAM
1Mx16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY PRELIMINARY INFORMATION DECEMBER 2016 FEATURES High-speed access time: 8ns, 10ns, 20ns High- performance, low power CMOS process Multiple
IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2017
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current: 3.7uA (typ)
IS61WV20488FALL IS61/64WV20488FBLL. 2Mx8 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY FUNCTIONAL BLOCK DIAGRAM
2Mx8 HIGH-SPEED ASYHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY PRELIMINARY INFORMATION DECEMBER 2016 FEATURES High-speed access time: 8ns, 10ns, 20ns High- performance, low power CMOS process Multiple
IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL
1M x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY MAY 2012 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground pins for
1-Megabit (64K x 16) OTP EPROM AT27C1024
Features Fast Read Access Time 45 ns Low-Power CMOS Operation 100 µa Max Standby 30 ma Max Active at 5 MHz JEDEC Standard Packages 40-lead PDIP 44-lead PLCC 40-lead VSOP Direct Upgrade from 512K (AT27C516)
PY263/PY264. 8K x 8 REPROGRAMMABLE PROM FEATURES DESCRIPTION. EPROM Technology for reprogramming. Windowed devices for reprogramming.
FEATURES EPROM Technology for reprogramming High Speed 25/35/45/55 ns (Commercial) 25/35/45/55 ns (Military) Low Power Operation: 660 mw Commercial 770 mw Military PY263/PY264 8K x 8 REPROGRAMMABLE PROM
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
512K x 8 HIGH-SPEED CMOS STATIC RAM APRIL 2005 FEATURES High-speed access times: 10, 12 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity Easy
IS62WV25616EALL/EBLL/ECLL IS65WV25616EBLL/ECLL. 256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM JANUARY 2018
256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JANUARY 2018 KEY FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current:
IDT CMOS Static RAM 1 Meg (256K x 4-Bit)
CMOS Static RAM 1 Meg (256K x 4-Bit) IDT71028 Features 256K x 4 advanced high-speed CMOS static RAM Equal access and cycle times Commercial and Industrial: 12/15/20ns One Chip Select plus one Output Enable