Z86E04/E08 1 CMOS Z8 OTP MICROCONTROLLERS

Transcription

1 PRELIMINARY PRODUCT SPECIFICATION Z86E04/E08 CMOS Z8 OTP MICROCONTROLLERS PRODUCT DEVICES Part Oscillator Operating Operating ROM Number Type V CC Temperature (KB) Package Z86E042PEC Crystal 4.5V 5.5V 40 C/05 C 8-Pin DIP Z86E042PSC866 Crystal 4.5V 5.5V 0 C/70 C 8-Pin DIP Z86E042PSC903 RC 4.5V 5.5V 0 C/70 C 8-Pin DIP Z86E042PEC903 RC 4.5V 5.5V 40 C/05 C 8-Pin DIP Z86E042SEC Crystal 4.5V 5.5V 40 C/05 C 8-Pin SOIC Z86E042SSC866 Crystal 4.5V 5.5V 0 C/70 C 8-Pin SOIC Z86E042SSC903 RC 4.5V 5.5V 0 C/70 C 8-Pin SOIC Z86E042SEC903 RC 4.5V 5.5V 40 C/05 C 8-Pin SOIC Z86E082PEC Crystal 4.5V 5.5V 40 C/05 C 2 8-Pin DIP Z86E082PSC866 Crystal 4.5V 5.5V 0 C/70 C 2 8-Pin DIP Z86E082PSC903 RC 4.5V 5.5V 0 C/70 C 2 8-Pin DIP Z86E082PEC903 RC 4.5V 5.5V 40 C/05 C 2 8-Pin DIP Z86E082SEC Crystal 4.5V 5.5V 40 C/05 C 2 8-Pin SOIC Z86E082SSC866 Crystal 4.5V 5.5V 0 C/70 C 2 8-Pin SOIC Z86E082SSC903 RC 4.5V 5.5V 0 C/70 C 2 8-Pin SOIC Z86E082SEC903 RC 4.5V 5.5V 40 C/05 C 2 8-Pin SOIC Several key product features of the extensive family of Zilog Z86E04/E08 CMOS OTP microcontrollers are presented in the above table. This table enables the user to identify which of the E04/E08 product variants most closely match the user s application requirements. DS97Z8X04 P R E L I M I N A R Y

2 Z86E04/E08 Zilog FEATURES 4 Input/Output Lines Six Vectored, Prioritized Interrupts (3 falling edge, rising edge, 2 timers) Two Analog Comparators Program Options: Low Noise ROM Protect Auto Latch Watch-Dog Timer (WDT) EPROM/Test Mode Disable Two Programmable 8-Bit Counter/Timers, Each with 6-Bit Programmable Prescaler WDT/ Power-On Reset (POR) On-Chip Oscillator that Accepts XTAL, Ceramic Resonance, LC, RC, or External Clock Clock-Free WDT Reset Low-Power Consumption (50 mw typical) Fast Instruction Pointer 2 MHz) RAM Bytes (25) GENERAL DESCRIPTION Zilog's Z86E04/E08 Microcontrollers (MCU) are One-Time Programmable (OTP) members of Zilog s single-chip Z8 MCU family that allow easy software development, debug, prototyping, and small production runs not economically desirable with masked ROM versions. For applications demanding powerful I/O capabilities, the Z86E04/E08's dedicated input and output lines are grouped into three ports, and are configurable under software control to provide timing, status signals, or parallel I/O. Note: All Signals with an overline,, are active Low, for example: B/W (WORD is active Low); B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Circuit Device Power V CC V DD Ground GND V SS Two on-chip counter/timers, with a large number of user selectable modes, offload the system of administering real-time tasks such as counting/timing and I/O data communications. 2 P R E L I M I N A R Y DS97Z8X04

3 Zilog Z86E04/E08 Input Vcc GND XTAL Port 3 Machine Timing & Inst. Control Counter/ Timers (2) ALU Interrupt Control FLAG OTP Two Analog Comparators Register Pointer General-Purpose Register File Program Counter Port 2 Port 0 I/O (Bit Programmable) I/O Figure. Functional Block Diagram DS97Z8X04 P R E L I M I N A R Y 3

4 Z86E04/E08 Zilog GENERAL DESCRIPTION (Continued) D7 0 Z8 MCU AD 0 0 AD 0 0 Address MUX Clear P00 Clock P0 Address Counter PGM Mode Logic 3 bits AD 0 0 EPROM ROM PROT Low Noise D7 0 Data MUX D7 0 Z8 Port 2 EPM P32 PGM P30 CE XT VPP P33 OE P3 Figure 2. EPROM Programming Mode Block Diagram 4 P R E L I M I N A R Y DS97Z8X04

5 Zilog Z86E04/E08 PIN DESCRIPTION D4 D5 D6 D7 V CC NC CE OE EPM D3 D2 D D0 GND PGM CLOCK CLEAR V PP P24 P25 P26 P27 V CC XTAL2 XTAL P3 P P23 P22 P2 P20 GND P02 P0 P00 P33 Figure 3. 8-Pin EPROM Mode Configuration Figure 4. 8-Pin DIP/SOIC Mode Configuration Table. 8-Pin DIP Pin Identification EPROM Programming Mode Pin # Symbol Function Direction 4 D4 D7 Data 4, 5, 6, 7 In/Output 5 V CC Power Supply 6 NC No Connection 7 CE Chip Enable Input 8 OE Output Enable Input 9 EPM EPROM Prog Mode Input 0 V PP Prog Voltage Input Clear Clear Clock Input 2 Clock Address Input 3 PGM Prog Mode Input 4 GND Ground 5 8 D0 D3 Data 0,, 2, 3 In/Output Table 2. 8-Pin DIP/SOIC Pin Identification Standard Mode Pin # Symbol Function Direction 4 P24 P27 Port 2, Pins 4,5,6,7 In/Output 5 V CC Power Supply 6 XTAL2 Crystal Osc. Clock Output 7 XTAL Crystal Osc. Clock Input 8 P3 Port 3, Pin, AN Input 9 P32 Port 3, Pin 2, AN2 Input 0 P33 Port 3, Pin 3, REF Input 3 P00 P02 Port 0, Pins 0,,2 In/Output 4 GND Ground 5 8 P20 P23 Port 2, Pins 0,,2,3 In/Output DS97Z8X04 P R E L I M I N A R Y 5

6 Z86E04/E08 ABSOLUTE MAXIMUM RATINGS Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Total power Zilog dissipation should not exceed 462 mw for the package. Power dissipation is calculated as follows: Total Power Dissipation = V DD x [I DD (sum of I OH )] + sum of [(V DD V OH ) x I OH ] + sum of (V 0L x I 0L ) Parameter Min Max Units Note Ambient Temperature under Bias C Storage Temperature C Voltage on any Pin with Respect to V SS V Voltage on V DD Pin with Respect to V SS V Voltage on Pins 7, 8, 9, 0 with Respect to V SS 0.6 V DD + V 2 Total Power Dissipation.65 W Maximum Allowable Current out of V SS 300 ma Maximum Allowable Current into V DD 220 ma Maximum Allowable Current into an Input Pin µa 3 Maximum Allowable Current into an Open-Drain Pin µa 4 Maximum Allowable Output Current Sinked by Any I/O Pin 25 ma Maximum Allowable Output Current Sourced by Any I/O Pin 25 ma Total Maximum Output Current Sinked by a Port 60 ma Total Maximum Output Current Sourced by a Port 45 ma Notes:. This applies to all pins except where otherwise noted. Maximum current into pin must be ± 600 µa. 2. There is no input protection diode from pin to V DD (not applicable to EPROM Mode). 3. This excludes Pin 6 and Pin Device pin is not at an output Low state. 6 P R E L I M I N A R Y DS97Z8X04

7 Zilog Z86E04/E08 STANDARD TEST CONDITIONS The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Figure 5). From Output Under Test 50 pf Figure 5. Test Load Diagram CAPACITANCE T A = 25 C, V CC = GND = 0V, f =.0 MHz, unmeasured pins returned to GND. Parameter Min Max Input capacitance 0 0 pf Output capacitance 0 20 pf I/O capacitance 0 25 pf DS97Z8X04 P R E L I M I N A R Y 7

8 Z86E04/E08 Zilog DC ELECTRICAL CHARACTERISTICS Standard Temperature T A = 0 C to +70 C Typical Sym Parameter V CC [4] Min 25 C Units Conditions Notes V INMAX Max Input Voltage 4.5V 2 V I In <250 µa 5.5V 2 V I In <250 µa V CH V CL Clock Input High Voltage Clock Input Low Voltage V IH Input High Voltage 4.5V 5.5V V IL Input Low Voltage 4.5V 5.5V 4.5V 0.8 V CC V CC V Driven by External Clock Generator 5.5V 0.8 V CC V CC V Driven by External Clock Generator 4.5V V SS V CC.7 V Driven by External Clock Generator 5.5V V SS V CC.7 V Driven by External Clock Generator 0.7 V CC V CC V CC V CC +0.3 V SS 0.3 V SS V CC V CC.5 V OH Output High Voltage 4.5V V CC V I OH = 2.0 ma 5 5.5V V CC V I OH = 2.0 ma 5 4.5V V CC V Low I OH = 0.5 ma 5.5V V CC V Low I OH = 0.5 ma V OL Output Low Voltage 4.5V V I OL = +4.0 ma 5 5.5V V I OL = +4.0 ma 5 4.5V V Low I OL =.0 ma 5.5V V Low I OL =.0 ma V OL2 Output Low Voltage 4.5V V I OL = +2 ma, 5 5.5V V I OL = +2 ma, 5 V OFFSET Comparator Input 4.5V mv Offset Voltage 5.5V mv V LV V CC Low Voltage Auto Reset MHz Max. Int. CLK Freq. I IL Input Leakage 4.5V.0.0 µa V IN = 0V, V CC (Input Bias Current of Comparator) 5.5V.0.0 µa V IN = 0V, V CC I OL Output Leakage 4.5V.0.0 µa V IN = 0V, V CC V V V V V ICR Comparator Input Common Mode Voltage Range 5.5V.0.0 µa V IN = 0V, V CC 0 V CC.0 V 8 P R E L I M I N A R Y DS97Z8X04

9 Zilog Z86E04/E08 T A = 0 C to +70 C Typical Sym Parameter V CC [4] Min 25 C Units Conditions Notes I CC Supply Current 4.5V ma All Output and I/O Pins 5,7 2 MHz 5.5V ma All Output and I/O Pins 5,7 2 MHz 4.5V ma All Output and I/O Pins 5,7 8 MHz 5.5V ma All Output and I/O Pins 5,7 8 MHz 4.5V ma All Output and I/O Pins 5,7 2 MHz 5.5V ma All Output and I/O Pins 5,7 2 MHz I CC Standby Current 4.5V ma HALT Mode V IN = 0V, 5,7 V 2 MHz 5.5V ma HALT Mode V IN = 0V, 5,7 V 2 MHz 4.5V ma HALT Mode V IN = 0V, 5,7 V 8 MHz 5.5V ma HALT Mode V IN = 0V, 5,7 V 8 MHz 4.5V ma HALT Mode V IN = 0V, 5,7 V 2 MHz 5.5V ma HALT Mode V IN = 0V, 5,7 V 2 MHz I CC Supply Current 4.5V ma All Output and I/O Pins 7 (Low Noise Mode) MHz 5.5V ma All Output and I/O Pins 7 MHz 4.5V ma All Output and I/O Pins 7 2 MHz 5.5V ma All Output and I/O Pins 7 2 MHz 4.5V ma All Output and I/O Pins 7 4 MHz 5.5V ma All Output and I/O Pins 4 MHz 7 DS97Z8X04 P R E L I M I N A R Y 9

10 Z86E04/E08 Zilog DC ELECTRICAL CHARACTERISTICS (Continued) T A = 0 C to +70 C Typical Sym Parameter V CC [4] Min 25 C Units Conditions Notes I CC Standby Current (Low Noise Mode) 4.5V ma HALT Mode V IN = 0V, V MHz 5.5V ma HALT Mode V IN = 0V, V MHz 4.5V ma HALT Mode V IN = 0V, V 2 MHz 5.5V ma HALT Mode V IN = 0V, V 2 MHz 4.5V ma HALT Mode V IN = 0V, V 4 MHz 5.5V ma HALT Mode V IN = 0V, V 4 MHz I CC2 Standby Current 4.5V µa STOP Mode V IN = 0V, V CC WDT is not Running 5.5V µa STOP Mode V IN = 0V,V CC WDT is not Running I ALL Auto Latch Low 4.5V µa 0V < V IN < V CC Current 5.5V µa 0V < V IN < V CC I ALH Auto Latch High Current 4.5V µa 0V < V IN < V CC 5.5V µa 0V < V IN < V CC Notes:. Port 2 and Port 0 only 2. V SS = 0V = GND 3. The device operates down to V LV of the specified frequency for V LV. The minimum operational V CC is determined on the value of the voltage V LV at the ambient temperature. The V LV increases as the temperature decreases. 4. V CC = 4.5 to 5.5V, typical values measured at V CC = 5.0V. The V CC voltage specification of 5.5 V guarantees 5.0 V ± 0.5V with typical values measured at V CC = 5.0V. 5. Standard Mode (not Low EMI Mode) 6. Z86E08 only 7. All outputs unloaded and all inputs are at V CC or V SS level. 8. If analog comparator is selected, then the comparator inputs must be at V CC level ,8 7,8 0 P R E L I M I N A R Y DS97Z8X04

11 Zilog Z86E04/E08 DC ELECTRICAL CHARACTERISTICS Extended Temperature T A = 40 C to +05 C Typical Sym Parameter V CC [4] Min 25 C Units Conditions Notes V INMAX Max Input Voltage 4.5V 2.0 V I IN < 250 µa 5.5V 2.0 V I IN < 250 µa V CH V CL Clock Input High Voltage Clock Input Low Voltage 4.5V 0.8 V CC V CC V Driven by External Clock Generator 5.5V 0.8 V CC V CC V Driven by External Clock Generator 4.5V V SS V CC.7 V Driven by External Clock Generator 5.5V V SS V CC.7 V Driven by External Clock Generator V IH Input High Voltage 4.5V 0.7 V CC V CC V 5.5V 0.7 V CC V CC V V IL Input Low Voltage 4.5V V SS V CC.5 V 5.5V V SS V CC.5 V V OH Output High Voltage 4.5V V CC V I OH = 2.0 ma 5 5.5V V CC V I OH = 2.0 ma 5 4.5V V CC 0.4 V Low I OH = 0.5 ma 5.5V V CC 0.4 V Low I OH = 0.5 ma V OL Output Low Voltage 4.5V V I OL = +4.0 ma 5 5.5V V I OL = +4.0 ma 5 4.5V V Low I OL =.0 ma 5.5V V Low I OL =.0 ma V OL2 Output Low Voltage 4.5V V I OL = +2 ma, 5 5.5V V I OL = +2 ma, 5 V OFFSET Comparator Input 4.5V mv Offset Voltage 5.5V mv V LV V CC Low Voltage Auto Reset MHz Max. Int. CLK Freq. 3 I IL Input Leakage 4.5V.0.0 µa V IN = 0V, V CC (Input Bias Current of Comparator) 5.5V.0.0 µa V IN = 0V, V CC I OL Output Leakage 4.5V.0.0 µa V IN = 0V, V CC V ICR Comparator Input Common Mode Voltage Range 5.5V.0.0 µa V IN = 0V, V CC 0 V CC.5 V DS97Z8X04 P R E L I M I N A R Y

12 Z86E04/E08 Zilog DC ELECTRICAL CHARACTERISTICS (Continued) T A = 40 C to +05 C Typical Sym Parameter V CC [4] Min 25 C Units Conditions Notes I CC Supply Current 4.5V ma All Output and I/O Pins 2 MHz 5.5V ma All Output and I/O Pins 2 MHz 4.5V ma All Output and I/O Pins 8 MHz 5.5V ma All Output and I/O Pins 8 MHz 4.5V ma All Output and I/O Pins 2 MHz 5.5V ma All Output and I/O Pins 2 MHz I CC Standby Current 4.5V ma HALT Mode V IN = 0V, V 2 MHz 5.5V ma HALT Mode V IN = 0V, V 2 MHz 4.5V ma HALT Mode V IN = 0V, V 8 MHz 5.5V ma HALT Mode V IN = 0V, V 8 MHz 4.5V ma HALT Mode V IN = 0V, V 2 MHz 5.5V ma HALT Mode V IN = 0V, V 2 MHz I CC Supply Current 4.5V ma All Output and I/O Pins (Low Noise Mode) MHz 5.5V ma All Output and I/O Pins MHz 4.5V ma All Output and I/O Pins 2 MHz 5.5V ma All Output and I/O Pins 2 MHz 4.5V ma All Output and I/O Pins 4 MHz 5.5V ma All Output and I/O Pins 4 MHz 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5,7 5, P R E L I M I N A R Y DS97Z8X04

13 Zilog Z86E04/E08 T A = 40 C to +05 C Typical Sym Parameter V CC [4] Min 25 C Units Conditions Notes I CC Standby Current (Low Noise Mode) 4.5V ma HALT Mode V IN = 0V, V MHz 5.5V ma HALT Mode V IN = 0V, V MHz 4.5V ma HALT Mode V IN = 0V, V 2 MHz 5.5V ma HALT Mode V IN = 0V, V 2 MHz 4.5V ma HALT Mode V IN = 0V, V 4 MHz 5.5V ma HALT Mode V IN = 0V, V 4 MHz I CC2 Standby Current 4.5V 20.0 µa STOP Mode V IN = 0V, V CC WDT is not Running 5.5V 20.0 µa STOP Mode V IN = 0V, V CC WDT is not Running I ALL Auto Latch Low 4.5V 40 6 µa 0V < V IN < V CC Current 5.5V 40 6 µa 0V < V IN < V CC I ALH Auto Latch High Current 4.5V µa 0V < V IN < V CC 5.5V µa 0V < V IN < V CC Notes:. Port 2 and Port 0 only 2. V SS = 0V = GND 3. The device operates down to V LV of the specified frequency for V LV. The minimum operational V CC is determined on the value of the voltage V LV at the ambient temperature. The V LV increases as the temperature decreases. 4. V CC = 4.5V to 5.5V, typical values measured at V CC = 5.0V 5. Standard Mode (not Low EMI Mode) 6. Z86E08 only 7. All outputs unloaded and all inputs are at V CC or V SS level. 8. If analog comparator is selected, then the comparator inputs must be at V CC level ,8 7,8 DS97Z8X04 P R E L I M I N A R Y 3

14 Z86E04/E08 Zilog AC ELECTRICAL CHARACTERISTICS 3 Clock T IN IRQ N 8 9 Figure 6. AC Electrical Timing Diagram 4 P R E L I M I N A R Y DS97Z8X04

15 Zilog Z86E04/E08 AC ELECTRICAL CHARACTERISTICS Timing Table (Standard Mode for SCLK/TCLK = XTAL/2) Standard Temperature 5 T A = 0 C to +70 C 8 MHz 2 MHz No Symbol Parameter V CC Min Max Min Max Units Notes TpC Input Clock Period 4.5V 25 DC 83 DC ns 5.5V 25 DC 83 DC ns 2 TrC,TfC Clock Input Rise and Fall Times 4.5V 25 5 ns 5.5V 25 5 ns 3 TwC Input Clock Width 4.5V 62 4 ns 5.5V 62 4 ns 4 TwTinL Timer Input Low Width 4.5V ns 5.5V ns 5 TwTinH Timer Input High Width 4.5V 5TpC 5TpC 5.5V 5TpC 5TpC 6 TpTin Timer Input Period 4.5V 8TpC 8TpC 5.5V 8TpC 8TpC 7 TrTin, TtTin Timer Input Rise and Fall Time 8 TwIL Int. Request Input Low Time 9 TwIH Int. Request Input High Time 0 Twdt Watch-Dog Timer Delay Time for Timeout 4.5V ns 5.5V ns 4.5V ns,2 5.5V ns,2 4.5V 5TpC 5TpC,2 5.5V 5TpC 5TpC,2 4.5V 2 2 ms 5.5V 2 2 ms Tpor Power-On Reset Time 4.5V ms 5.5V ms Notes:. Timing Reference uses 0.7 V CC for a logic and 0.2 V CC for a logic Interrupt request through Port 3 (P33 P3). DS97Z8X04 P R E L I M I N A R Y 5

16 Z86E04/E08 Zilog AC ELECTRICAL CHARACTERISTICS Timing Table (Standard Mode for SCLK/TCLK = XTAL/2) Extended Temperature T A = 40 C to +05 C 8 MHz 2 MHz No Symbol Parameter V CC Min Max Min Max Units Notes TpC Input Clock Period 4.5V 25 DC 83 DC ns 5.5V 25 DC 83 DC ns 2 TrC,TfC Clock Input Rise and Fall Times 4.5V 25 5 ns 5.5V 25 5 ns 3 TwC Input Clock Width 4.5V 62 4 ns 5.5V 62 4 ns 4 TwTinL Timer Input Low Width 4.5V ns 5.5V ns 5 TwTinH Timer Input High Width 4.5V 5TpC 5TpC 5.5V 5TpC 5TpC 6 TpTin Timer Input Period 4.5V 8TpC 8TpC 5.5V 8TpC 8TpC 7 TrTin, TtTin Timer Input Rise and Fall Time 8 TwIL Int. Request Input Low Time 9 TwIH Int. Request Input High Time 0 Twdt Watch-Dog Timer Delay Time for Timeout 4.5V ns 5.5V ns 4.5V ns,2 5.5V ns,2 4.5V 5TpC 5TpC,2 5.5V 5TpC 5TpC,2 4.5V 0 0 ms 5.5V 0 0 ms Tpor Power-On Reset Time 4.5V ms 5.5V ms Notes:. Timing Reference uses 0.7 V CC for a logic and 0.2 V CC for a logic Interrupt request made through Port 3 (P33 P3). 6 P R E L I M I N A R Y DS97Z8X04

17 Zilog Z86E04/E08 AC ELECTRICAL CHARACTERISTICS Low Noise Mode, Standard Temperature T A = 0 C to +70 C MHz 4 MHz No Symbol Parameter V CC Min Max Min Max Units Notes TPC Input Clock Period 4.5V 000 DC 250 DC ns 5.5V 000 DC 250 DC ns 2 TrC TfC Clock Input Rise and Fall Times 4.5V ns 5.5V ns 3 TwC Input Clock Width 4.5V ns 5.5V ns 4. TwTinL Timer Input Low Width 4.5V ns 5.5V ns 5 TwTinH Timer Input High Width 4.5V 2.5TpC 2.5TpC 5.5V 2.5TpC 2.5TpC 6 TpTin Timer Input Period 4.5V 4TpC 4TpC 5.5V 4TpC 4TpC 7 TrTin, TtTin 8 TwIL Low Time 9 TwIH High Time Timer Input Rise 4.5V ns and Fall Time 5.5V ns Int. Request Input 4.5V ns,2 5.5V ns,2 Int. Request Input 4.5V 2.5TpC 2.5TpC,2 5.5V 2.5TpC 2.5TpC,2 0 Twdt Watch-Dog Timer Delay Time for Timeout Notes:. Timing Reference uses 0.7 V CC for a logic and 0.2 V CC for a logic Interrupt request through Port 3 (P33 P3). 4.5V 2 2 ms 5.5V 2 2 ms DS97Z8X04 P R E L I M I N A R Y 7

18 Z86E04/E08 Zilog AC ELECTRICAL CHARACTERISTICS (Continued) Low Noise Mode, Extended Temperature T A = 40 C to +05 C MHz 4 MHz No Symbol Parameter V CC Min Max Min Max Units Notes TPC Input Clock Period 4.5V 000 DC 250 DC ns 5.5V 000 DC 250 DC ns 2 TrC TfC Clock Input Rise and Fall Times 4.5V ns 5.5V ns 3 TwC Input Clock Width 4.5V ns 5.5V ns 4. TwTinL Timer Input Low Width 4.5V ns 5.5V ns 5 TwTinH Timer Input High Width 4.5V 2.5TpC 2.5TpC 5.5V 2.5TpC 2.5TpC 6 TpTin Timer Input Period 4.5V 4TpC 4TpC 5.5V 4TpC 4TpC 7 TrTin, TtTin Timer Input Rise and Fall Time 8 TwIL Int. Request Input Low Time 9 TwIH Int. Request Input High Time 0 Twdt Watch-Dog Timer Delay Time for Timeout Notes:. Timing Reference uses 0.7 V CC for a logic and 0.2 V CC for a logic Interrupt request through Port 3 (P33 P3). 4.5V ns 5.5V ns 4.5V ns,2 5.5V ns,2 4.5V 2.5TpC 2.5TpC,2 5.5V 2.5TpC 2.5TpC,2 4.5V 0 0 ms 5.5V 0 0 ms 8 P R E L I M I N A R Y DS97Z8X04

19 Zilog Z86E04/E08 LOW NOISE VERSION Low EMI Emission The Z86E04/E08 can be programmed to operate in a Low EMI Emission Mode by means of a mask ROM bit option. Use of this feature results in: All pre-driver slew rates reduced to 0 ns typical. Internal SCLK/TCLK operation limited to a maximum of 4 MHz 250 ns cycle time. Output drivers have resistances of 500 Ohms (typical). Oscillator divide-by-two circuitry eliminated. The Low EMI Mode is mask-programmable to be selected by the customer at the time the ROM code is submitted. PIN FUNCTIONS OTP Programming Mode D7 D0 Data Bus. Data can be read from, or written to, the EPROM through this data bus. V CC Power Supply. It is typically 5V during EPROM Read Mode and 6.4V during the other modes (Program, Program Verify, and so on). CE Chip Enable (active Low). This pin is active during EPROM Read Mode, Program Mode, and Program Verify Mode. OE Output Enable (active Low). This pin drives the Data Bus direction. When this pin is Low, the Data Bus is output. When High, the Data Bus is input. EPM EPROM Program Mode. This pin controls the different EPROM Program Modes by applying different voltages. V PP Program Voltage. This pin supplies the program voltage. Clear Clear (active High). This pin resets the internal address counter at the High Level. Clock Address Clock. This pin is a clock input. The internal address counter increases by one with one clock cycle. PGM Program Mode (active Low). A Low level at this pin programs the data to the EPROM through the Data Bus. Application Precaution The production test-mode environment may be enabled accidentally during normal operation if excessive noise surges above V CC occur on the XTAL pin. In addition, processor operation of Z8 OTP devices may be affected by excessive noise surges on the V PP, CE, EPM, OE pins while the microcontroller is in Standard Mode. Recommendations for dampening voltage surges in both test and OTP Mode include the following: Using a clamping diode to V CC. Adding a capacitor to the affected pin. Note: Programming the EPROM/Test Mode Disable option will prevent accidental entry into EPROM Mode or Test Mode. DS97Z8X04 P R E L I M I N A R Y 9

20 Z86E04/E08 Zilog PIN FUNCTIONS (Continued) XTAL, XTAL2 Crystal In, Crystal Out (time-based input and output, respectively). These pins connect a parallelresonant crystal, LC, or an external single-phase clock (8 MHz or 2 MHz max) to the on-chip clock oscillator and buffer. Port 0, P02 P00. Port 0 is a 3-bit bidirectional, Schmitttriggered CMOS-compatible I/O port. These three I/O lines can be globally configured under software control to be inputs or outputs (Figure 7). Auto Latch. The Auto Latch puts valid CMOS levels on all CMOS inputs (except P33, P32, P3) that are not externally driven. A valid CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer. On Power-up and Reset, the Auto Latch will set the ports to an undetermined state of 0 or. Default condition is Auto Latches enabled. Z8 Port 0 (I/O) OE PAD Out Hysteresis 5.0V CC In Auto Latch Option R 500 kω Figure 7. Port 0 Configuration 20 P R E L I M I N A R Y DS97Z8X04

21 Zilog Port 2, P27 P20. Port 2 is an 8-bit, bit programmable, bidirectional, Schmitt-triggered CMOS-compatible I/O port. These eight I/O lines can be configured under software Z86E04/E08 control to be inputs or outputs, independently. Bits programmed as outputs can be globally programmed as either push-pull or open-drain (Figure 8). Z8 Port 2 (I/O) Open-Drain /OE PAD Out Hysteresis 5.0V In Auto Latch Option R 500 kω Figure 8. Port 2 Configuration DS97Z8X04 P R E L I M I N A R Y 2

22 Z86E04/E08 Zilog PIN FUNCTIONS (Continued) Port 3, P33 P3. Port 3 is a 3-bit, CMOS-compatible port with three fixed input (P33 P3) lines. These three input lines can be configured under software control as digital Schmitt-trigger inputs or analog inputs. These three input lines are also used as the interrupt sources IRQ0 IRQ3, and as the timer input signal T IN (Figure 9). Z86E04 Z8 and Z86E08 Port 3 R247 = P3M 0 = Digital = Analog D PAD P3 (AN) + - DIG. AN. TIN P3 Data Latch IRQ2 IRQ3 PAD PAD P32 (AN2) P33 (REF) + - P32 Data Latch IRQ0 Vcc P33 Data Latch IRQ IRQ 0,,2 = Falling Edge Detection IRQ3 = Rising Edge Detection Figure 9. Port 3 Configuration 22 P R E L I M I N A R Y DS97Z8X04

23 Zilog Comparator Inputs. Two analog comparators are added to input of Port 3, P3, and P32, for interface flexibility. The comparators reference voltage P33 (REF) is common to both comparators. Typical applications for the on-board comparators; Zero crossing detection, A/D conversion, voltage scaling, and threshold detection. In Analog Mode, P33 input functions serve as a reference voltage to the comparators. The dual comparator (common inverting terminal) features a single power supply which discontinues power in STOP Z86E04/E08 Mode. The common voltage range is 0 4 V when the V CC is 5.0V; the power supply and common mode rejection ratios are 90 db and 60 db, respectively. Interrupts are generated on either edge of Comparator 2's output, or on the falling edge of Comparator 's output. The comparator output is used for interrupt generation, Port 3 data inputs, or T IN through P3. Alternatively, the comparators can be disabled, freeing the reference input (P33) for use as IRQ and/or P33 input. FUNCTIONAL DESCRIPTION The following special functions have been incorporated into the Z8 devices to enhance the standard Z8 core architecture to provide the user with increased design flexibility. RESET. This function is accomplished by means of a Power-On Reset or a Watch-Dog Timer Reset. Upon powerup, the Power-On Reset circuit waits for T POR ms, plus 8 clock cycles, then starts program execution at address 000C (Hex) (Figure 0). The Z8 control registers' reset value is shown in Table 3. INT OSC XTAL OSC POR (Cold Start) Delay Line TPOR msec 8 CLK Reset Filiter Chip Reset P27 (Stop Mode) Figure 0. Internal Reset Configuration Power-On Reset (POR). A timer circuit clocked by a dedicated on-board RC oscillator is used for a POR timer function. The POR time allows V CC and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of the four following conditions: Watch-Dog Timer Reset. The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT is initially enabled by executing the WDT instruction and is retriggered on subsequent execution of the WDT instruction. The timer circuit is driven by an onboard RC oscillator. Power-bad to power-good status Stop-Mode Recovery WDT time-out WDH time-out DS97Z8X04 P R E L I M I N A R Y 23

24 Z86E04/E08 Zilog FUNCTIONAL DESCRIPTION (Continued) Table 3. Control Registers Reset Condition Addr. Reg. D7 D6 D5 D4 D3 D2 D D0 Comments FF SPL FD RP FC FLAGS U U U U U U U U FB IMR 0 U U U U U U U FA IRQ U U IRQ3 is used for positive edge detection F9 IPR U U U U U U U U F8* P0M U U U 0 U U 0 F7* P3M U U U U U U 0 0 F6* P2M Inputs after reset F5 PRE0 U U U U U U U 0 F4 T0 U U U U U U U U F3 PRE U U U U U U 0 0 F2 T U U U U U U U U F TMR Note: *Registers are not reset after a STOP-Mode Recovery using P27 pin. A subsequent reset will cause these control registers to be reconfigured as shown in Table 4 and the user must avoid bus contention on the port pins or it may affect device reliability. 24 P R E L I M I N A R Y DS97Z8X04

25 Zilog Program Memory. The Z86E04/E08 addresses up to K/2KB of Internal Program Memory (Figure ). The first 2 bytes of program memory are reserved for the interrupt vectors. These locations contain six 6-bit vectors that correspond to the six available interrupts. Bytes 0 024/2048 are on-chip one-time programmable ROM. Z86E04/E08 Register File. The Register File consists of three I/O port registers, 24 general-purpose registers, and 4 control and status registers R0 R3, R4 R27 and R24 R255, respectively (Figure 2). General-purpose registers occupy the 04H to 7FH address space. I/O ports are mapped as per the existing CMOS Z8. 023/2047 Location of First Byte of Instruction Executed After RESET Interrupt Vector (Lower Byte) Interrupt Vector (Upper Byte) On-Chip ROM IRQ5 IRQ5 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ IRQ Identifiers 3FFH/7FFH 3FH/7FFH 0CH 0BH 0AH 09H 08H 07H 06H 05H 04H 03H 02H Location 255 (FFH) 254 (FE) 253 (FD) 252 (FC) 25 (FB) 250 (FA) 249 (F9) 248 (F8) 247 (F7) 246 (F6) 245 (F5) 244 (F4) 243 (F3) Stack Pointer (Bits 7-0) General-Purpose Register Register Pointer Program Control Flags Interrupt Mask Register Interrupt Request Register Interrupt Priority Register Ports 0- Mode Port 3 Mode Port 2 Mode T0 Prescaler Timer/Counter 0 T Prescaler Identifiers SPL GPR RP FLAGS IMR IRQ IPR P0M P3M P2M PRE0 T0 PRE IRQ0 0H 242 (F2) Timer/Counter T 0 IRQ0 00H 24 (FH) Timer Mode TMR Figure. Program Memory Map (7FH) 4 Not Implemented General-Purpose Registers (00H) Port 3 Port 2 Reserved Port 0 P3 P2 P P0 Figure 2. Register File DS97Z8X04 P R E L I M I N A R Y 25

26 Z86E04/E08 Zilog FUNCTIONAL DESCRIPTION (Continued) The Z8 instructions can access registers directly or indirectly through an 8-bit address field. This allows short 4-bit register addressing using the Register Pointer. In the 4-bit mode, the register file is divided into eight working register groups, each occupying 6 continuous locations. The Register Pointer (Figure 3) addresses the starting location of the active working-register group. FF F0 7F 70 6F 60 5F 50 4F 40 3F 30 2F 20 F 0 0F 00 r7 r6 r5 r4 r3 r2 r r0 R253 (Register Pointer) The upper nibble of the register file address provided by the register pointer specifies the active working-register group. Register Group F Specified Working Register Group Register Group Register Group 0 I/O Ports *Expanded Register Group (0) is selected in this figure by handling bits D3 to D0 as "0" in Register R253(RP). R5 to R0 The lower nibble of the register file address provided by the instruction points to the specified register. R5 to R0 R5 to R4* R3 to R0 Stack Pointer. The Z8 has an 8-bit Stack Pointer (R255) used for the internal stack that resides within the 24 general-purpose registers. General-Purpose Registers (GPR). These registers are undefined after the device is powered up. The registers keep their last value after any reset, as long as the reset occurs in the V CC voltage-specified operating range. Note: Register R254 has been designated as a general-purpose register and is set to 00 Hex after any reset or Stop-Mode Recovery. Counter/Timer. There are two 8-bit programmable counter/timers (T0 and T), each driven by its own 6-bit programmable prescaler. The T prescaler is driven by internal or external clock sources; however, the T0 can be driven by the internal clock source only (Figure 4). The 6-bit prescalers divide the input frequency of the clock source by any integer number from to 64. Each prescaler drives its counter, which decrements the value ( to 256) that has been loaded into the counter. When both counter and prescaler reach the end of count, a timer interrupt request IRQ4 (T0) or IRQ5 (T) is generated. The counter can be programmed to start, stop, restart to continue, or restart from the initial value. The counters are also programmed to stop upon reaching zero (Single-Pass Mode) or to automatically reload the initial value and continue counting (Modulo-N Continuous Mode). The counters, but not the prescalers, are read at any time without disturbing their value or count mode. The clock source for T is user-definable and is either the internal microprocessor clock divided by four, or an external signal input through Port 3. The Timer Mode register configures the external timer input (P3) as an external clock, a trigger input that is retriggerable or non-retriggerable, or used as a gate input for the internal clock. Figure 3. Register Pointer 26 P R E L I M I N A R Y DS97Z8X04

27 Zilog Z86E04/E08 Internal Data Bus Write Write Read OSC PRE0 Initial Value Register T0 Initial Value Register T0 Current Value Register 2 * 4 6-Bit Down Counter 8-bit Down Counter IRQ4 Internal Clock External Clock Clock Logic 4 6-Bit Down Counter 8-Bit Down Counter IRQ5 Internal Clock Gated Clock Triggered Clock PRE Initial Value Register T Initial Value Register T Current Value Register TIN P3 Write Write Read Internal Data Bus * Note: By passed, if Low EMI Mode is selected. Figure 4. Counter/Timers Block Diagram DS97Z8X04 P R E L I M I N A R Y 27

28 Z86E04/E08 Zilog FUNCTIONAL DESCRIPTION (Continued) Interrupts. The Z8 has six interrupts from six different sources. These interrupts are maskable and prioritized (Figure 5). The sources are divided as follows: the falling edge of P3 (AN), P32 (AN2), P33 (REF), the rising edge of P32 (AN2), and two counter/timers. The Interrupt Mask Register globally or individually enables or disables the six interrupt requests (Table 4). When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register. All Z8 interrupts are vectored through locations in program memory. When an Interrupt machine cycle is activated, an Interrupt Request is granted. This disables all subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt. This memory location and the next byte contain the 6-bit starting address of the interrupt service routine for that particular interrupt request. To accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests needs service. Note: User must select any Z86E08 mode in Zilog's C2 ICEBOX emulator. The rising edge interrupt is not supported on the CCP emulator (a hardware/software workaround must be employed). Table 4. Interrupt Types, Sources, and Vectors Vector Name Source Location Comments IRQ0 AN2(P32) 0, External (F)Edge IRQ REF(P33) 2,3 External (F)Edge IRQ2 AN(P3) 4,5 External (F)Edge IRQ3 AN2(P32) 6,7 External (R)Edge IRQ4 T0 8,9 Internal IRQ5 T 0, Internal Notes: F = Falling edge triggered R = Rising edge triggered IRQ0 - IRQ5 IRQ IMR Global Interrupt Enable IPR 6 Interrupt Request PRIORITY LOGIC Vector Select Figure 5. Interrupt Block Diagram 28 P R E L I M I N A R Y DS97Z8X04

29 Zilog Clock. The Z8 on-chip oscillator has a high-gain, parallelresonant amplifier for connection to a crystal, LC, RC, ceramic resonator, or any suitable external clock source (XTAL = INPUT, XTAL2 = OUTPUT). The crystal should be AT cut, up to 2 MHz max., with a series resistance (RS) of less than or equal to 00 Ohms. Z86E04/E08 The crystal should be connected across XTAL and XTAL2 using the vendors crystal recommended capacitors from each pin directly to device ground pin 4 (Figure 6). Note that the crystal capacitor loads should be connected to V SS, Pin 4 to reduce Ground noise injection. C * XTAL XTAL XTAL C C * L * R XTAL C2 XTAL2 C2 XTAL2 XTAL2 XTAL2 * * Ceramic Resonator or Crystal C, C2 = 47 pf TYP * F = 8 MHz LC External Clock 5V Vcc (TYP) C = 00 pf R = 2K F = 6 MHz * Typical value including pin parasitics Figure 6. Oscillator Configuration DS97Z8X04 P R E L I M I N A R Y 29

30 Z86E04/E08 Zilog FUNCTIONAL DESCRIPTION (Continued) Table 5. Typical Frequency vs. RC Values V CC = 25 C Load Capacitor 33 pfd 56 pfd 00 pfd 0.00 µfd Resistor (R) A(Hz) B(Hz) A(Hz) B(Hz) A(Hz) B(Hz) A(Hz) B(Hz).0M 33K 3K 20K 20K 2K K.4K.4K 560K 56K 52K 34K 32K 20K 9K 2.5K 2.4K 220K 44K 30K 84K 78K 48K 45K 6K 6K 00K 35K 270K 82K 64K 00K 95K 2K 2K 56K 552K 480K 330K 300K 85K 70K 23K 22K 20K.4M M 884K 740K 500K 450K 65K 6K 0K 2.6M 2M.6M.3M 980K 820K 30K 23K 5K 4.4M 3M 2.8M 2M.7K.3M 245K 225K 2K 8M 5M 6M 4M 3.8K 2.7M 600K 536K K 2M 7M 8.8M 6M 6.3K 4.2M.0M 950K Notes: A = STD Mode Frequency. B = Low EMI Mode Frequency. Table 6. Typical Frequency vs. RC Values V CC = 25 C Load Capacitor Resistor (R) 33 pfd 56 pfd 00 pfd 0.00 µfd A(Hz) B(Hz) A(Hz) B(Hz) A(Hz) B(Hz) A(Hz) B(Hz).0M 8K 8K 2K 2K 7.4K 7.7K K K 560K 30K 30K 20K 20K 2K 2K.6K.6K 220K 70K 70K 47K 47K 30K 30K 4K 4K 00K 50K 48K 97K 96K 60K 60K 8K 8K 56K 268K 250K 76K 70K 00K 00K 5K 5K 20K 690M 600K 463K 46K 286K 266K 40K 40K 0K.2M M 860K 730K 540K 480K 80K 76K 5K 2M.7M.5M.2M 950K 820K 5K 38K 2K 4.6M 3M 3.3M 2.4M 2.2M.6M 360K 36K K 7M 4.6M 5M 3.6M 3.6K 2.6M 660K 565K Notes: A = STD Mode Frequency. B = Low EMI Mode Frequency. 30 P R E L I M I N A R Y DS97Z8X04

31 Zilog HALT Mode. This instruction turns off the internal CPU clock but not the crystal oscillation. The counter/timers and external interrupts IRQ0, IRQ, IRQ2 and IRQ3 remain active. The device is recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT Mode. After the interrupt service routine, the program continues from the instruction after the HALT. Note: On the C2 ICEBOX, the IRQ3 does not wake the device out of HALT Mode. STOP Mode. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 0 µa. The STOP Mode is released by a RESET through a Stop-Mode Recovery (pin P27). A Low input condition on P27 releases the STOP Mode. Program execution begins at location 000C(Hex). However, when P27 is used to release the STOP Mode, the I/O port Mode registers are not reconfigured to their default power-on conditions. This prevents any I/O, configured as output when the STOP instruction was executed, from glitching to an unknown state. To use the P27 release approach with STOP Mode, use the following instruction: LD NOP STOP P2M, #XXX XXXXB X = Dependent on user's application. Note: A low level detected on P27 pin will take the device out of STOP Mode even if configured as an output. In order to enter STOP or HALT Mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user executes a NOP (opcode=ffh) immediately before the appropriate SLEEP instruction, such as: FF NOP ; clear the pipeline 6F STOP ; enter STOP Mode or FF NOP ; clear the pipeline 7F HALT ; enter HALT Mode Z86E04/E08 Watch-Dog Timer (WDT). The Watch-Dog Timer is enabled by instruction WDT. When the WDT is enabled, it cannot be stopped by the instruction. With the WDT instruction, the WDT is refreshed when it is enabled within every Twdt period; otherwise, the controller resets itself, The WDT instruction affects the flags accordingly; Z=, S=0, V=0. WDT = 5F (Hex) Opcode WDT (5FH). The first time Opcode 5FH is executed, the WDT is enabled and subsequent execution clears the WDT counter. This must be done at least every T WDT ; otherwise, the WDT times out and generates a reset. The generated reset is the same as a power-on reset of T POR, plus 8 XTAL clock cycles. The software enabled WDT does not run in STOP Mode. Opcode WDH (4FH). When this instruction is executed it enables the WDT during HALT. If not, the WDT stops when entering HALT. This instruction does not clear the counters, it just makes it possible to have the WDT running during HALT Mode. A WDH instruction executed without executing WDT (5FH) has no effect. Permanent WDT. Selecting the hardware enabled Permanent WDT option, will automatically enable the WDT upon exiting reset. The permanent WDT will always run in HALT Mode and STOP Mode, and it cannot be disabled. Auto Reset Voltage (V LV ). The Z8 has an auto-reset builtin. The auto-reset circuit resets the Z8 when it detects the V CC below V LV. Figure 7 shows the Auto Reset Voltage versus temperature. If the V CC drops below the VCC operating voltage range, the Z8 will function down to the V LV unless the internal clock frequency is higher than the specified maximum V LV frequency. DS97Z8X04 P R E L I M I N A R Y 3

32 Z86E04/E08 Zilog FUNCTIONAL DESCRIPTION (Continued) Vcc (Volts) C 20 C 0 C 20 C 40 C 60 C 80 C 00 C Temp Figure 7. Typical Auto Reset Voltage (V LV ) vs. Temperature 32 P R E L I M I N A R Y DS97Z8X04

33 Zilog Low EMI Emission The Z8 can be programmed to operate in a low EMI Emission (Low Noise) Mode by means of an EPROM programmable bit option. Use of this feature results in: Less than ma consumed during HALT Mode. All drivers slew rates reduced to 0 ns (typical). Internal SCLK/TCLK = XTAL operation limited to a maximum of 4 MHz 250 ns cycle time. Output drivers have resistances of 500 ohms (typical). Oscillator divide-by-two circuitry eliminated. In addition to V DD and GND (V SS ), the Z8 changes all its pin functions in the EPROM Mode. XTAL2 has no function, XTAL functions as CE, P3 functions as OE, P32 functions as EPM, P33 functions as V PP, and P02 functions as PGM. Z86E04/E08 ROM Protect. ROM Protect fully protects the Z8 ROM code from being read externally. When ROM Protect is selected, the instructions LDC and LDCI are supported (Z86E04/E08 and Z86C04/C08 do not support the instructions of LDE and LDEI). When the device is programmed for ROM Protect, the Low Noise feature will not automatically be enabled. Please note that when using the device in a noisy environment, it is suggested that the voltages on the EPM and CE pins be clamped to V CC through a diode to V CC to prevent accidentally entering the OTP Mode. The V PP requires both a diode and a 00 pf capacitor. Auto Latch Disable. Auto Latch Disable option bit when programmed will globally disable all Auto Latches. WDT Enable. The WDT Enable option bit, when programmed, will have the hardware enabled Permanent WDT enabled after exiting reset and can not be stopped in Halt or Stop Mode. EPROM/Test Mode Disable. The EPROM/Test Mode Disable option bit, when programmed, will disable the EPROM Mode and the Factory Test Mode. Reading, verifying, and programming the Z8 will be disabled. To fully verify that this mode is disabled, the device must be power cycled. User Modes. Table 7 shows the programming voltage of each mode. Table 7. OTP Programming Table Programming Modes V PP EPM CE OE PGM ADDR DATA V CC * EPROM READ NU V H V IL V IL V IH ADDR Out 5.0V PROGRAM V H V IH V IL V IH V IL ADDR In 6.4V PROGRAM VERIFY V H V IH V IL V IL V IH ADDR Out 6.4V EPROM PROTECT V H V H V H V IH V IL NU NU 6.4V LOW NOISE SELECT V H V IH V H V IH V IL NU NU 6.4V AUTO LATCH DISABLE V H V IH V H V IL V IL NU NU 6.4V WDT ENABLE V H V IL V H V IH V IL NU NU 6.4V EPROM/TEST MODE V H V IL V H V IL V IL NU NU 6.4V Notes:. V H =2.75V ± 0.25 V DC. 2. V IH = As per specific Z8 DC specification. 3. V IL = As per specific Z8 DC specification. 4. X = Not used, but must be set to V H or V IH level. 5. NU = Not used, but must be set to either V IH or V IL level. 6. I PP during programming = 40 ma maximum. 7. I CC during programming, verify, or read = 40 ma maximum. 8. * V CC has a tolerance of ±0.25V. DS97Z8X04 P R E L I M I N A R Y 33

34 Z86E04/E08 Zilog FUNCTIONAL DESCRIPTION (Continued) Internal Address Counter. The address of Z8 is generated internally with a counter clocked through pin P0 (Clock). Each clock signal increases the address by one and the high level of pin P00 (Clear) will reset the address to zero. Figure 8 shows the setup time of the serial address input. Programming Waveform. Figures 9, 20, 2 and 22 show the programming waveforms of each mode. Table 8 shows the timing of programming waveforms. Programming Algorithm. Figure 23 shows the flow chart of the Z8 programming algorithm. Table 8. Timing of Programming Waveforms Parameters Name Min Max Units Address Setup Time 2 µs 2 Data Setup Time 2 µs 3 V PP Setup 2 µs 4 V CC Setup Time 2 µs 5 Chip Enable Setup Time 2 µs 6 Program Pulse Width 0.95 ms 7 Data Hold Time 2 µs 8 OE Setup Time 2 µs 9 Data Access Time 88 ns 0 Data Output Float Time 00 ns Overprogram Pulse Width 2.85 ms 2 EPM Setup Time 2 µs 3 PGM Setup Time 2 µs 4 Address to OE Setup Time 2 µs 5 Option Program Pulse Width 78 ms 6 OE Width 250 ns 7 Address Valid to OE Low 25 ns 34 P R E L I M I N A R Y DS97Z8X04

35 Zilog Z86E04/E08 P0 = Clock T2 T4 T3 T P00 = Clear Vpp/EPM T6 T5 Internal Address Vih 0 Min Data Vil Invalid Valid Invalid Valid 9 Legend: T Reset Clock Width T2 Input Clock High T3 Input Clock Period T4 Input Clock Low T5 Clock to Address Counter Out Delay T6 Epm/Vpp Set up Time 30 ns Min 00 ns Min 200 ns Min 00 ns Min 5 ns Max 40 µs Min Figure 8. Z86E04/E08 Address Counter Waveform DS97Z8X04 P R E L I M I N A R Y 35

36 Z86E04/E08 Zilog FUNCTIONAL DESCRIPTION (Continued) VIH Address VIL Address Stable Address Stable Data V PP VIH VIL VIH VIL 7 Invalid Valid Invalid Valid 9 EPM V CC CE VH VIL 5.0V VIH VIL 2 VIH 5 OE VIL VIH 6 6 PGM VIL 3 Figure 9. Z86E04/E08 Programming Waveform (EPROM Read) 36 P R E L I M I N A R Y DS97Z8X04

37 Zilog Z86E04/E08 Address VIH VIL Address Stable Data VIH VIL Data Stable Data Out Valid VPP EPM VH VIH VH VIL 3 VCC 6V 5.0V VIH 4 7 CE VIL OE VIH 5 VIL VIH 3 6 PGM VIL 6 8 Program Cycle Verify Cycle Figure 20. Z86E04/E08 Programming Waveform (Program and Verify) DS97Z8X04 P R E L I M I N A R Y 37

38 Z86E04/E08 Zilog FUNCTIONAL DESCRIPTION (Continued) V IH Address V IL V IH Data V IL V PP V H V IH V CC 6V 5.0V 3 4 CE V H V IH 5 OE V IH V IL V H EPM V IH V IH V IL V IH PGM V IL 5 EPROM Protect 5 Low Noise Program Figure 2. Z86E04/E08 Programming Options Waveform (EPROM Protect and Low Noise Program) 38 P R E L I M I N A R Y DS97Z8X04

39 Zilog Z86E04/E08 Address V IH V IL Data V IH V IL VPP V H V IH V CC 6V 5.0V 3 4 CE V H V IH 5 V IH OE V IL V IH EPM V IL V IH PGM V IL Auto Latch WDT EPROM/Test Mode Disabl e Figure 22. Z86E04/E08 Programming Options Waveform (Auto Latch Disable, Permanent WDT Enable and EPROM/Test Mode Disable) DS97Z8X04 P R E L I M I N A R Y 39

40 Z86E04/E08 Zilog FUNCTIONAL DESCRIPTION (Continued) Start Addr = First Location V CC = 6.4V V PP= 3.0V N = 0 Program ms Pulse Increment N N = 25? Yes No Fail Verify One Byte Verify Byte Fail Pass Pass Prog. One Pulse 3xN ms Duration Increment Address No Last Addr? Yes V CC = V PP = 5.0V Pass Verify All Bytes Fail Device Failed Device Passed Figure 23. Z86E04/E08 Programming Algorithm 40 P R E L I M I N A R Y DS97Z8X04

41 Zilog Z86E04/E08 Z8 CONTROL REGISTERS R24 TMR D7 D6 D5 D4 D3 D2 D D0 R244 T0 D7 D6 D5 D4 D3 D2 D D0 0 No Function Load T0 0 Disable T0 Count Enable T0 Count 0 No Function Load T 0 Disable T Count Enable T Count TIN Modes 00 External Clock Input 0 Gate Input 0 Trigger Input (Non-retriggerable) Trigger Input (Retriggerable) Reserved (Must be 0) R245 PRE0 Figure 27. Counter/Timer 0 Register (F4 H : Read/Write) D7 D6 D5 D4 D3 D2 D D0 T 0 Initial Value (When Written) (Range: -256 Decimal 0-00 HEX) T 0 Current Value (When READ) Figure 24. Timer Mode Register (F H : Read/Write) R242 T D7 D6 D5 D4 D3 D2 D D0 Count Mode 0 T0 Single Pass T0 Modulo N Reserved (Must be 0) Prescaler Modulo (Range: -64 Decimal 0-00 HEX) T Initial Value (When Written) (Range -256 Decimal 0-00 HEX) T Current Value (When READ) Figure 25. Counter Timer Register (F2 H : Read/Write) Figure 28. Prescaler 0 Register (F5 H : Write Only) R246 P2M D7 D6 D5 D4 D3 D2 D D0 P2 7 - P2 0 I/O Definition 0 Defines Bit as OUTPUT Defines Bit as INPUT R243 PRE D7 D6 D5 D4 D3 D2 D D0 Count Mode 0 = T Single Pass = T Modulo N Clock Source = T Internal 0 = T External Timing Input (T IN ) Mode Prescaler Modulo (Range: -64 Decimal 0-00 HEX) Figure 26. Prescaler Register (F3 H : Write Only) Figure 29. Port 2 Mode Register (F6 H : Write Only) R247 P3M D7 D6 D5 D4 D3 D2 D D0 0 Port 2 Open-Drain Port 2 Push-pull Port 3 Inputs 0 Digital Mode Analog Mode Reserved (Must be 0) Figure 30. Port 3 Mode Register (F7 H : Write Only) DS97Z8X04 P R E L I M I N A R Y 4

42 Z86E04/E08 Zilog Z8 CONTROL REGISTERS (Continued) R248 P0M D7 D6 D5 D4 D3 D2 D D0 R25 IMR D7 D6 D5 D4 D3 D2 D D0 R249 IPR P0 2 -P0 0 Mode 00 = Output 0 = Input Reserved (Must be.) Reserved (Must be 0.) Figure 3. Port 0 and Mode Register (F8 H : Write Only) R252 Flags Figure 34. Interrupt Mask Register (FB H : Read/Write) D7 D6 D5 D4 D3 D2 D D0 Enables IRQ0-IRQ5 (D 0 = IRQ0) Reserved (Must be 0.) Enables Interrupts D7 D6 D5 D4 D3 D2 D D0 Interrupt Group Priority Reserved = 000 C > A > B = 00 A > B > C = 00 A > C > B = 0 B > C > A = 00 C > B > A = 0 B > A > C = 0 Reserved = IRQ, IRQ4 Priority (Group C) 0 = IRQ > IRQ4 = IRQ4 > IRQ IRQ0, IRQ2 Priority (Group B) 0 = IRQ2 > IRQ0 = IRQ0 > IRQ2 IRQ3, IRQ5 Priority (Group A) 0 = IRQ5 > IRQ3 = IRQ3 > IRQ5 Reserved (Must be 0.) R253 RP Figure 35. Flag Register (FC H : Read/Write) D7 D6 D5 D4 D3 D2 D D0 User Flag F User Flag F2 Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag Figure 32. Interrupt Priority Register (F9 H : Write Only) Default After Reset = 00H Expanded Register File Working Register Pointer R250 IRQ D7 D6 D5 D4 D3 D2 D D0 Figure 36. Register Pointer (FD H : Read/Write) IRQ0 = P32 Input IRQ = P33 Input IRQ2 = P3 Input IRQ3 = P32 Input IRQ4 = T0 IRQ5 = T Reserved (Must be 0) Figure 33. Interrupt Request Register (FA H : Read/Write) R255 SPL D7 D6 D5 D4 D3 D2 D D0 Figure 37. Stack Pointer (FF H : Read/Write) Stack Pointer Lower Byte (SP 7 - SP 0 ) 42 P R E L I M I N A R Y DS97Z8X04

43 Zilog Z86E04/E08 PACKAGE INFORMATION 8-Pin DIP Package Diagram 8-Pin SOIC Package Diagram DS97Z8X04 P R E L I M I N A R Y 43

44 Z86E04/E08 Zilog ORDERING INFORMATION Z86E04 Standard Temperature 8-Pin DIP 8-Pin SOIC Z86E042PSC Z86E042SSC Z86E042PEC Z86E042SEC Z86E08 Standard Temperature 8-Pin DIP 8-Pin SOIC Z86E082PSC Z86E082SSC Z86E082PEC Z86E082SEC For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired. Codes Preferred Package P = Plastic DIP Longer Lead Time S = SOIC Speeds 2 =2 MHz Environmental C = Plastic Standard Preferred Temperature S = 0 C to +70 C E = 40 C to +05 C Example: Z 86E04 2 P S C is a Z86E04, 2 MHz, DIP, 0 C to +70 C, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix 998 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY, IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document. Zilog s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 20 East Hacienda Ave. Campbell, CA Telephone (408) FAX Internet: 44 P R E L I M I N A R Y DS97Z8X04