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1 .2W Audio Power Amplifier with Standby Mode Active High Operating from V CC = 2.5V to 5.5V Rail-to-rail output.2w output Vcc=5V, THD=%, F=kHz, with 8Ω load Ultra low consumption in standby mode (na) 75dB 27Hz from 2.5 to 5V Low pop & click Ultra low distortion (.5%) Unity gain stable Flip-chip package 8 x 3µm bumps Description The is an Audio Power Amplifier capable of delivering.6w of continuous RMS ouput power into a 4Ω 5V. This Audio Amplifier is exhibiting.% distortion level (THD) from a 5V supply for a Pout = 25mW RMS. An external standby mode control reduces the supply current to less than na. An internal shutdown protection is provided. The has been designed for high quality audio applications such as mobile phones and to minimize the number of external components. The unity-gain stable amplifier can be configured by external gain setting resistors. Applications Mobile phones (cellular / cordless) PDAs Laptop/notebook computers Portable audio devices Order Codes Pin Connections (top view) Audio Input Cin VCC TYPICAL APPLICATION SCHEMATIC Rin Rstb Cb JT - FLIP CHIP Vin- Vin+ Bypass Standby Vout Vout Part Number Temperature Range Package Packing Marking IJT EIJT ) Lead free Flip-Chip part number - + Cfeed Rfeed Bias Gnd VCC 6 2 VCC GND - AV = - + Stdby Bypass, +85 C Flip-Chip Tape & Reel 4972 Vin + Vin Vcc Vout Vout Cs RL 8 Ohms October 24 Revision 2 /3

2 Absolute Maximum Ratings Absolute Maximum Ratings Table : Key parameters and their absolute maximum ratings Symbol Parameter Value Unit VCC Supply voltage 6 V V i Input Voltage 2 G ND to V CC V T oper Operating Free Air Temperature Range to + 85 C T stg Storage Temperature -65 to +5 C T j Maximum Junction Temperature 5 C R thja Thermal Resistance Junction to Ambient 3 2 C/W Pd Power Dissipation Internally Limited 4 ESD Human Body Model 2 kv ESD Machine Model 2 V Latch-up Latch-up Immunity Class A Lead Temperature (soldering, sec) 25 C ) All voltages values are measured with respect to the ground pin. 2) The magnitude of input signal must never exceed V CC +.3V / G ND -.3V 3) Device is protected in case of over temperature by a thermal shutdown 5 C. 4) Exceeding the power derating curves during a long period, involves abnormal operating condition. Table 2: Operating Conditions Symbol Parameter Value Unit VCC Supply Voltage 2.5 to 5.5 V V ICM Common Mode Input Voltage Range G ND to V CC -.2V V VSTB Standby Voltage Input : Device ON G ND V STB.5V V Device OFF V CC -.5V V STB V CC RL Load Resistor 4-32 Ω R thja Thermal Resistance Junction to Ambient 9 C/W ) With Heat Sink Surface = 25mm 2 2/3

3 Electrical Characteristics 2 Electrical Characteristics Table 3: V CC = +5V, GND = V, T amb = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit I CC Supply Current No input signal, no load 6 8 ma I STANDBY Standby Current No input signal, Vstdby = Vcc, RL = 8Ω Voo Po THD + N PSRR Φ M GM GBP Output Offset Voltage No input signal, RL = 8Ω Output Power THD = % Max, f = khz, RL = 8Ω Total Harmonic Distortion + Noise Po = 25mW rms,, < f <, RL = 8Ω Power Supply Rejection Ratio 2 f = 27Hz, RL = 8Ω, RFeed = 22KΩ, Vripple = 2mV rms Phase Margin at Unity Gain R L = 8Ω, C L = 5pF Gain Margin R L = 8Ω, C L = 5pF Gain Bandwidth Product R L = 8Ω ) Standby mode is actived when Vstdby is tied to Vcc 2) Dynamic measurements - 2*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to f = 27Hz na 5 2 mv.2 W. % 75 db 7 Degrees 2 db 2 MHz 3/3

4 Electrical Characteristics Table 4: V CC = +3.3V, GND = V, T amb = 25 C (unless otherwise specified) 3) Symbol Parameter Min. Typ. Max. Unit I CC Supply Current No input signal, no load ma I STANDBY Standby Current No input signal, Vstdby = Vcc, RL = 8Ω Voo Po THD + N PSRR Φ M GM GBP Output Offset Voltage No input signal, RL = 8Ω Output Power THD = % Max, f = khz, RL = 8Ω Total Harmonic Distortion + Noise Po = 25mW rms,, < f <, RL = 8Ω Power Supply Rejection Ratio 2 f = 27Hz, RL = 8Ω, RFeed = 22KΩ, Vripple = 2mV rms Phase Margin at Unity Gain R L = 8Ω, C L = 5pF Gain Margin R L = 8Ω, C L = 5pF Gain Bandwidth Product R L = 8Ω ) Standby mode is actived when Vstdby is tied to Vcc 2) Dynamic measurements - 2*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to f = 27Hz 3. All electrical values are made by correlation between 2.6V and 5V measurements na 5 2 mv 5 mw. % 75 db 7 Degrees 2 db 2 MHz 4/3

5 Electrical Characteristics Table 5: V CC = 2.6V, GND = V, T amb = 25 C (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit I CC Supply Current No input signal, no load ma I STANDBY Standby Current No input signal, Vstdby = Vcc, RL = 8Ω Voo Po THD + N PSRR Φ M GM GBP Table 6: Components description Remarks: Output Offset Voltage No input signal, RL = 8Ω Output Power THD = % Max, f = khz, RL = 8Ω Total Harmonic Distortion + Noise Po = 2mW rms,, < f <, RL = 8Ω Power Supply Rejection Ratio 2 f = 27Hz, RL = 8Ω, RFeed = 22KΩ, Vripple = 2mV rms Phase Margin at Unity Gain R L = 8Ω, C L = 5pF Gain Margin R L = 8Ω, C L = 5pF Gain Bandwidth Product R L = 8Ω ) Standby mode is actived when Vstdby is tied to Vcc 2) Dynamic measurements - 2*log(rms(Vout)/rms(Vripple)). Vripple is an added sinus signal to f = 27Hz Components Rin Cin Rfeed Cs Cb Cfeed Rstb Gv Functional Description na 5 2 mv 3 mw. % 75 db 7 Degrees 2 db 2 MHz Inverting input resistor which sets the closed loop gain in conjunction with Rfeed. This resistor also forms a high pass filter with Cin (fc = / (2 x Pi x Rin x Cin)) Input coupling capacitor which blocks the DC voltage at the amplifier input terminal Feed back resistor which sets the closed loop gain in conjunction with Rin Supply Bypass capacitor which provides power supply filtering Bypass pin capacitor which provides half supply filtering Low pass filter capacitor allowing to cut the high frequency (low pass filter cut-off frequency / (2 x Pi x Rfeed x Cfeed)) Pull-up resistor which fixes the right supply level on the standby pin Closed loop gain in BTL configuration = 2 x (Rfeed / Rin). All measurements, except PSRR measurements, are made with a supply bypass capacitor Cs = µf. 2. External resistors are not needed for having better stability when Vcc down to 3V. By the way, the quiescent current remains the same. 3. The standby response time is about µs. 5/3

6 Electrical Characteristics Figure : Open Loop Frequency Response Figure 4: Open Loop Frequency Response Gain (db) Phase Gain Vcc = 5V RL = 8Ω.3 Frequency (khz) Figure 2: Open Loop Frequency Response Gain (db) Frequency (khz) Figure 3: Open Loop Frequency Response Gain (db) Phase Phase Gain Gain Vcc = 33V RL = 8Ω Vcc = 2.6V RL = 8Ω.3 Frequency (khz) Phase (Deg) Phase (Deg) Phase (Deg) Gain (db) Phase Gain Vcc = 5V ZL = 8Ω + 56pF.3 Frequency (khz) Figure 5: Open Loop Frequency Response Gain (db) Frequency (khz) Figure 6: Open Loop Frequency Response Gain (db) Phase Gain Vcc = 3.3V ZL = 8Ω + 56pF Vcc = 2.6V ZL = 8Ω + 56pF Phase Gain.3 Frequency (khz) Phase (Deg) Phase (Deg) Phase (Deg) 6/3

7 Electrical Characteristics Figure 7: Open Loop Frequency Response Figure : Power Supply Rejection Ratio (PSRR) vs Power supply Gain (db) Gain Vcc = 5V CL = 56pF Phase.3 Frequency (khz) Figure 8: Open Loop Frequency Response Gain (db) Gain Phase Vcc = 2.6V -2 CL = 56pF.3 Frequency (khz) Figure 9: Open Loop Frequency Response Gain (db) Gain Vcc = 3.3V CL = 56pF Phase.3 Frequency (khz) Phase (Deg) Phase (Deg) Phase (Deg) PSRR (db) Vripple = 2mVrms Rfeed = 22Ω Input = floating RL = 8Ω Vcc = 5V, 3.3V & 2.6V Cb = µf &.µf -8 Figure : Power Supply Rejection Ratio (PSRR) vs Bypass Capacitor PSRR (db) Cb=µF Cb=µF Vcc = 5, 3.3 & 2.6V Rfeed = 22k Cb=µF Rin = 22k, Cin = µf Rg = Ω, RL = 8Ω Cb=47µF -8 Figure 2: Power Supply Rejection Ratio (PSRR) vs Feedback Resistor Vcc = 5, 3.3 & 2.6V Cb = µf &.µf Vripple = 2mVrms Input = floating RL = 8Ω Rfeed=kΩ PSRR (db) Rfeed=47kΩ Rfeed=22kΩ -7 Rfeed=kΩ -8 7/3

8 Electrical Characteristics Figure 3: Power Supply Rejection Ratio (PSRR) vs Feedback Capacitor Figure 6: Power Dissipation vs Pout PSRR (db) Vcc = 5, 3.3 & 2.6V Cb = µf &.µf Rfeed = 22kΩ Vripple = 2mVrms Input = floating RL = 8Ω Cfeed= Cfeed=5pF Cfeed=33pF Power Dissipation (W) Vcc=5V F=kHz THD+N<% RL=4Ω RL=8Ω -7 Cfeed=68pF -8 Figure 4: Power Supply Rejection Ratio (PSRR) vs Input Capacitor PSRR (db) Cin=µF Cin=33nF Cin=nF Cin=22nF Cin=22nF Vcc = 5, 3.3 & 2.6V Rfeed = 22kΩ, Rin = 22k Cb = µf Rg = Ω, RL = 8Ω -6 Figure 5: THD + N = % vs Supply Voltage vs RL Output % THD + N (W) & Cb = µf F = khz BW < 25kHz 4 Ω 6 Ω 8 Ω 6 Ω 32 Ω Power Supply (V).2 RL=6Ω Figure 7: Power Dissipation vs Pout Power Dissipation (W) Vcc=2.6V F=kHz THD+N<% RL=6Ω RL=8Ω RL=4Ω Figure 8: THD + N = % vs Supply Voltage vs RL Output % THD + N (W) & Cb = µf F = khz BW < 25kHz 4 Ω 6 Ω 8 Ω 6 Ω 32 Ω Power Supply (V) 8/3

9 Electrical Characteristics Figure 9: Power Dissipation vs Pout Figure 22: THD + N vs Output Power Power Dissipation (W) Vcc=3.3V F=kHz THD+N<% RL=6Ω Figure 2: Power Derating Curves Flip-Chip Package Power Dissipation (W) No Heat sink RL=8Ω Figure 2: THD + N vs Output Power RL=4Ω Heat sink surface = 25mm 2 (See demoboard) RL = 4Ω Vcc = 5V Cb = Cin = µf BW < 25kHz Ambiant Temperature ( C) khz. RL = 4Ω, Vcc = 3.3V Cb = Cin = µf BW < 25kHz khz. E-3.. Figure 23: THD + N vs Output Power. RL = 4Ω, Vcc = 2.6V Cb = Cin = µf BW < 25kHz khz. E-3.. Figure 24: THD + N vs Output Power. RL = 4Ω, Vcc = 5V Gv = Cb = Cin = µf BW < 25kHz, khz. E-3... E-3.. 9/3

10 Electrical Characteristics Figure 25: THD + N vs Output Power Figure 28: THD + N vs Output Power. RL = 4Ω, Vcc = 3.3V Gv = Cb = Cin = µf BW < 25kHz. RL = 8Ω, Vcc = 3.3V Cb = Cin = µf BW < 25kHz khz. E-3.. Figure 26: THD + N vs Output Power. RL = 4Ω, Vcc = 2.6V Gv = Cb = Cin = µf BW < 25kHz khz. E-3.. Figure 27: THD + N vs Output Power. RL = 8Ω Vcc = 5V Cb = Cin = µf BW < 25kHz khz. E-3.. khz. E-3.. Figure 29: THD + N vs Output Power. RL = 8Ω, Vcc = 2.6V Cb = Cin = µf BW < 25kHz khz. E-3.. Figure 3: THD + N vs Output Power. RL = 8Ω Vcc = 5V Gv = Cb = Cin = µf BW < 25kHz khz. E-3.. /3

11 Electrical Characteristics Figure 3: THD + N vs Output Power Figure 34: THD + N vs Output Power. RL = 8Ω, Vcc = 3.3V Gv = Cb = Cin = µf BW < 25kHz. RL = 8Ω, Vcc = 3.3V Cb =.µf, Cin = µf BW < 25kHz khz. E-3.. Figure 32: THD + N vs Output Power. RL = 8Ω, Vcc = 2.6V Gv = Cb = Cin = µf BW < 25kHz khz. E-3.. Figure 33: THD + N vs Output Power. RL = 8Ω Vcc = 5V Cb =.µf, Cin = µf BW < 25kHz khz. E-3.. khz. E-3.. Figure 35: THD + N vs Output Power. RL = 8Ω, Vcc = 2.6V Cb =.µf, Cin = µf BW < 25kHz khz. E-3.. Figure 36: THD + N vs Output Power. RL = 8Ω, Vcc = 5V, Gv = Cb =.µf, Cin = µf BW < 25kHz, khz. E-3.. /3

12 Electrical Characteristics Figure 37: THD + N vs Output Power Figure 4: THD + N vs Output Power. RL = 8Ω, Vcc = 3.3V, Gv = Cb =.µf, Cin = µf BW < 25kHz,. RL = 6Ω, Vcc = 3.3V Cb = Cin = µf BW < 25kHz khz. E-3.. Figure 38: THD + N vs Output Power. RL = 8Ω, Vcc = 2.6V, Gv = Cb =.µf, Cin = µf BW < 25kHz, khz. E-3.. Figure 39: THD + N vs Output Power.. RL = 6Ω, Vcc = 5V Cb = Cin = µf BW < 25kHz khz E-3... khz E-3.. Figure 4: THD + N vs Output Power.. RL = 6Ω Vcc = 2.6V Cb = Cin = µf BW < 25kHz khz E-3.. Figure 42: THD + N vs Output Power. RL = 6Ω, Vcc = 5V Gv = Cb = Cin = µf BW < 25kHz khz. E-3.. 2/3

13 Electrical Characteristics Figure 43: THD + N vs Output Power Figure 46: THD + N vs Frequency. RL = 6Ω Vcc = 3.3V Gv = Cb = Cin = µf BW < 25kHz. RL = 4Ω, Vcc = 3.3V Cb = µf BW < 25kHz Pout = 56mW. khz E-3.. Figure 44: THD + N vs Output Power. RL = 6Ω Vcc = 2.6V Gv = Cb = Cin = µf BW < 25kHz khz. E-3.. Figure 45: THD + N vs Frequency. RL = 4Ω, Vcc = 5V Cb = µf BW < 25kHz Pout =.3W Pout = 65mW. 2 Pout = 28mW. 2 Figure 47: THD + N vs Frequency. RL = 4Ω, Vcc = 2.6V Cb = µf BW < 25kHz Pout = 24 & 2mW. 2 Figure 48: THD + N vs Frequency Pout =.3W. Pout = 65mW RL = 4Ω, Vcc = 5V Gv = Cb = µf BW < 25kHz. 2 3/3

14 Electrical Characteristics Figure 49: THD + N vs Frequency Figure 52: THD + N vs Frequency. Pout = 56mW RL = 4Ω, Vcc = 3.3V Gv = Cb = µf BW < 25kHz. Cb =.µf RL = 8Ω, Vcc = 5V Gv = Pout = 92mW BW < 25kHz Pout = 28mW Cb = µf. 2 Figure 5: THD + N vs Frequency. Pout = 24 & 2mW RL = 4Ω, Vcc = 2.6V Gv = Cb = µf BW < 25kHz. 2 Figure 5: THD + N vs Frequency. Cb =.µf RL = 8Ω Vcc = 5V Pout = 92mW BW < 25kHz Cb = µf Figure 53: THD + N vs Frequency. Cb =.µf Cb = µf. 2 Figure 54: THD + N vs Frequency. Cb =.µf RL = 8Ω, Vcc = 3.3V Pout = 42mW BW < 25kHz RL = 8Ω Vcc = 5V Pout = 46mW BW < 25kHz Cb = µf. 2 4/3

15 Electrical Characteristics Figure 55: THD + N vs Frequency Figure 58: THD + N vs Frequency. Cb =.µf RL = 8Ω, Vcc = 5V Gv = Pout = 46mW BW < 25kHz. Cb =.µf RL = 8Ω, Vcc = 2.6V Pout = 22mW BW < 25kHz Cb = µf. 2 Figure 56: THD + N vs Frequency. Cb =.µf Cb = µf. 2 Figure 57: THD + N vs Frequency. Cb = µf Cb =.µf RL = 8Ω, Vcc = 3.3V Pout = 2mW BW < 25kHz RL = 8Ω, Vcc = 3.3V Gv = Pout = 42mW BW < 25kHz Cb = µf. 2 Figure 59: THD + N vs Frequency. Cb = µf Cb =.µf. 2 Figure 6: THD + N vs Frequency. Cb = µf Cb =.µf RL = 8Ω, Vcc = 2.6V Gv = Pout = 22mW BW < 25kHz RL = 8Ω, Vcc = 3.3V Gv = Pout = 2mW BW < 25kHz /3

16 Electrical Characteristics Figure 6: THD + N vs Frequency Figure 64: THD + N vs Frequency.. Cb =.µf RL = 8Ω, Vcc = 2.6V Gv = Pout = mw BW < 25kHz. Pout = 4mW Cb = µf. 2 Figure 62: THD + N vs Frequency. Cb =.µf Cb = µf. 2 Figure 63: THD + N vs Frequency.. Pout = 35mW RL = 8Ω, Vcc = 2.6V Gv = Pout = mw BW < 25kHz Pout = 63mW RL = 6Ω, Vcc = 5V, Cb = µf BW < 25kHz E-3 2 Pout = 28mW RL = 6Ω, Vcc = 3.3V, Cb = µf BW < 25kHz E-3 2 Figure 65: THD + N vs Frequency.. Pout = 8mW Pout = 6mW RL = 6Ω, Vcc = 2.6V, Cb = µf BW < 25kHz E-3 2 Figure 66: THD + N vs Frequency. RL = 6Ω, Vcc = 5V Gv =, Cb = µf BW < 25kHz Pout = 35mW Pout = 63mW. 2 6/3

17 Electrical Characteristics Figure 67: THD + N vs Frequency Figure 7: Signal to Noise Ratio vs Power Supply with Weighted Filter Type A. RL = 6Ω, Vcc = 3.3V Gv =, Cb = µf BW < 25kHz Pout = 4mW Pout = 28mW. 2 Figure 68: THD + N vs Frequency. RL = 6Ω, Vcc = 2.6V Gv =, Cb = µf BW < 25kHz Pout = 6mW Pout = 8mW. 2 Figure 69: Signal to Noise Ratio vs Power Supply with Unweighted Filter ( to ) SNR (db) RL=6Ω RL=8Ω RL=4Ω SNR (db) 9 8 RL=6Ω RL=8Ω RL=4Ω 7 Cb = Cin = µf THD+N <.4% Vcc (V) Figure 7: Frequency Response Gain vs Cin, & Cfeed Gain (db) Cin = 47nF Cin = 22nF Cfeed = 33pF Cfeed = 68pF Cfeed = 2.2nF -2 Cin = 82nF Rin = Rfeed = 22kΩ -25 Figure 72: Signal to Noise Ratio vs Power Supply with Unweighted Filter ( to ) 9 SNR (db) 8 7 RL=6Ω RL=4Ω RL=8Ω 6 Cb = Cin = µf THD+N <.4% Vcc (V) 6 Gv = Cb = Cin = µf THD+N <.7% Vcc (V) 7/3

18 Electrical Characteristics Figure 73: Signal to Noise Ratio vs Power Supply with Weighted Filter Type A Figure 76: Current Consumption vs Standby Vcc = 2.6V 6 5 Vcc = 2.6V 9 4 SNR (db) 8 RL=6Ω RL=4Ω RL=8Ω Icc (ma) 3 7 Gv = Cb = Cin = µf THD+N <.7% Vcc (V) Figure 74: Current Consumption vs Power Supply Voltage Icc (ma) Vstandby = V Vcc (V) Figure 75: Current Consumption vs Standby Vcc = 5V Icc (ma) Vcc = 5V Vstandby (V) Figure 77: Clipping Voltage vs Power Supply Voltage and Load Resistor Vout & Vout2 Clipping Voltage Low side (V) RL = 4Ω RL = 8Ω. RL = 6Ω Power supply Voltage (V) Figure 78: Current Consumption vs Standby Vcc = 3.3V Vcc = 3.3V Icc (ma) Vstandby (V) Vstandby (V) 8/3

19 Electrical Characteristics Figure 79: Clipping Voltage vs Power Supply Voltage and Load Resistor Vout & Vout2 Clipping Voltage High side (V) RL = 4Ω RL = 8Ω. RL = 6Ω Power supply Voltage (V) 9/3

20 Application Information 3 Application Information Figure 8: Demoboard Schematic S VCC VCC Vcc S2 C GND GND R2 R C2 VCC P Neg. Input + C6 µ C7 n P2 Pos. Input C3 R3 C5 R4 C4 R5 S5 R6 Positive Input mode VCC R7 k S8 R8 k Standby Figure 8: Flip-Chip 3µm Demoboard Components Side C + C2 + u C8 n Vin- Vin+ Bypass Standby Bias 2 U S6 VC OUT C C9 S3 Vout 8 + G ND - AV = - + Vout µ + C 47µ S4 GND S7 GND OUT2 2/3

21 Application Information Figure 82: Flip-Chip 3µm Demoboard Top Solder Layer The output power is: 2 (2 Vout RMS ) Pout = (W) RL Figure 83: Flip-Chip 3µm Demoboard Bottom Solder Layer BTL Configuration Principle The is a monolithic power amplifier with a BTL output type. BTL (Bridge Tied Load) means that each end of the load is connected to two single ended output amplifiers. Thus, we have : Single ended output = Vout = Vout (V) Single ended output 2 = Vout2 = -Vout (V) And Vout - Vout2 = 2Vout (V) For the same power supply voltage, the output power in BTL configuration is four times higher than the output power in single ended configuration. Gain In Typical Application Schematic (cf. page ) In flat region (no effect of Cin), the output voltage of the first stage is: Rfeed Vout = Vin (V) Rin For the second stage : Vout2 = -Vout (V) The differential output voltage is: Vout2 Rfeed Vout = 2Vin (V) Rin The differential gain named gain (Gv) for more convenient usage is: Gv = Vout Vout = 2 Rfeed Vin Rin Remark : Vout2 is in phase with Vin and Vout is 8 phased with Vin. It means that the positive terminal of the loudspeaker should be connected to Vout2 and the negative to Vout. Low and high frequency response In low frequency region, the effect of Cin starts. Cin with Rin forms a high pass filter with a -3dB cut off frequency. FCL = ( Hz) 2π Rin Cin In high frequency region, you can limit the bandwidth by adding a capacitor (Cfeed) in parallel on Rfeed. Its form a low pass filter with a -3dB cut off frequency. FCH = ( Hz) 2π Rfeed Cfeed Power dissipation and efficiency Hypothesis : Voltage and current in the load are sinusoidal (Vout and Iout) Supply voltage is a pure DC source (Vcc) 2/3

22 Application Information Regarding the load we have: and and Then, the average current delivered by the supply voltage is: The power delivered by the supply voltage is Psupply = Vcc Icc AVG (W) Then, the power dissipated by the amplifier is Pdiss = Psupply - Pout (W) and the maximum value is obtained when: and its value is: VOUT = V PEAK sinωt (V) IOUT = VOUT (A) R L POUT = VPEAK (W) 2RL ICC AVG = 2 VPEAK (A) πrl Pdiss = Vcc P OUT POUT (W) π RL Pdiss = POUT 2Vcc Pdiss max = 2 π R (W) Remark : This maximum value is only depending on power supply voltage and load values. The efficiency is the ratio between the output power and the power supply η = POUT The maximum theoretical value is reached when Vpeak = Vcc, so Decoupling of the circuit Two capacitors are needed to bypass properly the, a power supply bypass capacitor Cs and a bias voltage bypass capacitor Cb. L = πvpeak Psupply 4VCC 2 Cs has especially an influence on the THD+N in high frequency (above 7kHz) and indirectly on the power supply disturbances. With µf, you can expect similar THD+N performances like shown in the datasheet. If Cs is lower than µf, in high frequency increases, THD+N and disturbances on the power supply rail are less filtered. To the contrary, if Cs is higher than µf, those disturbances on the power supply rail are more filtered. Cb has an influence on THD+N in lower frequency, but its function is critical on the final result of PSRR with input grounded in lower frequency. If Cb is lower than µf, THD+N increase in lower frequency (see THD+N vs frequency curves) and the PSRR worsens up If Cb is higher than µf, the benefit on THD+N in lower frequency is small but the benefit on PSRR is substantial (see PSRR vs. Cb curve : fig.2). Note that Cin has a non-negligible effect on PSRR in lower frequency. Lower is its value, higher is the PSRR (see fig. 3). Pop and Click performance Pop and Click performance is intimately linked with the size of the input capacitor Cin and the bias voltage bypass capacitor Cb. Size of Cin is due to the lower cut-off frequency and PSRR value requested. Size of Cb is due to THD+N and PSRR requested always in lower frequency. Moreover, Cb determines the speed that the amplifier turns ON. The slower the speed is, the softer the turn ON noise is. The charge time of Cb is directly proportional to the internal generator resistance 5kΩ. Then, the charge time constant for Cb is τb = 5kΩxCb (s) As Cb is directly connected to the non-inverting input (pin 2 & 3) and if we want to minimize, in amplitude and duration, the output spike on Vout (pin 5), Cin must be charged faster than Cb. The charge time constant of Cin is τin = (Rin+Rfeed)xCin (s) π ---- = 78.5% 4 22/3

23 Application Information Thus we have the relation τin << τb (s) The respect of this relation permits to minimize the pop and click noise. Remark : Minimize Cin and Cb has a benefit on pop and click phenomena but also on cost and size of the application. Example : your target for the -3dB cut off frequency is Hz. With Rin=Rfeed=22 kω, Cin=72nF (in fact 82nF or nf). With Cb=µF, if you choose the one of the latest two values of Cin, the pop and click phenomena at power supply ON or standby function ON/OFF will be very small 5 kωxµf >> 44kΩxnF (5ms >> 4.4ms). Increasing Cin value increases the pop and click phenomena to an unpleasant sound at power supply ON and standby function ON/OFF. Why Cs is not important in pop and click consideration? Hypothesis : Cs = µf Supply voltage = 5V Supply voltage internal resistor =.Ω Supply current of the amplifier Icc = 6mA At power ON of the supply, the supply capacitor is charged through the internal power supply resistor. So, to reach 5V you need about five to ten times the charging time constant of Cs (τs =.xcs (s)). Then, this time equal 5µs to µs << τb in the majority of application. At power OFF of the supply, Cs is discharged by a constant current Icc. The discharge time from 5V to V of Cs is: tdischcs = Cs = 83 ms Icc Now, we must consider the discharge time of Cb. At power OFF or standby ON, Cb is discharged by a kω resistor. So the discharge time is about τb Disch 3xCbxkΩ (s). In the majority of application, Cb=µF, then τb Disch 3ms >> t dischcs. Power amplifier design examples Given : Load impedance : 8Ω Output % THD+N :.5W Input impedance : kω min. Input voltage peak to peak : Vpp Bandwidth frequency : to (, - 3dB) Ambient temperature max = 5 C SO8 package First of all, we must calculate the minimum power supply voltage to obtain.5w into 8Ω. With curves in fig. 5, we can read 3.5V. Thus, the power supply voltage value min. will be 3.5V. Following the maximum power dissipation equation 2 2 Vcc Pdissmax = (W) 2 π RL with 3.5V we have Pdissmax=.3W. Refer to power derating curves (fig. 2), with.3w the maximum ambient temperature will be C. This last value could be higher if you follow the example layout shown on the demoboard (better dissipation). The gain of the amplifier in flat region will be: GV = VOUTPP 2 2RL POUT = = 5.65 VINPP VINPP We have Rin > kω. Let's take Rin = kω, then Rfeed = 28.25kΩ. We could use for Rfeed = 3kΩ in normalized value and the gain will be Gv = 6. In lower frequency we want 2 Hz (-3dB cut off frequency). Then: CIN = = 795nF 2π RinFCL So, we could use for Cin a µf capacitor value which gives 6Hz. In Higher frequency we want (-3dB cut off frequency). The Gain Bandwidth Product of the is 2MHz typical and doesn't change when the amplifier delivers power into the load. The first amplifier has a gain of: Rfeed = 3 Rin 23/3

24 Application Information and the theoretical value of the -3dB cut-off higher frequency is 2MHz/3 = 66kHz. We can keep this value or limit the bandwidth by adding a capacitor Cfeed, in parallel on Rfeed. Then: So, we could use for Cfeed a 22pF capacitor value that gives 24kHz. Now, we can calculate the value of Cb with the formula τb = 5kΩxCb >> τin = (Rin+Rfeed)xCin which permits to reduce the pop and click effects. Then Cb >>.8µF. We can choose for Cb a normalized value of 2.2µF that gives good results in THD+N and PSRR. In the following tables, you could find three another examples with values required for the demoboard. Application n : to bandwidth and 6dB gain BTL power amplifier Components: Designator R 22k /.25W R4 22k /.25W R6 Short Cicuit Part Type R7 k /.25W R8 C5 Short Circuit 47nF C6 µf C7 C9 C CFEED = nf C2 µf = 265pF 2π RFEEDFCH Short Circuit Short Circuit S, S2, S6, S7 2mm insulated Plug.6mm pitch Application n 2 : to bandwidth and 2dB gain BTL power amplifier Components: Designator Part Type R k /.25W R4 22k /.25W R6 Short Cicuit R7 k /.25W R8 C5 Short Cicuit 47nF C6 µf C7 C9 C nf C2 µf Short Circuit Short Circuit S, S2, S6, S7 2mm insulated Plug.6mm pitch S8 P 3 pts connector 2.54mm pitch Application n 3 : 5Hz to khz bandwidth and db gain BTL power amplifier Components: Designator SMB Plug R 33k /.25W R2 Short Circuit R4 22k /.25W R6 Short Cicuit Part Type R7 k /.25W R8 C2 C5 Short Cicuit 47pF 5nF S8 P 3 pts connector 2.54mm pitch SMB Plug C6 µf C7 nf C9 Short Circuit 24/3

25 Application Information C C2 µf Short Circuit S, S2, S6, S7 2mm insulated Plug.6mm pitch S8 Designator Part Type 3 pts connector 2.54mm pitch For Vcc=5V, a to bandwidth and 2dB gain BTL power amplifier you could follow the bill of material below. Components: Designator Part Type R k /.25W R4 22k /.25W P SMB Plug Application n 4 : Differential inputs BTL power amplifier In this configuration, we need to place these components : R, R4, R5, R6, R7, C4, C5, C2. We have also : R4 = R5, R = R6, C4 = C5. The differential gain of the amplifier is: G VDIFF = 2 R R4 Note : Due to the VICM range (see Operating Condition), GVDIFF must have a minimum value shown in figure 84. Figure 84: Minimum Differential Gain vs Power Supply Voltage Differential Gain min. (db) Power Supply Voltage (V) R5 22k /.25W R6 k /.25W R7 k /.25W R8 C4 C5 Short circuit 47nF 47nF C6 µf C7 C9 C nf C2 µf Short Circuit Short Circuit S, S2, S6, S7 2mm insulated Plug.6mm pitch S8 P, P2 SMB Plug 3 pts connector 2.54mm pitch 25/3

26 Application Information Note on how to use the PSRR curves (page 7) We have finished a design and we have chosen the components values : Rin=Rfeed=22kΩ Cin=nF Cb=µF Now, on fig. 3, we can see the PSRR (input grounded) vs frequency curves. At 27Hz we have a PSRR value of -36dB. In reality we want a value about -7dB. So, we need a gain of 34dB! Now, on fig. 2 we can see the effect of Cb on the PSRR (input grounded) vs. frequency. With Cb=µF, we can reach the -7dB value. The process to obtain the final curve (Cb=µF, Cin=nF, Rin=Rfeed=22kΩ) is a simple transfer point by point on each frequency of the curve on fig. 3 to the curve on fig. 2. The measurement result is shown on the next figure. Figure 85: PSRR changes with Cb PSRR (db) Cin=nF Cb=µF Cin=nF Cb=µF Vcc = 5, 3.3 & 2.6V Rfeed = 22k, Rin = 22k Rg = Ω, RL = 8Ω Note on PSRR measurement What is the PSRR? The PSRR is the Power Supply Rejection Ratio. It's a kind of SVR in a determined frequency range. The PSRR of a device, is the ratio between a power supply disturbance and the result on the output. We can say that the PSRR is the ability of a device to minimize the impact of power supply disturbances to the output. How we measure the PSRR? Figure 86: PSRR measurement schematic Vripple Vcc Cin Rg Ohms Rin Cb Vs- Vin- Vin+ Bypass Standby Rfeed Bias Principle of operation VCC GND 2 AV = - Vout Vout 2 We fixed the DC voltage supply (Vcc) We fixed the AC sinusoidal ripple voltage (Vripple) No bypass capacitor Cs is used The PSRR value for each frequency is: Remark : The measure of the Rms voltage is not a Rms selective measure but a full range (2 Hz to 25 khz) Rms measure. It means that we measure the effective Rms signal + the noise PSRR( db) = 2 x Log Rms( Vripple) Rms( Vs + - Vs-) RL Vs+ 26/3

27 Mechanical Data 4 Mechanical Data Figure 87: Footprint Recommendation (Non Solder Mask Defined) Φ=25µm 5µm 5µm 75µm min. µm max. Track 5µm Φ=4µm 5µm min. Figure 88: Top View Of The Daisy Chain Mechanical Data ( all drawings dimensions are in millimeters Remarks: 5µm Daisy chain sample is featuring pins connection two by two. The schematic above is illustrating the way connecting pins each other. This sample is used for testing continuity on board. PCB needs to be designed on the opposite way, where pin connections are not done on daisy chain samples. By that way, just connecting an Ohmeter between pin 8 and pin, the soldering process continuity can be tested. Order Codes Solder mask opening 8 7 Vin+ Vout Pad in Cu 35µm with Flash NiAu (6µm,.5µm) 6 Vcc 2 5 Stdby Vout2 Vin Gnd Bypass 2.26 mm mm Package Part Number Temperature Range Marking J TSDC3IJT, +85 C DC3 27/3

28 Mechanical Data Figure 89: Tape & reel specification (top view) A A m µ 7 + Y e s iz ie D Die size X + 7µm 4 All dimensions are in mm User direction of feed 28/3

29 Package Mechanical Data 5 Package Mechanical Data 5. Flip-Chip - 8 BUMPS Figure 9: Pin Out (top view) Balls are underneath.5.5 4µm 25µm Die size : (2.26mm ±%) x (.6mm ±%) Die height (including bumps) : 65µm ± 5 Bumps diameter : 35µm ±5µm Silicon thickness : 4µm ±25µm Pitch: 5µm ±µm 65µm Figure 9: Marking (top view) A72 YWW E 29/3

30 Package Mechanical Data Revision History Date Revision Description of Changes January 23 First Release October 24 2 Update Mechanical Data for Flip-Chip package Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 24 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Repubic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 3/3