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1 OPERATING FROM V CC = 3. V to 5. V SPEAKER: Mono, khz is % W into 8 Ω BTL HEADSET: Stereo, khz is.5% 85 mw into 32 Ω BTL VOLUME CONTROL: 32-step digital volume control OUTPUT MODE: Eight different selections Ultra low pop-and-click Low Shutdown Current (. µa, typ.) Thermal Shutdown Protection FLIP-CHIP Package 8 X 3 µm Bumps E IJT Lead-Free option available DESCRIPTION The is a complete low power audio amplifier solution targeted at mobile phones. It integrates, into an extremely compact flip-chip package, an audio amplifier, a speaker driver, and a headset driver. The Audio Power Amplifier can deliver. W (typ.) of continuous RMS output power into an 8 Ω speaker with a % THD+N value. To the headset driver, the amplifier can deliver 85 mw (typ.) per channel of continuous average power into stereo 32 Ω bridged-tied load with.5% 5 V. This device features a 32-step digital volume control and 8 different output selections. The digital volume and output modes are controlled through a three-digit SPI interface bus. APPLICATIONS Mobile Phones ORDER CODE Temperature Package Part Number Range J IJT -4, +85 C EIJT -4, +85 C PIN CONNECTIONS (top view) IJT - Flip Chip Pin Out (top view) LOUDSPEAKER & HEADSET DRIVER WITH VOLUME CONTROL J = Flip Chip Package - only available in Tape & Reel (JT)) March 24 /27

2 Application Information for a Typical Application APPLICATION INFORMATION FOR A TYPICAL APPLICATION External component descriptions Component Functional Description C in This is the input coupling capacitor. It blocks the DC voltage at, and couples the input signal to the amplifier s input terminals. Cin also creates a highpass filter with the internal input impedance Zin at Fc = / (2π x Zin x Cin). C s C B This is the Supply Bypass capacitor. It provides power supply filtering. This is the Bypass pin capacitor. It provides half-supply filtering. 2/27

3 SPI Bus Interface 2 SPI BUS INTERFACE 2. Pin Descriptions Pin DATA CLK ENB Functional Description This is the serial data input pin This is the clock input pin This is the SPI enable pin active at high level 2.2 SPI Operation Description The serial data bits are organized into a field containing 8 bits of data as shown in Table. The DATA to DATA 2 bits determine the output mode of the as shown in Table 2. The DATA 3 to DATA 7 bits determine the gain level setting as illustrated by Table 3. For each SPI transfer, the data bits are written to the DATA pin with the least significant bit (LSB) first. All serial data are sampled at the rising edge of the CLK signal. Once all the data bits have been sampled, ENB transitions from logic-high to logic low to complete the SPI sequence. All 8 bits must be received before any data latch can occur. Any excess CLK and DATA transitions will be ignored after the height rising clock edge has occurred. For any data sequence longer than 8 bits, only the Output Mode # Table 2: Output Mode Selection first 8 bits will get loaded into the shift register and the rest of the bits will be disregarded. Table : Bit Allocation DATA MODES LSB DATA Mode DATA Mode 2 DATA 2 Mode 3 DATA 3 gain DATA 4 gain 2 DATA 5 gain 3 DATA 6 gain 4 MSB DATA 7 gain 5 DATA 2 DATA DATA SPKR out R out L out SD SD SD +2dBxP IHF SD SD 2 MUTE GxP HS GxP HS 3 +2dBxP IHF GxP HS GxP HS 4 MUTE G2xR in G2xL in 5 +2dBxP IHF G2xR in G2xL in 6 MUTE GxP HS + G2xR in GxP HS + G2xL in 7 +2dBxP IHF GxP HS + G2xR in GxP HS + G2xL in (SD = Shut Down Mode, P HS = Non Filtered Phone In HS, P IHF = External High Pass Filtered Phone In IHF) 3/27

4 SPI Bus Interface Table 3: Gain Control Settings G2: Gain (db) G: Gain (db) DATA 7 DATA 6 DATA 5 DATA 4 DATA /27

5 Absolute Maximum Ratings 2.3 SPI Timing Diagram 3 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V CC Supply voltage 6 V T oper Operating Free Air Temperature Range -4 to + 85 C T stg Storage Temperature -65 to +5 C T j Maximum Junction Temperature 5 C R thja Flip Chip Thermal Resistance Junction to Ambient 2 66 C/W Pd Power Dissipation Internally Limited ESD Human Body Model 3 2 kv ESD Machine Model 4 V Latch-up Immunity 2 ma Lead Temperature (soldering, sec) 25 C ) All voltage values are measured with respect to the ground pin. 2) Device is protected in case of over temperature by a thermal shutdown 5 C typ. 3) Human body model, pf discharged through a.5kω resistor into pin of device. 4) This is a minimum Value. Machine model ESD, a 2pF cap is charged to the specified voltage, then discharged directly into the IC with no external series resistor (internal resistor < 5Ω), into pin to pin of device. 5.) All PSRR data limits are guaranteed by evaluation tests. 4 OPERATING CONDITIONS Symbol Parameter Value Unit V CC Supply Voltage 3 to 5 V V phin Maximum Phone In Input Voltage G ND to V CC V V Rin/ V Lin Maximum Rin & Lin Input Voltage G ND to V CC V T SD Thermal Shutdown Temperature 5 C 5/27

6 Electrical Characteristics 5 ELECTRICAL CHARACTERISTICS Table 4: Electrical characteristics at VCC = +5. V, GND = V, (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit I CC I STANDBY Voo Supply Current, all max settings Output Mode, Vin = V, no load Output Mode, Vin = V, loaded (8Ω) Output Mode 2,3,4,5,6,7 Vin = V, no loads Output mode 2,3,4,5,6,7 Vin = V, loaded (8Ω, 32Ω) Standby Current Output Mode.75 2 Output Offset Voltage (differential) Output Mode to 7, Vin = V, no load, Speaker Out Output Mode 2 to 7 Vin = V, no loads, Headset Out Vil Logic low input Voltage.4 V Vih Logic high input Voltage.4 5 V Po Output Power mw SPKR out, RL = 8Ω, THD+N = %, f = khz R out & L out,, THD+N =.5%, f = khz 8 7 THD + N Total Harmonic Distortion + Noise R out & L out, Po = 7 mw, f = khz, SPKR out, Po = 8 mw, f = khz, RL = 8Ω R out & L out, Po=5mW, 2Hz<f< 2kHz, RL=32Ω SPKR out, Po = 4 mw, 2 Hz < f < 2 khz, RL = 8Ω SNR PSRR 5) Signal To Noise Ratio A-Weighted, f = khz Power Supply Rejection Ratio SPKR out ;Vripple = 2 mv Vpp, F = 27 Hz, Input Terminated 5Ω Gain (BTL) = 2 db, Output mode,3,5,7 R out & L out ;Vripple = 2 mv Vpp, F = 27 Hz, Input Terminated 5Ω Maximum gain setting, Output mode 2,3 R out & L out ;Vripple = 2 mv Vpp, F = 27 Hz, Input Terminated 5Ω Maximum gain setting, Output mode 4,5 R out & L out ;Vripple = 2 mv Vpp, F = 27 Hz, Input Terminated 5Ω Maximum gain setting, Output mode 6, ma µa mv % 8 db G2 Digital Gain Range (Rin & Lin) to R out, L out db G Digital Gain Range (Phone In HS) to R out, L out db Digital Gain Stepsize.5 db Stepsize Error ±.6 db db 6/27

7 Electrical Characteristics Table 4: Electrical characteristics at VCC = +5. V, GND = V, (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit Phone In Volume BTL maximum GAIN from Phone In HS to R out, L out BTL minimum GAIN from Phone In HS to R out, L out db Phone In Volume BTL maximum gain from Rin, Lin to R out, L out BTL minimum gain from Rin, Lin to R out, L out Phone In Volume db BTL gain from Phone In IHF to SPKR out Zin Phone In IHF Input Impedance kω Zin Phone In HS, Rin & Lin Input Impedance, All Gain setting kω tes Enable Step up Time - ENB 2 ns teh Enable Hold Time - ENB 2 ns tel Enable Low Time - ENB 3 ns tds Data Setup Time- DATA 2 ns tdh Data Hold Time - DATA 2 ns tcs Clock Setup time - CLK 2 ns tch Clock Logic High Time - CLK 5 ns tcl Clock Logic Low Time - CLK 5 ns fclk Clock Frequency - CLK DC MHz Table 5: Electrical characteristics at VCC = +3. V, GND = V, (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit I CC Supply Current, all max settings Output Mode, Vin = V, no load Output Mode, Vin = V, loaded (8Ω) Output Mode 2,3,4,5,6,7 Vin = V, no loads Output mode 2,3,4,5,6,7 Vin = V, loaded (8Ω, 32Ω) I STANDBY Voo Standby Current Output Mode.6 2 Output Offset Voltage (differential) Output Mode to 7, Vin = V, no load, Speaker Out Output Mode 2 to 7 Vin = V, no loads, Headset Out Vil Logic low input Voltage.4 V Vih Logic high input Voltage.4 3 V db ma µa mv 7/27

8 Electrical Characteristics Table 5: Electrical characteristics at VCC = +3. V, GND = V, (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit Po Output Power SPKR out, RL = 8Ω, THD = %, f = khz R out & L out,, THD =.5%, f = khz mw THD + N Total Harmonic Distortion + Noise R out & L out, Po=2mW, f=khz, RL=32Ω SPKR out, Po = 3 mw, f = khz, RL = 8Ω R out & L out, Po = 5 mw, 2 Hz < f < 2 khz, SPKR out, Po = 25 mw, 2 Hz < f < 2 khz, RL = 8Ω SNR PSRR 5) Signal To Noise Ratio A-Weighted, f = khz Power Supply Rejection Ratio SPKR out,vripple = 2 mv Vpp, F = 27 Hz, Input Terminated 5Ω Gain (BTL) = 2 db, Output Mode,3,5,7 R out & L out Vripple = 2 mv Vpp, F = 27 Hz, Input Terminated 5Ω Maximum gain setting, Output Mode 2,3 R out & L out Vripple = 2 mv Vpp, F = 27 Hz, Input Terminated 5Ω Maximum gain setting, Output Mode 4,5 R out & L out Vripple = 2 mv Vpp, F = 27 Hz, Input Terminated 5Ω Maximum gain setting, Output Mode 6, % 8 db G2 Digital Gain Range - Rin & Lin to R out, L out db G Digital Gain Range - Phone In HS to R out, L out db Digital Gain stepsize.5 db Stepsize Error ±.6 db Phone In Volume db BTL maximum GAIN from Phone In HS to R out, L out BTL minimum GAIN from Phone In HS to R out, L out Phone In Volume BTL maximum gain from Rin, Lin to R out, L out.4 BTL minimum gain from Rin, Lin to R out, L out db db Phone In Volume BTL gain from Phone In IHF to SPKR out db Zin Phone In IHF Input Impedance, all gains setting kω Zin Phone In HS, Rin & Lin Input Impedance, all gains setting kω tes Enable Step up Time - ENB 2 ns teh Enable Hold Time - ENB 2 ns tel Enable Low Time - ENB 3 ns 8/27

9 Electrical Characteristics tds Data Setup Time- DATA 2 ns tdh Data Hold Time - DATA 2 ns tcs Clock Setup time - CLK 2 ns tch Clock Logic High Time - CLK 5 ns tcl Clock Logic Low Time - CLK 5 ns fclk Clock Frequency - CLK DC MHz Index of Graphics Note: Table 5: Electrical characteristics at VCC = +3. V, GND = V, (unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit Description Figure Page THD + N vs. Output Power Figures to page to page THD + N vs. Frequency Figures 2 to 8 page to page 2 Output Power vs. Power Supply Voltage Figures 9 to 22 page 3 Output Power vs. Load Resistor Figures 23 to 26 page 3 to page 4 PSRR vs. Frequency Figures 27 to 34 page 4 to page 5 Mute Attenuation vs. Frequency Figure35 page5 Frequency Response Figures 36 to 38 page 5 to page 6-3 db Lower Cut Off Frequency vs. Input Capacitor Figures 39 to 4 page 6-3 db Lower Cut Off Frequency vs. Gain Setting Figure39 page6 Power Derating Curves Figure42 page6 Signal to Noise Ratio vs. Power Supply Voltage Figures 43 to 5 page 7 to page 8 Current Consumption vs. Power Supply Voltage Figure5 page8 Power Dissipation vs. Output Power Figures 52 to 55 page 8 to page 9 In the graphs that follow, the abbreviations Spkout = Speaker Output, and HDout = Headphone Output are used. 9/27

10 Electrical Characteristics Figure : Spkout THD+N vs. output power (Output modes, 3, 5, 7) Figure 4: HDout THD+N vs. output power (Output modes 2, 3 G=+6dB). RL = 4Ω F=kHz F=kHz E-3.. Figure 2: Spkout THD+N vs. output power (Output modes, 3, 5, 7). RL = 8Ω F=kHz F=kHz. E-3.. Figure 3: Spkout THD+N vs. output power (Output modes, 3, 5, 7). RL = 6Ω F=kHz F=kHz. E-3... RL = 6Ω F=kHz F=kHz. E-3.. Figure 5: HDout THD+N vs. output power (Output modes 2, 3 G=+3dB). RL = 6Ω F=kHz F=kHz. E-3.. Figure 6: HDout THD+N vs. output power (Output modes 2, 3 G=+6dB). F=kHz F=kHz. E-3.. /27

11 Electrical Characteristics Figure 7: HDout THD+N vs. output power (Output modes 2, 3 G=+3dB) Figure : HDout THD+N vs. output power (Output modes 4, 5 G=+2dB). F=kHz F=kHz. E-3.. Figure 8: HDout THD+N vs. output power (Output modes 4, 5 G=+2dB). RL = 6Ω F=kHz F=kHz. E-3.. Figure 9: HDout THD+N vs. output power (Output modes 4, 5 G=+6dB). RL = 6Ω F=kHz F=kHz. E-3... F=kHz F=kHz. E-3.. Figure : HDout THD+N vs. output power (Output modes 4, 5 G=+6dB). F=kHz F=kHz. E-3.. Figure 2: HDout THD+N vs. frequency (Output modes, 3, 5, 7). RL = 4Ω P=W P=45mW /27

12 Electrical Characteristics Figure 3: Spkout THD+N vs. frequency (Output modes, 3, 5, 7) Figure 6: HDout THD+N vs. Frequency (Output modes 2, 3 G=+6dB). RL = 8Ω P=8mW P=25mW Figure 4: Spout THD+N vs. frequency (Output modes, 3, 5, 7).. RL = 6Ω P=5mW P=8mW Figure 5: HDout THD+N vs. frequency (Output modes 2, 3 G=+6dB). RL = 6Ω G=+6dB, P=5mW, P=5mW.. G=+6dB, P=75mW, P=25mW Figure 7: HDout THD+N vs. frequency (Output modes 4, 5 G=+2dB).. RL = 6Ω G=+2dB P=5mW P=5mW Figure 8: HDout THD+N vs. frequency (Output modes 4, 5 G=+2dB). G=+2dB P=25mW P=75mW.. 2/27

13 Electrical Characteristics Figure 9: Speaker output power vs. power supply voltage (Output modes, 3, 5, 7) Figure 22: Headphone output power vs. power supply voltage (Output modes 2, 3, 4, 5, 6, 7) Output power at % THD + N (W) F = khz 6 Ω Vcc (V) Figure 2: Speaker output power vs. power supply voltage (Output modes, 3, 5, 7) Output power at % THD + N (W) F = khz Figure 2: Headphone output power vs. power supply voltage (Output modes 2, 3, 4, 5, 6, 7) Output power at % THD + N (W) 4 Ω 4 Ω 8 Ω 8 Ω 6 Ω Vcc (V) F = khz 6 Ω 32 Ω Vcc (V) Output power at % THD + N (W) F = khz 6 Ω 32 Ω Vcc (V) Figure 23: Speaker output power vs. load resistance (Output modes, 3, 5, 7) Output power (W) THD+N=% THD+N=% Vcc = 5V F = khz Load Resistance (Ohm) Figure 24: Speaker output power vs. load resistance (Output modes, 3, 5, 7) Output power (W) THD+N=% THD+N=% Vcc = 3V F = khz Load Resistance (ohm) 3/27

14 Electrical Characteristics Figure 25: Headphone output power vs. load resistance (Output modes 2, 3, 4, 5, 6, 7) Figure 28: Spkout PSRR vs. frequency (Output modes 2, 4, 6 input grounded) Output power (mw) THD+N=% THD+N=% Vcc = 5V F = khz Load Resistance (Ohm) Figure 26: Headphone output power vs. load resistance (Output modes 2, 3, 4, 5, 6, 7) PSRR (db) Output power (mw) THD+N=% THD+N=% Vcc = 3V 2 F = khz Load Resistance (Ohm) Figure 27: Spkout PSRR vs. frequency (Output modes, 3, 5, 7 input grounded) Ouput mode, 3, 5, 7 RL = 8Ω Vripple=.2Vpp -9 PSRR (db) PSRR (db) Ouput mode 2, 4, 6 RL = 8Ω Vripple=.2Vpp -8 Figure 29: HDout PSRR vs. frequency (Output modes 2, 3 input grounded) Output mode 2, 3 Vcc=+5V Vripple=.2Vpp G=+6dB G=-6dB G=-8dB G=+3dB G=-4.5dB G=dB -7 Figure 3: HDout PSRR vs. frequency (Output modes 2, 3 input grounded) PSRR (db) Output mode 2, 3 Vcc=+3V Vripple=.2Vpp G=+6dB G=+3dB G=-6dB G=dB G=-4.5dB G=-8dB -6 4/27

15 Electrical Characteristics Figure 3: HDout PSRR vs. frequency (Output modes 4, 5 inputs grounded) Figure 34: HDout PSRR vs. frequency (Output modes 6, 7 inputs grounded) PSRR (db) PSRR (db) PSRR (db) Output mode 4, 5 Vcc=+5V Vripple=.2Vpp G=+2dB G=+9dB G=+6dB G=-34.5dB G=-2dB G=dB Figure 32: HDout PSRR vs. frequency (Output modes 4, 5 inputs grounded) Output mode 4, 5 Vcc=+3V Vripple=.2Vpp G=+2dB G=+6dB G=+9dB G=-34.5dB G=-2dB G=dB -6 Figure 33: HDout PSRR vs. frequency (Output modes 6, 7 inputs grounded) Output mode 6, 7 Vcc=+5V Vripple=.2Vpp G=+6dB G2=+2dB G=dB G2=+6dB G=+3dB G2=+9dB G=-6dB G2=dB G=-4.5dB G2=-34.5dB G=-8dB G2=-2dB -6 PSRR (db) Mute attenuation (db) Output mode 6, 7 Vcc=+3V Vripple=.2Vpp G=+6dB G2=+2dB G=dB G2=+6dB G=+3dB G2=+9dB G=-6dB G2=dB G=-4.5dB G2=-34.5dB G=-8dB G2=-2dB Figure 35: Spkout mute attenuation vs. frequency (Output modes 2, 4, 6) Ouput mode 2, 4, 6 RL = 8Ω VinPIHF=Vrms Figure 36: Spkout frequency response (Output modes, 3, 5, 7) Output level (db) Ouput mode, 3, 5, 7 RL = 8Ω Cin=22nF VinPIHF=.2Vrms 2 5/27

16 Electrical Characteristics Figure 37: HDout frequency response (Output modes 2, 3 G=+6dB) Figure 4: HDout -3dB lower cut-off frequency vs. input capacitor (Output modes 2, 3, 4, 5, 6, 7) Output level (db) Output level (db) Ouput mode 2, 3 Cin=22nF VinPHS=.2Vrms G=+6dB 2 Figure 38: HDout frequency response (Output modes 4, 5 G=+2dB) Ouput mode 4, 5 Cin=22nF VinR/L=.2Vrms G=+2dB 2 Figure 39: Spkout -3dB lower cut off freq. vs. input capacitor (Output modes, 3, 5, 7) Lower -3dB Cut Off Typical Input Impedance Minimum Input Impedance Maximum Input Impedance Phone In IHF Input Tamb=25 C Input Capacitor ( F) Lower -3dB Cut Off Typical Input Impedance Minimum Input Impedance Maximum Input Impedance Phone In HS Input Rin & Lin Inputs All gain setting Tamb=25 C Input Capacitor ( F) Figure 4: HDout -3dB lower cut-off freq. vs. gain setting (Output modes 2, 3, 4, 5, 6, 7) Phone In Hs / Rin & Lin Inputs Tamb=25 C Cin=µF Gain Setting (db) Cin=nF Cin=22nF Cin=47nF Figure 42: Power derating curves Lower -3dB Cut Off Flip-Chip Package Power Dissipation (W) No Heat sink Heat sink surface = 25mm Ambiant Temperature ( C) 6/27

17 Electrical Characteristics Figure 43: Spkout SNR vs. power supply voltage, unweighted filter, BW = 2 Hz to 2 khz Figure 46: HDout SNR vs. power supply voltage, weighted filter A, BW=2Hz to 2kHz SNR (db) Vcc = 3V Vcc = 5V RL=8Ω Unweighted filter (2Hz to 2kHz) THD + N <.7% Output Mode Figure 44: Spkout SNR vs. power supply voltage, weighted filter A, BW = 2 Hz to 2 khz SNR (db) Vcc = 3V Vcc = 5V RL=8Ω Weighted filter A (2Hz to 2kHz) THD + N <.7% Output Mode Figure 45: HDout SNR vs. power supply voltage, unweighted filter, BW= 2 Hz to 2 khz SNR (db) Vcc = 3V Vcc = 5V G=+6dB Unweighted filter (2Hz to 2kHz) THD + N <.7% Output Mode SNR (db) Vcc = 3V Vcc = 5V G=+6dB Weighted filter A (2Hz to 2kHz) THD + N <.7% Output Mode Figure 47: HDout SNR vs. Power supply voltage, unweighted filter, BW=2Hz to 2kHz SNR (db) Vcc = 3V Vcc = 5V G=+2dB Unweighted filter (2Hz to 2kHz) THD + N <.7% Output Mode Figure 48: HDout SNR vs. power supply voltage, weighted filter A, BW = 2 Hz to 2 khz SNR (db) Vcc = 3V Vcc = 5V G=+2dB Weighted filter A (2Hz to 2kHz) THD + N <.7% Output Mode 7/27

18 Electrical Characteristics Figure 49: HDout SNR vs. power supply voltage, unweighted filter, BW = 2 Hz to 2 khz) Figure 52: Power dissipation vs. output power: speaker output SNR (db) Vcc = 3V Vcc = 5V G=+6dB and +2dB Unweighted filter (2Hz to 2kHz) THD + N <.7% Output Mode Figure 5: HDout SNR vs. power supply voltage, weighted filter A, BW = 2 Hz to 2 khz) SNR (db) Vcc = 3V Vcc = 5V G=+6dB and +2dB Weighted filter A (2Hz to 2kHz) THD + N <.7% Output Mode Figure 5: Current consumption vs. power supply voltage Icc (ma) Output mode 2 to 7 no loads Output mode RL=8Ω Output mode 2 to 7 RL=8Ω and 2x32Ω Output mode no load Vcc (V) Power Dissipation (W) F=kHz THD+N<% RL=4Ω RL=8Ω.2 RL=6Ω Figure 53: Power dissipation vs. output power: speaker output Power Dissipation (W) F=kHz THD+N<% RL=6Ω RL=8Ω RL=4Ω Figure 54: Power dissipation vs. output power. headphone output one channel Power Dissipation (W) F=kHz THD+N<% RL=32Ω RL=6Ω /27

19 Electrical Characteristics Figure 55: Power dissipation vs. output power. headphone output one channel Power Dissipation (mw) F=kHz THD+N<% RL=32Ω RL=6Ω Output Power (mw) 9/27

20 Application Information 6 APPLICATION INFORMATION 6. BTL Configuration Principle The integrates 3 monolithic power amplifiers having BTL output. BTL (Bridge Tied Load) means that each end of the load is connected to two single-ended output amplifiers. Thus, we have: Single ended output = Vout = Vout (V) Single ended output 2 = Vout2 = -Vout (V) and Vout - Vout2 = 2Vout (V) The output power is: For the same power supply voltage, the output power in BTL configuration is 4 times higher than the output power in single-ended configuration. 6.2 Power dissipation and efficiency Hypotheses: Voltage and current in the load are sinusoidal (Vout and Iout). Supply voltage is a pure DC source (Vcc). Regarding the load we have: and and (2 Vout Pout = R (W) Therefore, the average current delivered by the supply voltage is: The power delivered by the supply voltage is: Psupply = Vcc Icc AVG (W) L RMS VOUT = V PEAK sinωt (V) IOUT = VOUT R L ) (A) POUT = VPEAK (W) 2RL ICC AVG = 2 VPEAK (A) πrl Then, the power dissipated by each amplifier is Pdiss = Psupply - Pout (W) and the maximum value is obtained when: and its value is: Note: P diss 2 2 V = π R CC L P (W) This maximum value is only depending on power supply voltage and load values. The efficiency is the ratio between the output power and the power supply The maximum theoretical value is reached when Vpeak = Vcc, so The has 3 independent power amplifiers and each amplifier produces heat due to its power dissipation. Therefore, the maximum die temperature is the sum of the each amplifier s maximum power dissipation. It is calculated as follows: P diss speaker = Power dissipation due to the speaker power amplifier. P diss head = Power dissipation due to each headphone s power amplifier. P OUT Pdiss = POUT 2Vcc Pdissmax = 2 π R η = POUT OUT (W) Total P diss =P diss speaker +P diss head +P diss head2 (W) L = πvpeak Psupply 4VCC 2 π ---- = 78.5% 4 In most cases, P diss head = P diss head 2, giving: Total P diss = P diss speaker +2P diss head (W) 2 2 V P P CC OUT SPEAKER TotalP diss = + 2 π RL SPEAKER RL HEAD [ P + 2 P ] (W) OUT SPEAKER OUT HEAD OUT HEAD 2/27

21 Application Information The following graph shows an example of the previous formula, with Vcc set to +5 V, R load speaker set to 8 Ω, and R load headphone se to 6 Ω. Figure 56: Example of total power dissipation vs. speaker and headphone output power Total Power Dissipation (W) Low frequency response In low frequency region, the effect of Cin starts. Cin with Zin forms a high pass filter with a -3 db cut off frequency. Zin is the input impedance of the corresponding input: 2 kω for Phone In IHF input 5 kω for the 3 other inputs Note: Speaker Ouput Power (W) F CL THD+N<% Tamb=25 C = (Hz) 2 π Zin Cin For all inputs, the impedance value remains constant for all gain settings. This means that the lower cut-off frequency doesn t change with gain setting. Note also that 2 kω and 5 kω are typical values and there are tolerances around these values (see Electrical Characteristics on page 6). In Figures 39 to 4, you could easily establish the Cin value for a -3 db cut-off frequency required. 6.4 Decoupling of the circuit Headphone Output Power (mw) Two capacitors are needed to bypass properly the, a power supply bypass capacitor Cs and a bias voltage bypass capacitor Cb. Cs has especially an influence on the THD+N in high frequency (above 7 khz) and indirectly on the power supply disturbances. With µf, you could expect similar THD+N performances like shown in the datasheet. If Cs is lower than µf, THD+N increases in high frequency and disturbances on the power supply rail are less filtered. To the contrary, if Cs is higher than µf, those disturbances on the power supply rail are more filtered. Cb has an influence on THD+N in lower frequency, but its value is critical on the final result of PSRR with input grounded in lower frequency: If Cb is lower than µf, THD+N increases at lower frequencies and the PSRR worsens upwards. If Cb is higher than µf, the benefit on THD+N and PSRR in the lower frequency range is small. 6.5 Startup time When the is controlled to switch from the full standby mode (output mode ) to another output mode, a delay is necessary to stabilize the DC bias. This delay depends on the Cb value and can be calculated by the following formulas. Typical startup time =.75 x Cb (s) Max. startup time =.25 x Cb (s) (Cb is in µf in these formulas) These formulas assume that the Cb voltage is equal to V. If the Cb voltage is not equal to V, the startup time will be always lower. The startup time is the delay between the negative edge of Enable input (see SPI Operation Description on page 3) and the power ON of the output amplifiers. Note: When the is set in full standby mode, Cb is discharged through an internal switch. The time to reach V of Cb voltage with µf is about ms. 2/27

22 Application Information 6.6 Pop and Click performance The has internal Pop and Click reduction circuitry. The performance of this circuitry is closely linked with the value of the input capacitor Cin and the bias voltage bypass capacitor Cb. The value of Cin is due to the lower cut-off frequency value requested. The value of Cb is due to THD+N and PSRR requested always in lower frequency. The is optimized to have a low pop and click in the typical schematic configuration (see page 2). Note: The value of Cs is not an important consideration as regards pop and click. 6.7 Notes on PSRR measurement What is the PSRR? The PSRR is the Power Supply Rejection Ratio. The PSRR of a device, is the ratio between a power supply disturbance and the result on the output. We can say that the PSRR is the ability of a device to minimize the impact of power supply disturbances to the output. How we measure the PSRR? The PSSR was measured according to the schematic shown in Figure 57. Figure 57: PSRR measurement schematic Principles of operation The DC voltage supply (Vcc) is fixed. The AC sinusoidal ripple voltage (Vripple) is fixed. No bypass capacitor Cs is used. The PSRR value for each frequency is: Note: PSRR RMS = 2 Log RMS The measure of the Rms voltage is a Rms selective measure with a bandpass equal to % of the measured frequency. 6.8 Power-On Reset ( Output ) ( Vripple (db ) When Power is applied to Vdd, an internal Power On Reset holds the in a reset state until the Supply Voltage reached its nominal value. The Power On reset has a typical threshold at.8v. ) 22/27

23 Application Information Figure 58: Footprint Recommendation 23/27

24 Package Information 7 PACKAGE INFORMATION Flip-chip package 8 bumps: IJT Marking (on top view) Package mechanical data 75µm 5µm 244µm 866µm 866µm ST LOGO Part number: B55 Three digit Datecode: YWW The dot is for marking the bumpa 27µm Die size: 244µm x 27µm ±3µm Die height (including bumps): 6µm Nominal Bumps diameter: 35µm ±µm Nominal Bumps height: 25µm ±µm Pitch: 5µm ±µm Die Height : 35µm ±2µm 6µm 24/27

25 Package Information Pin out (top view) 7 R OUT- GND L OUT - 6 R OUT + L OUT R VDD DATA IN PHONE IN HS BYPASS A L IN SPKR OUT - B VDD GND C PHONE IN IHF SPKR OUT + D ENB CLK E 25/27

26 Package Information Daisy chain mechanical data All drawings dimensions are in millimeters 2.44 mm 7 R OUT- GND L OUT - Remarks Daisy chain sample is featuring pin connection two by two. The schematic above is illustrating the way connecting pins each others. This sample is used for testing continuity on board. PCB needs to be designed on the opposite way, where pin connections are not done on daisy chain samples. By that way, just connecting a Ohmmeter between pin A and pin 5A, the soldering process continuity can be tested. Order code R IN PHONE IN HS BYPASS A R OUT + L IN SPKR OUT - B Package Part Temperature Marking Number Range J TSDC2IJT -4, +85 C DC2 VDD VDD GND C L OUT + PHONE IN IHF SPKR OUT + D DATA ENB CLK E 2.7 mm 26/27

27 Tape & Reel Specification 8 TAPE & REEL SPECIFICATION Figure 59: Top view of tape & reel Device orientation A A User direction of feed The devices are oriented in the carrier pocket with bump number A adjacent to the sprocket holes. Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 24 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom 27/27