Design of Very Low Power 8 Bit SAR ADC in 90 nm using STSCL Approach

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1 ISSN : (Online) ISSN : (Print) Abstract Low power design has become the main concern for batterypowered portable applications, such as environmental monitoring and biomedical detection. This paper presents a novel approach for implementing ultra-low-power SAR ADC using Source- Coupled Logic (SCL) circuit topology, operating in weak inversion (subthreshold) regime. Minimum size pmos transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in subthreshold CMOS circuits. An 8 bit SAR ADC is implemented using 90nm technology. The measurement shows the power consumption of few micro watts & performance near to ideal. Keywords Power Delay Product, Source-Coupled Logic (SCL), Subthreshold SCL, Ultra-Low-Power Circuits, Weak Inversion, Analog-to- Digital Conversion, SAR ADC I. Introduction Recently, energy-efficient products have been the hot issue of the society for the preservation of the environment. Along with the boom of the hand-held mobile products with touch screens the need for the low-power high-efficient products is intense. The SAR Analog-to-Digital Converter (ADC) has the lowest power consumption and modest resolution among various ADC structures [9-12]. Therefore, the SAR ADC is suitable in lowpower systems such as mobile systems or touch screens. SAR ADC s power consumption has been decreased and its sampling speed has been continuously increased to expand its application area and it gradually replaces other ADC s areas. Subthreshold source coupled logic is proposed in order to reduce the current density. This topology allows adjusting the power consumption playing on the bias conditions. Supply voltage reduction, reduces total power consumption but on the other hand, increases the delay in each gate which means the power dissipation, logic swing, and speed of operation are tightly related to each other. Meanwhile, the exponential relationship between power dissipation and supply voltage in subthreshold regime makes the accurate control of power consumption difficult. To implement very low power digital systems, it is necessary to minimize the energy dissipation at the system level in addition to the gate level to achieve the desired performance [2]. Source- Coupled Logic (SCL) circuits are widely used in mixed mode integrated circuits where supply noise and substrate noise injection are crucial [3]. Reduced output voltage swing in SCL circuits compared to the CMOS logic gates has made this topology very suitable for high frequency applications [4-5]. This paper explores the potentials of subthreshold SCL circuits as an alternative solution for implementing ultra-low-power comparator. In this approach, the power consumption and maximum speed of operation of IJECT Vo l. 3, Is s u e 1, Ja n. - Ma r c h 2012 Design of Very Low Power 8 Bit SAR ADC in 90 nm using STSCL Approach 1 Chandradatta Verma, 2 Chandrahas Sahu 1,2 Dept. of Electronics and Telecommunication, Shri Sankeracharya Group of Institution, Bhilai,CG, India comparator can be adjusted linearly through the tail bias current of each gate over a very wide range [6-7], thus, efficiently decoupling the decision of output voltage swing from power dissipation and delay. To enable operation at very low current levels and to achieve the desired performance specifications, special circuit techniques have to be applied, [5-8], for implementing very low power SCL circuits. In [7], the intrinsically limited output impedance of deep-submicron, short-channel pmos devices has been used to implement very high value load resistances for SCL topology. Here, a more general approach with much less sensitivity to process and technology variations will be introduced [6]. II. Over All Architecture Fig. 1, shows the overall circuit architecture of the ADC. SAR ADC has four mains building blocks: Comparator Digital-to-Analog Converter (DAC) Sample-and-Hold Stage (S/H) Successive Approximation Register (SAR) The analog input voltage VIN is sampled by sampled by the Track & Hold block. To implement the binary search algorithm, the N-bit register is first set to midscale setting the MSB to 1 and all other bits to 0. This forces the DAC output, VDAC, to be half of the reference voltage, VREF/2. VIN is then compared with VDAC, if VIN is greater than VDAC, the comparator output is logic 1 and the MSB of the N-bit register comparator output is logic 0 and the MSB of the Fig. 1: A Simplified SAR ADC register is cleared to 0. The SAR control logic then moves to the next bit down, forces that bit high, and does another comparison. The sequence continues all the way down to the LSB. Once this is done, the conversion is completed, and the N-bit digital word is available in the register [13]. III. Comparator The comparator is the block that affects the most the total power consumption of the SAR ADC; it is composed by preamplifiers and latch. Most of the analog power is consumed by the comparator and it is almost constant with respect the clock frequency while In t e r n a t i o n a l Jo u r n a l o f El e c t r o n i c s & Co m m u n i c a t i o n Te c h n o l o g y 217

2 IJECT Vo l. 3, Is s u e 1, Ja n. - Ma r c h 2012 depends on the value of the supply voltage (as shown in fig. 2 & fig. 3). Fig. 2: Power vs. Frequency ISSN : (Online) ISSN : (Print) output voltage swing, the load resistance should be in the range of hundreds of MΩ. Meanwhile, this resistance should be controlled very accurately based on the I SS value. Hence, a well controlled high resistivity load device with a very small area is required. fig. 5, shows the proposed load device, where the drain of the pmos device is connected to its bulk. The cross section view of the proposed pmos load device can be seen in Fig. 5.Connecting the drain to the bulk of the pmos load device ties the cathode of the n-well-to-substrate reversebiased diode to the output node. However, since the devices are minimum size, the parasitic capacitance associated with this diode is very small and can usually be neglected. The other important parasitic element is the forward biased source-bulk diode; this diode can limit the possible voltage swing at the drain of the device to mv. This new topology makes the velocity of the comparator independent from the supply voltage with minimum power consumption (fig. 4). A. Subthreshold Source-Coupled Logic Source-Coupled Logic [1, 18], allows reducing the sensitivity of the circuit to the supply voltage variation. Hence the speed of operation of this logic is independent from the supply voltage while can be controlled by acting on the tail bias current. Moreover, using transistors operating in weak inversion, subthreshold regime, the current density is very low while the ratio between transconductance and bias current, gm/id, is maximum. STSCL logic gates can operate biased with a very small tail current which value can range from 10 pa to 100 na. It is been shown that in STSCL circuits the power consumption can be reduced to 1fJ/ gate, this makes this approach very suitable for low voltage-low power applications. Fig. 4: STSCL Circuit of the Comparator, and Replica Bias Circuit Fig. 5: Proposed Load Device However, as the required voltage swing for subthreshold SCL gates is well below this value, the source-bulk diode does not influence the operation of the circuit. Using the EKV model, the I V characteristics of the subthreshold pmos device can be expressed by [7-8]. Fig. 3: Normalized ADC Energy vs. Supply Voltage B. PMOS Load Devices The proposed comparator biased in subthreshold is implemented using a pmos load device. To maintain the desired output voltage swing at very low bias current levels, it is necessary to increase the load resistance value in inverse proportion to the reducing tail bias current as RL=V SW /I SS (1) In subthreshold operation, the tail bias current would be in the range of few na or even less. Therefore, to obtain a reasonable 218 International Journal of Electronics & Communication Technology (2) Where, n p is the subthreshold slope factor; UT is the thermal voltage. The current I 0 is given by: (3) In the proposed configuration illustrated in fig. 5, VBD=0 hence, (4) Therefore, the output small signal resistance of the proposed

3 ISSN : (Online) ISSN : (Print) IJECT Vo l. 3, Is s u e 1, Ja n. - Ma r c h 2012 (5) In which and (6) Thus, RSD can be controlled through the Source-Gate Voltage (VSG) of the device through ISD. Because of exponential dependence of the output resistance on VSG, it can be adjusted in a very wide range. To avoid process-related deviations, a replica bias generator is required for VSG, as explained in the next section. The wide tuning range of RSD means that the proposed STSCL gate can be used in a very wide range of operating conditions without the need for modifying the size of devices. C. Replica Bias The value of the PMOS load resistor can vary between hundreds of KΩ and 1GΩ, and it depends on the gate voltage VG of the device. In order to bias the load devices to have the right resistance and control VSW at the output of the comparator, a replica bias circuit is used (real schematic in Appendix IV, simplified schematic in fig. 4). The replica bias circuit should be well matched to the SCL gates, conversely, we would have a variation with respect to the desired operating point that is not negligible, and the output voltage swing would be different than the desired one. In terms of accuracy, the amplifier is a critical component; we need it to provide enough gain with a very low offset. D. Design Approach Here we design the preamplifiers of our comparator; we base our calculation on the Enz-Krummenacher-Vittoz (EKV) model. Its equations are valid in all regimes of operation, above or below threshold, as well as in saturation, for this reason, the EKV model is highly suitable our low-voltage circuit that operates in subthreshold regime [14]. The MOS digital circuits operate in subthreshold regime when the supply voltage is lower than the threshold voltage V th of the transistors. The drain current of an NMOS transistor operating in this regime is given by eq 4. The voltage swing at the output is (7) And it should be large enough to guarantee to switch completely the current in the input transistors of the next stage. It means that, being in subthreshold region, we need (8) The gain of each stage depends on the voltage swing Vsw. In order to calculate the voltage gain, the transconductance of the input differential pair can be expressed by: Fig. 6: Comparator Circuit Schematic Each preamplifier consists of an N-mirror, a differential pair and the P-load. The simplified schematic of a single preamplifier is shown in fig. 7. IV. Digital to Analog Converter The traditional binary weighted capacitor array has been chosen for the ease of operation. The ideal capacitors have then been replaced with symmetric Metal Oxide Metal, MOM, capacitors, the basic capacitance is chosen to be C0=100fF. MOM capacitors rely on coupling capacitance between metal fingers running in parallel. We choose a symmetric architecture; the equivalent circuit is shown in fig. 8. Using a configuration with the same value of parasitic capacitance on the top and the bottom plate means that the architecture is basically symmetric in terms of the two ports. Each analog switch has been implemented connecting an NMOS in parallel with a PMOS. The NMOS is driven by the signal coming from the logic block, while the PMOS is driven by the inverted signal. The switch conductivity depends not on the absolute potential of the control terminals, but on their potential relative to the others. (9) Where, ΔVin is the input differential voltage. It can be shown that there is an upper bound for the differential gain of the circuit for ΔVin = 0V that can be expressed as (10) E. Circuit Implementation The comparator is implemented with two preamplifier stages, and one latch. The preamplifiers amplifies the differential signal, than the latch establish full logic levels and synchronize the decision of the comparator with the other blocks. Fig. 7: Simplified Schematic of the Preamplifier In t e r n a t i o n a l Jo u r n a l o f El e c t r o n i c s & Co m m u n i c a t i o n Te c h n o l o g y 219

4 IJECT Vo l. 3, Is s u e 1, Ja n. - Ma r c h 2012 Fig. 8: Equivalent Sub-circuit of MOM Capacitor Model ISSN : (Online) ISSN : (Print) is f -3dB =46.8 khz, this is a value sufficiently large considering our working frequency. The phase margin is PM=74 and the gainbandwidth product is f GBW =167 khz. Fig. 12, shows the simulated response of the comparator for a differential input square wave. The first component to be substituted has been the capacitors of the DAC, then, we perform some Monte Carlo simulations. We have performed 100 runs; each run, the tool inserted a mismatch between the capacitors, where C0=100fF. Whether the n- or the p-channel device carries more signal current depends on the ratio of input to output voltage. Because the switch has no preferred direction for current flow, it has no preferred input or output. Fig. 11: Gain and Phase of the Preamplifier Fig. 9: Switch Circuit Schematic Using the Fast Fourier Transform (FFT), the power spectrum is plotted in the Nyquist bandwidth fs/2. We define a sampling clock fs=1.024 khz, than we simulate for a number of fft points N fft =256. The frequency of the input sinusoidal signal is fin=255hz. The power spectrum in fig. 14, is plotted for the simulation of the ADC with real components. V. Sample and Hold In the typical configuration of the SAR ADC, the Track and Hold is one of the basic building blocks. In our SAR ADC we choose to use the capacitor array as sampling capacitor to acquire the analog signal during the sampling phase, that least one clock period, and avoid this block. The reasons of this choice are several, first of all the Track & Hold circuit would need a switch and a capacitor, but also a voltage follower to adapt the impedance. This would add consumption of power that can be avoided. In order to charge directly on the DAC capacitors, we decide to define our specification on the sampling frequency in order to have driving impedance relatively high. In this way, our A/D converter can be directly driven by an external compatible impedance source, as shown in fig. 10, without gain error. Fig. 12: Comparator Transient Response for a Differential Input of 4mV Fig. 10: External Driving Circuit for the Analog Differential Input VI. Experimental Results The ADC circuit has been implemented in TANNER with ideal components, and then one kind of component has been substituted with the real one at each time in order to simulate its effect on the linearity. The comparator has two preamplifier stages and one latch. In fig. 11, the gain and phase versus frequency are plotted. The gain of a single preamplifier stage is A 0 =11.34dB. The frequency at -3dB 220 International Journal of Electronics & Communication Technology

5 ISSN : (Online) ISSN : (Print) IJECT Vo l. 3, Is s u e 1, Ja n. - Ma r c h 2012 VII. Conclusion From the results presented in the previous chapter it can be deduced that the performance of the ADC less than ideal. Actually it consumes a low amount of power, few tens of micro-watts, but the price to pay is in the speed of the conversion. Fig. 13: DNL and INL-Real Capacitors Power supply Process Technology Input dynamic range Resolution Sampling Rate Basic capacitor C0 Bias current Ibias Power 1.2 V 90 nm ±1.2V (differential) 8 bits 2.4 ksample/s ff 50 na 12.4 μw Fig. 14: Power Spectrum for the Real Circuit The output of the DAC is the input of the comparator. Whatever is the number to convert, the common mode of the comparator differential input is always 0.6V, half of the full scale. This avoids problems due to the input range of the comparator. The Power consumption can be estimated by current measurement because current is directly proportional to the power consumption. We consider the rms (root mean square) value of the currents flowing through: The comparator: Icomparator; The digital logic block: ISARlogic; The Digital to Analog converter: IDAC; The others analog blocks, level shifter and delay cells: Ianalog; The whole ADC circuit: I TOT = rms (I comparator + I SARlogic +I analog +I DAC ). C fF I bias 50nA Table 1: Current Versus a Change in Frequency fint [Hz] I comp arator I SARlogic I analog I DAC I TOT 8 k 495n 8.28u 2.66u 5.04u 10.74u 12.5 k 496n 9.21u 2.39u 4.04u 11.15u 20 k 505n 12.56u 2.39u 4.25u 14.18u P= VDD* I TOT [W] 11.9u 12.4u 17.0u References [1] A.Tajalli, Elizabeth J. Brauer et al., Subthreshold Source- Coupled Logic Circuits for Ultra-Low-Power Applications, IEEE J. Solid-State Circuits, Vol. 43, No.7, pp , [2] B. H. Calhoun, A. Wang, A. Chandrakasan, Modeling and sizing for minimum energy operation in subthreshold circuits, IEEE J. Solid- State Circuits, Vol. 40, No. 9, pp , [3] J.M. Musicer, J. Rabaey, MOS current mode logic for low power, low noise CORDIC computation in mixedsignal environment, in Proc. IEEE Int. Symp. Low Power Electronics and Design (ISLPED), pp , [4] S. Badel, Y. Leblebici, Breaking the power delay tradeoff: Design of low-power high-speed MOS current-mode logic circuits operating with reduced supply voltage, in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), pp , May [5] M. Alioto, G. Palumbo, Model and Design of Bipolar and MOS Current-Mode Logic (CML, ECL and SCL Digital Circuits), New York: Springer, [6] E. Brauer, Y. Leblebici, Semiconductor based high-resistance device and logic application, European Patent Application No , , 2007, March 26. [7] A. Tajalli, E. Vittoz, Y. Leblebici, E. J. Brauer, Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept, in Proc. European Solid-State Circuits Conf. (ESSCIRC), Munich, Germany, Sep. 2007, pp [8] F. Cannillo, C. Toumazou, T. S. Lande, Bulk-drain connected load for subthreshold MOS current-mode logic, IEEE Electron. Lett. Vol. 43, No. 12, pp , Jun [9] M. D. Scott, B. E. Boser, K. S. J. Pister, An Ultra-Energy ADC for Smart Dust, IEEE J. Solid-state Circuits, Vol. 38, pp , In t e r n a t i o n a l Jo u r n a l o f El e c t r o n i c s & Co m m u n i c a t i o n Te c h n o l o g y 221

6 IJECT Vo l. 3, Is s u e 1, Ja n. - Ma r c h 2012 [10] S. M. Chen, R. W. Brodersen, A 6-bit 600-MS/s 5.3-Mw Asynchronous ADC in 0.13-um CMOS, IEEE J. Solid-state Circuits, Vol. 41, pp , [11] S. M. Louwsma, E. J.M. van Tuijl, M. Vertregt and B. Nauta, A 1.35 GS/s, 10b, 175 mw Time-Interleaved AD Converter in 0.13 um CMOS, Symposium on VLSI Circuits Digest of Technical Papers, [12] P. N. Singh, A. Kumar, C. Debnath, R. Malik, 20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process, IEEE 2007 Custom Integrated Circuits Conference, pp , Sep [13] [Online] Available: an_pk / 1080/, 21 juin [14] C.J.B. Fayomi, M.Sawan, G.W. Roberts, Low-Voltage Analog Switch in Deep Submicron CMOS: Design Technique and Experimental Measurements, IEICE Trans. Fundamentals, Vol. E89 A, No. 4, April [15] A. Tajalli, E. Vittoz, Y. Leblebici, Elizabeth J. Brauer, Ultra Low Power Subthreshold MOS Current Mode Logic Circuits Using a Novel Load Device Concept, Solid State Circuits Conference, ESSCIRC rd European, September [16] S. Gambini, J. Rabaey, Low Power Successive Approximation Converter With 0.5 V Supply in 90nm CMOS, IEEE J. Solid-State Circuits, Vol. 42, No. 11, [17] H.C. Hong, G.M. Lee, A 65-fJ/Conversion-Step 0.9-V 200- ks/s Rail-to-Rail 8-bit Successive Approximation ADC, IEEE J. Solid-State Circuits, Vol. 42, No. 10, [18] A. Tajalli, E. J. Brauer, Y.Leblebici, Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fj/stage PDP, Microelectronics Journal 40, pp , ISSN : (Online) ISSN : (Print) Chandradatta Verma received his B.E. degree in Electronics and Telecommunication from Rungta College of Engineering and Technology, Bhilai, India, in 2009, and pursuing the M.E. degree in VLSI Design from Chhattisgarh Swami Vivekanand Technical University, Bhilai, India. He is an assistant professor, Shri Shankaracharya institute of Management and Technology. His research interests include digital image processing, digital signal processing, advance communication technology and VLSI technology. Chandrahas Sahu received his B.E. degree in Electronics & Telecommunication from Rungta College of Engineering & Technology Bhilai, Chhattisgarh, India, in 2005, the M.E degree in VLSI Design from CSVTU, Bhilai, Chhattisgarh, India, in His research interests include digital signal processing, electronic measurement techniques; low power vlsi design. He is working as a assistant professor in the department of Electronics & Instrumentation of shri shankaracharya Technical Campus Bhilai, Chhattisgarh, India since At present, He is engaged in to minimization of power in Analog to digital converter application. 222 International Journal of Electronics & Communication Technology