Wide-Bandwidth 2 x 1 VIDEO MULTIPLEXER

Transcription

1 Wide-Bandwidth x VIDEO MULTIPLEXER FEATURES BANDWIDTH: MHz (.Vp-p) LOW INTERCHANNEL CROSSTALK: 79dB (MHz, SO); 77dB (MHz, DIP) LOW SWITCHING TRANSIENTS: mv/ mv LOW DIFFERENTIAL GAIN/PHASE ERRORS:.%,. LOW QUIESCENT CURRENT: One Channel Selected: ±.ma No Channel Selected: ±µa APPLICATIONS VIDEO ROUTING AND MULTIPLEXING (CROSSPOINTS) RADAR SYSTEMS DATA ACQUISITION INFORMATION TERMINALS SATELLITE OR RADIO LINK IF ROUTING DESCRIPTION The is a wide-bandwidth, -to- channel video signal multiplexer, which can be used in a wide variety of applications. It was designed for wide-bandwidth systems, including high-definition television and broadcast equipment. Although it is primarily used to route video signals, the harmonic and dynamic attributes of the also make it appropriate for other analog signal routing applications such as radar, communications, computer graphics, and data acquisition systems. The consists of two identical monolithic, integrated, open-loop buffer amplifiers, which are connected internally at the output. The bipolar complementary buffers form a unidirectional transmission path and offer extremely high output-to-input isolation. The multiplexer enables the user to connect one of two input signals to the output. The output of the multiplexer is in a high-impedance state when no channel is selected. When one channel is selected with a digital at the corresponding SEL input, the component acts as a buffer with high input impedance and low output impedance. The wide bandwidth of over MHz at.vp-p signal level, high linearity and low distortion, and low input voltage noise of nv/ Hz make this crosspoint switch suitable for RF and video applications. All performance is specified with ±V supply voltage, which reduces power consumption in comparison with ±V designs. The multiplexer is available in a spacesaving -pin SO and DIP packages. Both are designed and specified for operation over the industrial temperature range ( C to C.) IN TRUTH TABLE IN SEL SEL SEL SEL HI-Z IN IN International Airport Industrial Park Mailing Address: PO Box Tucson, AZ 7 Street Address: 7 S. Tucson Blvd. Tucson, AZ 7 Tel: () 7- Twx: 9-9- Cable: BBRCORP Telex: -9 FAX: () 9- Immediate Product Info: () - 99 Burr-Brown Corporation PDS-B Printed in U.S.A. July, 99

2 SPECIFICATIONS DC CHARACTERISTICS At V CC = ±VDC, R L = kω, R IN =, R SOURCE = Ω, and T A = C, unless otherwise noted. AP, AU PARAMETER CONDITIONS MIN TYP MAX UNITS INPUT OFFSET VOLTAGE Initial ± mv vs Temperature µv/ C vs Supply (Tracking) V CC = ±.V to ±.V db vs Supply (Non-tracking) V CC =.V to.v db vs Supply (Non-tracking) V CC =.V to.v db Initial Matching All Buffers mv INPUT BIAS CURRENT Initial ± µa vs Temperature na/ C vs Supply (Tracking) V CC = ±.V to ±.V ±7 na/v vs Supply (Non-tracking) V CC =.V to.v. µa/v vs Supply (Non-tracking) V CC =.V to.v.7 µa/v INPUT IMPEDANCE Resistance Channel On. MΩ Capacitance Channel On. pf Capacitance Channel Off. pf INPUT NOISE Voltage Noise Density f OUT = khz to MHz nv/ Hz Signal-to-Noise Ratio S/N =.7/V N MHz 9 db INPUT VOLTAGE RANGE Gain Error = % ±. V TRANSFER CHARACTERISTICS Voltage Gain R L = kω, V IN = ±V.9 V/V R L = kω, V IN = ±.V.9.99 V/V RATED OUTPUT Voltage V IN = ±V ±. ±.97 V Resistance One Channel Selected. Ω Resistance No Channel Selected 9 MΩ Capacitance No Channel Selected. pf CHANNEL SELECTION INPUTS Logic Voltage V CC. V Logic Voltage. V Logic Current V SEL =.V 7 µa Logic Current V SEL =.V. µa SWITCHING CHARACTERISTICS V I =.V to.7v, f = MHz SEL to Channel ON Time 9% Point of = Vp-p. µs SEL to Channel OFF Time % Point of = Vp-p.7 µs Switching Transient, Positive (Measured While Switching mv Switching Transient, Negative Between Two Grounded Channels) mv POWER SUPPLY Rated Voltage ± V Derated Performance ±. ±. V Quiescent Current One Channel Selected, Over Temperature ±. ±. ma No Channel Selected, Over Temperature ± ±7 µa Rejection Ratio db The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

3 SPECIFICATIONS AC CHARACTERISTICS At V CC = ±VDC, R L = kω, R IN =, R SOURCE = Ω, and T A = C, unless otherwise noted. AP, AU PARAMETER CONDITIONS MIN TYP MAX UNITS LARGE SIGNAL BANDWIDTH ( db) =.Vp-p, C OUT = pf MHz =.Vp-p, C OUT = pf MHz =.Vp-p, C OUT = pf MHz SMALL SIGNAL BANDWIDTH =.Vp-p, C OUT = pf 9 MHz GROUP DELAY TIME ps DIFFERENTIAL GAIN f =.MHz, V IN =.Vp-p VDC = to.7v. % DIFFERENTIAL PHASE f =.MHz, V IN =.Vp-p VDC = to.7v. Degrees GAIN FLATNESS PEAKING =.Vp-p, DC to MHz. db =.Vp-p, DC to MHz.7 db HARMONIC DISTORTION f = MHz, =.Vp-p Second Harmonic dbc Third Harmonic dbc CROSSTALK V IN =.Vp-p AP All Hostile f = MHz, 9 db f = MHz, 77 db Off Isolation f = MHz, 9 db f = MHz, db AU All Hostile f = MHz, 9 db f = MHz, 79 db Off Isolation f = MHz, 9 db f = MHz db RISE/FALL TIME =.Vp-p, Step % to 9% C OUT = pf, R OUT = Ω. ns SLEW RATE =.Vp-p C OUT = pf V/µs C OUT = pf V/µs C OUT = 7pF V/µs

4 CONNECTION DIAGRAM PIN DESCRIPTION Top View SO/DIP PIN IN, IN DESCRIPTION Analog Input Channels IN SEL GND Analog Input Shielding Grounds, Connect to System Ground GND V CC IN 7 V CC SEL SEL, SEL Channel Selection Inputs Analog Output; tracks selected channel V CC Negative Supply Voltage; typical VDC V CC Positive Supply Voltage; typical VDC ABSOLUTE MAXIMUM RATINGS Power Supply Voltage (±V CC )... ±VDC Analog Input Voltage (IN through IN )... ±V CC, ±.7V Operating Temperature... C to C Storage Temperature... C to C Output Current... ±ma Junction Temperature... C Lead Temperature (soldering, s)... C Digital Input Voltages (SEL through SEL )....V to V CC.7V PACKAGE INFORMATION () PACKAGE DRAWING MODEL PACKAGE NUMBER AP -Pin DIP AU -Pin SOIC NOTE: () For detailed drawing and dimension table, please see end of data sheet, or Appendix D of Burr-Brown IC Data Book. ORDERING INFORMATION USA OEM PRICES MODEL DESCRIPTION TEMPERATURE RANGE AP -Pin Plastic DIP C to C $??? $??? $??? AU -Pin SOIC C to C??? DICE INFORMATION 7 PAD FUNCTION Input Ground V Supply Input Select Output 7 V Supply Select Substrate Bias: Negative Supply. NC: No Connection. Wire Bonding: Gold wire bonding is recommended. MECHANICAL INFORMATION MILS (.") MILLIMETERS Die Size x 7 ±. x.9 ±. Die Thickness ±. ±. Min. Pad Size x. x. Backing: Titanium.,.,.,.,.. Gold., ±..7, ±. AD DIE TOPOGRAPHY

5 TYPICAL PERFORMANCE CURVES At V CC = ±VDC, R L = kω, R IN =, R SOURCE = Ω, and T A = C, unless otherwise noted. Input Offset Voltage (mv) INPUT OFFSET VOLTAGE vs TEMPERATURE Temperature ( C) Temperature ( C) Input Bias Current (µa) INPUT BIAS CURRENT vs TEMPERATURE 7 Input Impedance (Ω).M k k k INPUT IMPEDANCE vs FREQUENCY Output Impedance (Ω) 9 7 OUTPUT IMPEDANCE vs FREQUENCY k k M M M G k k M M M G 9 TOTAL POSITIVE QUIESCENT CURRENT vs TEMPERATURE TOTAL POSITIVE QUIESCENT CURRENT vs TEMPERATURE Supply Current (ma) 7 One Channel Selected Temperature ( C) Supply Current (µa) No Channel Selected Temperature ( C)

6 TYPICAL PERFORMANCE CURVES (CONT) At V CC = ±VDC, R L = kω, R IN =, R SOURCE = Ω, and T A = C, unless otherwise noted. Output Voltage (V) TRANSFER FUNCTION Input Voltage (V) Input Voltage (V) Gain Error (%) GAIN ERROR vs INPUT VOLTAGE C C C INPUT VOLTAGE NOISE SPECTRAL DENSITY SWITCHING ENVELOPE (Channel-to-Channel Switching) Voltage Noise (nv/ Hz) SEL.7V V.V k k k M M Time (µs) V IN DB SEL DB SEL SWITCHING TRANSIENTS SWITCHING TRANSIENTS V V V mv Wideband Measurement SEL V mv MHz Low-Pass Filter Acc. Eureka Rec. EU9-PG in MHz Signal Low Path Pass Filter Acc. Eureka Rec. EU9-PG SEL V V mv Time (µs) mv Time (µs)

7 TYPICAL PERFORMANCE CURVES (CONT) At V CC = ±VDC, R L = kω, R IN =, R SOURCE = Ω, and T A = C, unless otherwise noted. SMALL SIGNAL PULSE RESPONSE SMALL SIGNAL PULSE RESPONSE Output Voltage (mv) Output Voltage (mv) Time (ns) V IN =.Vp-p, C OUT = pf t RISE = t FALL = ns (Generator) Time (ns) V IN =.Vp-p, C OUT = 7pF t RISE = t FALL = ns (Generator) LARGE SIGNAL PULSE RESPONSE LARGE SIGNAL PULSE RESPONSE Output Voltage (V) Output Voltage (V) Time (ns) V IN = Vp-p, C OUT = pf t RISE = t FALL = ns (Generator) Time (ns) V IN = Vp-p, C OUT = 7pF t RISE = t FALL = ns (Generator) GROUP DELAY TIME vs FREQUENCY BANDWIDTH vs C OUT WITH RECOMMENDED R OUT Delay Time (ns) Ω Ω DUT BUF V IN Ω pf V IN =.Vp-p M M M G Output (db) C OUT R OUT f db pf Ω 7MHz pf 7Ω MHz pf Ω pf Ω 7pF Ω 79MHz MHz MHz pf pf pf pf 7pF M M M G 7

8 TYPICAL PERFORMANCE CURVES (CONT) At V CC = ±VDC, R L = kω, R IN =, R SOURCE = Ω, and T A = C, unless otherwise noted. GAIN FLATNESS BANDWIDTH vs OUTPUT VOLTAGE Output (db) =.Vp-p =.Vp-p Output (dbm) Vp-p.Vp-p.Vp-p.Vp-p M M M G M M M G BANDWIDTH vs R LOAD BANDWIDTH MATCHING R L = kω Output (db) R L = Ω Output (db) Ch, Ch =.Vp-p, C OUT = pf M M M G C OUT = pf, =.Vp-p M M M G MHz HARMONIC DISTORITION ON/OFF CHARACTERISTIC SEL V Harmonic Distortion (dbc) HPA V IN =.Vp-p G BUFAU Ω 7Ω Advantest DUT RA Ω kω.7v V.7V M M 9M =.Vp-p, R L = kω, C OUT = pf Time (µs) V IN DB SEL DB SEL

9 APPLICATIONS INFORMATION The operates from ±V power supplies (±V maximum). Do not attempt to operate with larger power supply voltages or permanent damage may occur. The buffer outputs are not current-limited or protected. If the output is shorted to ground, currents up to ma could flow. Momentary shorts to ground (a few seconds) should be avoided, but are unlikely to cause permanent damage. INPUT PROTECTION As shown below, all pins on the are internally protected from ESD by a pair of back-to-back reverse-biased diodes to either power supply. These diodes will begin to conduct when the input voltage exceeds either power supply by about.7v. This situation can occur with loss of the amplifier s power supplies while a signal source is still present. The diodes can typically withstand a continuous current of ma without destruction. To insure long term reliability, however, diode current should be externally limited to ma whenever possible. The internal protection diodes are designed to withstand.kv (using Human Body Model) and will provide adequate ESD protection for most normal handling procedures. However, static damage can cause subtle changes in the characteristics of the buffer amplifier input without necessarily destroying the device. In precision buffer amplifiers, such damage may cause a noticeable degradation of offset voltage and drift. Therefore, static protection is strongly recommended when handling the. Static damage has been well-recognized as a problem for MOSFET devices, but any semiconductor device deserves protection from this potentially damaging source. The incorporates on-chip ESD protection diodes as shown in Figure. Thus the user does not need to add external protection diodes, which can add capacitance and degrade AC performance. External Pin FIGURE. Internal ESD Protection. V CC ESD Protection diodes internally connected to all pins. V CC DISCUSSION OF PERFORMANCE Internal Circuitry The is a x, wide-band analog signal multiplexer. It allows the user to connect one of the two inputs (IN /IN ) to the output. The switching speed between two input channels is typically less than ns. However, in contrast to signal switches using CMOS or DMOS transistors, the switching transients were kept very low at mv and mv. The consists of two identical unity-gain buffer amplifiers, respectively connected together internally at the output. The open-loop buffer amps, which consist of complementary emitter followers, apply no feedback so their low-frequency gain is slightly less than unity and somewhat dependent on loading. Unlike devices using MOS bilateral switching elements, the bipolar complementary buffers form a unidirectional transmission path, thus providing high output-to-input isolation. Switching stages compatible to TTL-level digital signals are provided for each buffer to select the input channel. When no channel is selected, the outputs of the device are high-impedance and allow the user to wire several s together to create multichannel switch matrices. Chip select logic is not integrated. The selected design increases the flexibility of address decoding in complex distribution fields, eases BUS-controlled channel selection, simplifies channel selection monitoring for the user, and lowers transient peaks. All of these characteristics make the multiplexer, in effect, a quad switchable high-speed buffer. The buffers require DC coupling and termination resistors when driven directly from a low-impedance cable. Highcurrent output amplifiers are recommended when driving low-impedance transmission lines or inputs. An advanced complementary bipolar process, consisting of pn-junction isolated, high-frequency NPN and PNP transistors, provides wide bandwidth while maintaining low crosstalk and harmonic distortion. The single chip bandwidth of over MHz at an output voltage of.vp-p allows the design of multi-channel crosspoint or distribution fields in HDTV-quality with an overall system bandwidth of MHz, or in quality for high resolution graphic and imaging systems with MHz system bandwidth. The buffer amplifiers also offer low differential gain (.%) and phase (. ) errors. These parameters are essential for video applications and demonstrate how well the signal path maintains a constant small-signal gain and phase for the low-level color subcarrier at.mhz (PAL) or.mhz (NSTC) as the luminance signal is ramped through its specified range. The bipolar construction also ensures that the input impedance remains high and constant between ON and OFF states. The ON/OFF input capacitance ratio is near unity, and does not vary with power supply voltage variations. The low output capacitance of.pf when no channel is selected is a very important parameter for large distribution fields. Each parallel output capacitance is an additional load and reduces the overall system bandwidth. Bipolar video crosspoint switches are virtually glitch-free when compared to signal switches using CMOS or DMOS devices. The operates with a fast make-beforebreak switching action to keep the output switching transients small and short. Switching from one channel to another causes the signal to mix at the output for a short time, but it hardly interferes with the input signals. The transient peaks remain less than mv and mv. The generated output transients are extremely small, so DC clamping during switching between channels is unnecessary. DC clamping during the switching dead time is re- 9

10 quired to avoid synchronization by large negative output glitches in subsequent equipment. The SEL-to-channel-ON time is typically ns and always shorter than the typical SEL-to-channel-OFF time of ns. In the worst case, an ON/OFF margin of ns ensures safe switching even for timing spreads in the digital control latches. The short interchannel switching time of ns allows channel change during the vertical blanking time, even in high-resolution graphic or broadcast systems. As shown in the typical performance curves, the signal envelope during transition from one channel to another rises and falls symmetrically and shows less overshooting and DC settling effects. Power consumption is a serious problem when designing large crosspoint fields with high component density. Most of the buffer amplifiers are in the off-state. One important design goal was to attain low off-state quiescent current when no channel is selected. The low supply current of ±µa when no channel is selected and ±.ma when one channel is selected, as well as the reduced ±V supply voltage, conserves power, simplifies the power supply design, and results in cooler, more reliable operation. CIRCUIT LAYOUT The high-frequency performance of the can be greatly affected by the physical layout of the circuit. The following tips are offered as suggestions, not as absolutes. Oscillations, ringing, poor bandwidth and settling, higher crosstalk, and peaking are all typical problems which plague high-speed components when they are used incorrectly. Bypass power supplies very close to the device pins. Use tantalum chip capacitors (approximately.µf), a parallel 7pF ceramic chip capacitor may be added if desired. Surface-mount types are recommended due to their low lead inductance. PC board traces for signal and power lines should be wide to reduce impedance or inductance. Make short and low inductance traces. The entire physical circuit should be as small as possible. Use a low-impedance ground plane on the component side to ensure that low-impedance ground is available throughout the layout. Grounded traces between the input traces are essential to achieve high interchannel crosstalk rejection. Do not extend the ground plane under high-impedance nodes sensitive to stray capacitances, such as the buffer s input terminals. Sockets are not recommended, because they add significant inductance and parasitic capacitance. If sockets must be used, consider using zero-profile solderless sockets. Use low-inductance and surface-mounted components. Circuits using all surface mount components with the will offer the best AC-performance. A resistor ( to Ω) in series with the input of the buffers may help to reduce peaking. Place the resistor as close as possible to the pin. Plug-in prototype boards and wire-wrap boards will not function well. A clean layout using RF techniques is essential there are no shortcuts. SEL () IN () DB GND () V CC = V () () SEL IN () DB () (7) V CC = V FIGURE. Simplified Circuit Diagram.

11 R IN IN DB SEL Ω Ω R IN IN DB SEL CHANNEL SEL SEL IN IN R IN R IN DB GND V IN Ω DB V IN GND Ω FIGURE. All Hostile Crosstalk Test Circuit. Ω V IN DB SEL IN Ω Ω Ω IN DB SEL SEL SEL FIGURE. Off Isolation Crosstalk Test Circuit. Interchannel Crosstalk (db) AP AU Off Isolation Crosstalk (db) AP AU k M M M G k M M M G FIGURE. Interchannel Crosstalk. FIGURE. Off Isolation Crosstalk.

12 Ω R IN DUT R OUT Ω BUF R B 7Ω Ω DSO.GHz R S = Ω Ω CH or CH C OUT R IN = Ω Pulse Generator FIGURE 7. Test Circuit Pulse Response. Generator R S =.MHz R IN DUT CH or CH Ω R OUT kω OPA 9Ω Video Analyzer R IN = VDC 9Ω FIGURE. Test Circuit Differential Gain and Phase. Generator Ω R IN DUT R OUT Ω BUF R B 7Ω Ω Spectrum Analyzer R S = Ω Ω CH or CH C OUT R IN = Ω FIGURE 9. Test Circuit Frequency Response. SER In D 7 Parallel Out HC9 SER Out 7 Parallel Out HC9 SER Out 7 Parallel Out HC9 SER Out Clock STR OE FIGURE. Serial Bus-Controlled Distribution Field.

13 SEL SEL V V.µF.µF In CH nf nf In Ω Ω.µF CH 7.µF 7 OPA 99Ω 99Ω R S Gain = V/V 99Ω -Bit MHz A/D Converter ADC V V FIGURE. High-Speed Data Acquisition System. V S () V S.µF In C V S CH SEL V S C R OUT Out In C V S CH R T 7 SEL NOTE: () V S should be within V to V. FIGURE. Single Supply Operation.

14 V V.µF.µF SEL SEL V, ma 9 In CH Ω 7 B E C CR () to CRT In CH kω Ω Contrast nf B E C.µF.µF OPA Ω V V Ω Ω pf pf NOTE: () Philips Semiconductors. FIGURE. Input Multiplexer for a CRT Output Stage.

15 Channel CH - CH TTL-Select Lines V V.µF.µF Red CH nf nf Red.µF CH 7.µF Ω 7 OPA 9Ω 9Ω Red Out V V V V.µF.µF Green CH nf nf Green.µF CH 7.µF Ω 7 OPA 9Ω 9Ω Green Out V V V V.µF.µF Blue CH nf nf Blue.µF CH 7.µF Ω 7 OPA 9Ω 9Ω Blue Out V V FIGURE. Input Multiplexer for RGB Video Signals.

16 PACKAGE DRAWINGS