Design and Measurement of CMOS RF-DC Energy Harvesting Circuits

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1 Design and Measurement of CMOS RF-DC Energy Harvesting Circuits Murat Eskiyerli, PhD Revolution Semiconductor March 26, 2017

2 Revolution Semiconductor 2/81

3 About Us Revolution Semiconductor is an IC Design Services and IP Company located in Ankara. We are active in: Full custom Analogue, RF and Mixed-Signal IC Design. RTL to GDSII Digital IC Design. Ultra-low power RFIC Intellectual Property. Operational since /81

4 Our Services Mapping system specifications to IP Specifications. System architecture selection and verification. Full-custom analogue/mixed-signal/radio-frequency integrated circuit design and layout. 28nm to 250nm CMOS technologies BiCMOS technologies with f t up to 300 GHz Digital IC design from RTL to GDSII. Analogue and RF IC bench test. 4/81

5 Revolution Semiconductor IP Portfolio Revolution Semiconductor has developed two key pieces of intellectual property: RVS101: ISO c compliant, silicon-proven passive UHF RFID Transponder IC, RVS102: 2.4 GHz ISM band, wide-band, ultra-low power RF transceiver for IoT and WSN markets. 5/81

6 Introduction 6/81

7 RF-DC Rectifiers A fundamental block for RF energy harvesting systems. Two well-known applications: Passive UHF RFID transponders. Wireless charging. This tutorial will exclusively concentrate on CMOS rectifiers for UHF RFID. 7/81

8 What is tutorial about? You are an integrated circuit designer asked to design a rectifier for RF energy harvesting chip. Probably for a passive UHF RFID transponder. RF-DC rectifier design is different: Not small signal RF, nonlinearities are not second-order effects. Timescales between charging behaviour and RF signals are orders of magnitude different. 8/81

9 Why this long tutorial? RF rectifiers are not like most of the other analogue circuits: Too long to simulate when using transient analysis. Too strongly non-linear to use HB analysis. How to determine the input power? How to determine all-important input impedance? Circuit models will not help the design. 9/81

10 What is tutorial not? Not a comprehensive survey of RF-DC rectifiers. Not an thorough analysis of the RF-DC rectifiers. No claim to be the best practice. Not the last word in this field. We present here only the outcome of our own thinking and design practice. 10/81

11 Requirements 11/81

12 Passive UHF RFID Transponders RF power in 850 MHz-950 MHz band. Normally a dedicated RFID reader will supply RF power. Ambient RF energy harvesting is a possibility, but is not as reliable. RFID reader radiated power is strictly regulated: 4 W EIRP in US. 3.8 W EIRP in Europe 12/81

13 Passive RFID Transponder Power Budget Passive UHF RFID chips operate with very small power budgets. Claimed minimum required input RF power When read by the reader < 10 µw. When written by the reader < 100 µw. If V sup = 1 V then I sup 10 µa Reader uses ASK for downlink communications. Incident RF power is interrupted. Including interruptions of power transfer, I sup,ave 10 µa 13/81

14 Power Conversion Efficiency Most important Figure of Merit for RF-DC rectifiers is Power Conversion Efficiency(PCE) Power Conversion Efficiency is ratio of the output DC power to input RF power and is always less than one. P out PCE = P out = < 1 P in P out + P loss Reflected Power P refl is not included in PCE. 14/81

15 RF Rectifier Circuits 15/81

16 UHF RF-DC Rectifier Design A fundamental component of any RF energy harvesting circuit. Traditionally realized with Zener diodes and capacitors. Most CMOS processes don t offer Zener Diodes. CMOS implementations suffer from the relatively high threshold voltages of MOSFETs. 16/81

17 Fundamental Rectifier Circuit The simplest RF-DC rectifier is a diode-capacitor circuit. D1 conducts when V D > V on, V on is the diode turn-on voltage. Assume that V out = t = 0. V in,pk > V on. At every cycle the load capacitor, C L will be charged, until V out = V in,pk V on. 17/81 V in D 1 C L V out

18 Output Transient of Diode-C Rectifier P+/NW (10um x 10um) diode and C L =10 pf. V in,pk =1 868 MHz. V out blue line, running average red line. 18/81

19 Diode-C Rectifier with Load Diode-C rectifier, by itself, is useless. Need to connect it to rest of the circuitry to make use of the rectified RF power. Often, the load presented by the rest of the chip is modelled by a linear resistance. Could be misleading, but sufficient to start the design process. 19/81

20 Rectifier with Load R L =1 kω, C L =10 pf V out =0.16 V. What happened? 20/81 V in D 1 V out C L R L

21 Voltage Doubler For Diode-C rectifier circuit V out V in,pk V on If V supply 1.2 V V in,pk > 2 V. Can we increase the V out any other way? Voltage Doubler (aka Charge Pump) is a solution. 21/81

22 Voltage Doubler Circuit Assume that V out = t = 0. When V in < V on D1 is on, D2 is off. C c is charged to V in,pk V on. When V in > V on D1 is off, D2 is on. C c shares charge with C L. C L is finally charged to V out,final = 2 V in,pk 2 V on 22/81 C c D 1 A V in D 2 C L V out

23 Problems with Voltage Doubler V in > V on condition should be satisfied. On-chip diodes have relatively high V on 0.6 V. It is inherently a single-ended design. RFID tag antenna has a differential topology. Has to fit differential antenna output to the single Voltage Doubler input. An idea: What if the rectifier circuit had differential inputs as well? 23/81

24 CMOS Differential Rectifier Circuit Design 24/81

25 Reviewing Rectifier Circuit What do the diodes do in the rectifier circuit? They are switches: Their state is determined by the voltage across their terminals. V D > V on = Diode is conducting. V D < V on = Diode is not-conducting. We know even better switches: MOSFETs MOSFETs have a third terminal, gate to control the switching state. 25/81

26 Voltage Doubler with NMOS Transistors Replace all diodes in the voltage doubler circuit with NMOS devices. Check the required gate voltages for the correct operation. C c 26/81 V in M1 G1 G2 M2 C L V out

27 Gate Voltages for NMOS Voltage Doubler C c V in M1 G1 G2 M2 C L V out When V in < 0, M1 on, M2 off. When V in > 0, M1 off, M1 on. V in G1 G2 M1 M2 low high low on off high low high off on 27/81

28 CMOS Voltage Doubler Circuit For NMOS Voltage Doubler circuit, G1 and G2 signals should be opposite polarity. If M2 were to be switched to a PMOS, G1 and G2 could be connected to same node. V in G1 G2 M1 M2 low high high on off high low low off on 28/81

29 CMOS Voltage Doubler Circuit Schematic Final circuit is very similar to a CMOS inverter. The next question: How to generate V cont? V in C c M2 M1 29/81 V cont C L V out

30 CMOS vs. Diode-C Voltage Doublers V DS,M1/2 0 when conducting current. Significant advantage: V on,d > V DS,M1/2 Unlike V on,d, V DS,M1/2 can be optimized by the designer by choosing appropriate aspect ratio. Leakage currents can be problematic in sub-100 nm process technologies. 30/81

31 RFID Antenna and Chip Configuration An RFID tag antenna is a symmetric structure. An RFID chip normally has no ground connection. Chip substrate is in fact floating. One solution: Connect one of the antenna terminals to substrate to create to refer all other on-chip voltages to substrate. How to equalise the parasitics seen by two antenna terminals? 31/81

32 CMOS Differential RF-DC Rectifier Signals at the output of a symmetric antenna are anti-phase. V cont signal could be supplied by anti-phase signal. We can connect outputs of two such rectifiers. C L is now charged at both phases of the input signal. 32/81

33 CMOS Differential RF-DC Rectifier Circuit C c,+ V in,+ M2 M1 2 1 M4 M3 V out C c, V in, R L C L 33/81

34 Positive Feedback Action In steady-state, two inverters are cross-coupled in a positive feedback configuration: 1 st inverter (M1 and M2) 2 nd inverter (M3 and M4) When V in,+ is high, V in, is low: Node 2 V in,pk V DS,1 and node V DS,2 When V in, is high, V in,+ is low: Node 2 V in,pk V DS,2 and node V DS,1 34/81

35 Output Voltage of Differential Rectifier Ignoring the effect of the R L for the moment, the output voltage: V out = 2 V in,p V DS,1 V DS,2 Compare this result to the diode-based Voltage doubler result: Normally V DS V on V out = 2 V in,p 2 V on 35/81

36 Simulation Results 36/81

37 Single Stage Rectifier Design Simulation results for a single-stage rectifier presented. Designs could be further optimized. Device geometries in TSMC 180nm CMOS: M1 M2 M3 M4 W 2 µm 4 µm 2 µm 4 µm L 180 nm 180 nm 180 nm 180 nm 37/81

38 Single Stage Rectifier Design Larger coupling capacitors C c will increase PCE at a cost of larger chip area and higher parastics at the input of the chip. = C c = 0.2 pf If I L = 20 µa and V out = 1 V = R L = 50 kω 38/81

39 Simulation Methods Transient Simulations of the rectifiers could take very long with large C L values. ISO c standard allows up to 1.5 ms for tag start-up. = Up to 1.4 million periods of RF Signal! Shooting-Newton could reduce the simulation duration by thousands! HSPICE-RF was the simulator of choice! 39/81

40 Definition of the Input Power In a typical RFIC design, the input RF power levels are very small, in the range of -130 dbm to -30 dbm. For a typical 50 Ω input impedance, input signal amplitudes would change between 0.1 µv to 10 mv. In UHF RFID tags, the minimum input signal amplitude has to be at least around 0.2 V for the rectifiers to function. Input ports for RFID chips have strongly nonlinear relationship between I in and V in. 40/81

41 Questions to Answer How to define for the P in if the chip input has a strong nonlinear relationship between I in and V in? How to define the input impedance, Z in? How to simulate for the input impedance, Z in? How to measure the input impedance, Z in 41/81

42 Calculation of RF Input Power Need to recognize that Power is an instantaneous quantity. We want to maximize the total energy input of the passive RFID chip! If using the transient simulations, calculate the total input energy over a certain duration ( t T RF ). If using Shooting-Newton simulations, calculate the total input energy over one period (T RF ). 42/81

Typical Waveforms at the input P source =-10 dbm, R source = 376.

43 Typical Waveforms at the input P source =-10 dbm, R source = Ω I inp, V inp, I inp V inp and I inp V inp dτ plotted. E inp = 5.03 fj = P ave = 5.03 fj/1.13 ns = 4.45 µw 43/81

44 Output Voltage vs. Pin Single Stage Differential Rectifier Circuit. f RF = 868 MHz P in between -25 dbm and -4 dbm. Increasing P in from -20 dbm to -10 dbm (10x) increases V out from 0.6 V to 1.2 V. 44/81

45 PCE for a single-stage Increasing P in from -20 dbm to -10 dbm (10x) increases V out from 0.6 V to 1.2 V. For a constant PCE, expected. 45/81

46 PCE Behaviour vs. Pin For a passive UHF RFID tag, P in could change between -20 dbm to -6 dbm = 400x. PCE behaviour at high power levels is not that bad. V out increase with P in less problematic. PCE numbers here for rectifier circuit only. When modulator and demodulator added to the circuit and layout parasitics are accounted for, PCE will drop. 46/81

47 Vgb and Pin V gb < 2 V for safe operation in 180nm CMOS. OK up to around P in =0 dbm = Distance = 2 m 47/81

48 Need for Multi-stage Rectifiers A typical UHF RFID chip requires different voltage supplies when read from and written to: It is a function of the minimum supplies levels that analogue, baseband and memory blocks need: Read Write min max min max 1 V 2 V 1.6 V 2 V 48/81

49 Need for Multi-stage Rectifiers Comparing minimum supply voltages vs. rectifier output voltage plots show that the read and write sensitivities cannot exceed -12 dbm and -5 dbm. Commercially available chips report -20 dbm read sensitivity, 4x better. We need higher V out for same P in. Once again, voltage doubler is to the rescue! 49/81

50 Multi-stage Rectifier Idea We derived CMOS Differential rectifier circuit starting from a Diode-C voltage doubler. What if we kept adding more voltage doublers to the output? The law of diminishing returns apply here as well! 50/81

51 2-Stages Rectifier Circuit V in,+ C c,+ C c,+ M6 M5 M2 M M8 M7 M4 M3 C c, C c, 51/81 V in, C i1 R L C L

52 2-Stages Rectifier Circuit Inter-stage capacitors (C i1 ) filter out the high-frequency noise. V th for M5 and M7 > V th for M1 and M2 due to body effect. For a process with deep n-well option, M5 and M7 can share a deep n-well. Parasitic capacitances between p-well/deep n-well and n-well/substrate reduce PCE. M2/M4 and M6/M8 share n-wells. Further voltage-doubler stages can be added to increase V out further. 52/81

53 PCE for Multi-stage Rectifiers PCE vs. P in for 1,2 and 3-stages rectifiers 53/81

54 Vout for Multi-stage Rectifiers V out vs. P in for 1,2 and 3-stages rectifiers 54/81

55 Observations Multi-stage rectifiers have different characteristics from single-stage rectifiers: Peak PCE is lower and happens at higher P in compared to a single-stage rectifier. At low-end of P in, V out for a multi-stage rectifier is lower than a single-stage rectifier. We need at least 2-stages to be able to write to this RFID tag. 55/81

56 Comparison of Rectifier Circuits CMOS rectifier has higher output voltage, V out. CMOS rectifier is easier to interface with antenna. V gb for CMOS rectifiers can be a problem at high RF input powers = RF limiter at input port. In low RF input powers, CMOS devices work in subthreshold = Carefully check simulator s accuracy settings and models. CMOS rectifiers allow for more design freedom. 56/81

57 Input Impedance Simulations 57/81

58 Input Impedance of RFID Tags RFID chips are not designed for a known Z in. Tag antennas are supposed to be complex-conjugate matched to the input impedance of the chip. Z ant = Z chip How do you define the input impedance of the chip? If the input signals are not small-signals? If the input voltage and current are related in a non-linear manner? 58/81

59 Input Network Model for RFID Chips Z ant = R chip j/(ω o C ant ). V in 120 π L series L shunt Z tag 59/81 Z chip R chip C chip

60 Some numbers for Rin and Cin For a typical UHF RFID transponder chip: R chip between 15 Ω and 25 Ω C chip between 0.8 pf and 2 pf. EM Micro EM4124 NTLAB NT1025B IMPINJ MONZA5 REVSEMI RVS101 R chip Ω Units C chip pf 60/81

61 Determination of Zin from Simulations Z chip changes with P in. A closed-form solution for Z in over wide range of P in is neither possible nor practical. Impedance matching is critical at read sensitivity level. At higher P incident, impedance is increasingly mismatched. 61/81

62 Simulation Setup Set P incident at target read sensitivity level. Determine a range of values for L shunt and L series using likely values for R chip and C chip. Use parameter sweep (or optimization methods) to sweep L shunt and L series values. When P incident P in for a particular pair of L shunt and L series values, it is trivial to determine Z chip. 62/81

63 Sweep Example SN analysis in HSPICE-RF was used. P incident =-12 dbm Final Z in = 2720 j 1440Ω for rectifier and ESD structures only. 63/81

64 Input Impedance Measurements 64/81

65 Background Input impedance measurements at read sensitivity critical for the design of optimum tag antenna. RFID tag chips are normally bonded as flip-chip. Reference plane at flip-chip bumps. Calibration structures to be included in setup. Measurement method as described by Kronberger et al. 65/81

66 Reasoning When P in is below read sensitivity limit, rectifier is drawing very little current. Input impedance is mostly capacitive with a small resistance value. As long as P in < P th = R chip, C chip constant When P in P th, rectifier turns on and load begins to draw current. Phase angle between V in and I in starts to move from π/2 to 0. 66/81

67 V in and I in Simulations V in and I in when P -40 dbm and -17 dbm. 67/81

68 Zin Behaviour When P in reaches the read sensivity limit, the chip begins to draw current. I in, V in constant = Z in R chip exhibits a small dip at read sensitivity limit. Easy to observe in an input power sweep with VNA. 68/81

69 Zin Measurement Board 69/81

70 Test Results NI PXIe-5632 VNA was used to power the chip. 70/81

71 Conclusion 71/81

72 Parting Thoughts In this tutorial, I shared our experience and learnings in UHF RFID rectifier design, simulation and measurements. I hope this tutorial leads to some further avenues of thought on this very critical block in any RF energy harvesting system. 72/81

73 Acknowledgements This tutorial was based on the work done in Revolution Semiconductor. I would like to thank for and acknowledge the work of the following team members: Kursat Akkurt Berk Omuz Alper Karakuzulu Havva Erdinc 73/81

74 Contact Us Website: Phone: Address: Cigdem Cad. 8/36, Dodurga Mah., Ankara Turkey 74/81

75 Appendix 75/81

76 RVS101 UHF RFID Transponder Chip Chip Layout. Response for a typical query sequence. 76/81

77 Range of Incident Input RF Power Distance between RFID readers and tags can vary significantly. Complicates design of RFID rectifer circuits. RF input power incident on the tag could change more than 100-fold. 77/81

78 Diode Reverse Leakage V out,final = V in,pk V on Deviation from our first-order model: V out is oscillating V out,pp 20 mv Cause is the reverse leakage current of Diode I d,leak To reduce V out oscillation Increase C L the chip area. Use diodes with smaller area Higher spreading resistance. 78/81

79 Charge Transfer to the Load We need to look at the total charge Q tot transferred to the output. Q tot = t0 0 i out (τ) dτ This charge will be shared between C L and R L. At steady-state, R L discharges all of this charge over one period. The slope of Q tot vs. time plot equals to V out /R L. 79/81

80 Rectifer Charge Transfer Behaviour Slope of Q tot vs. time I out,av Q/ t V out,final R L I out,av Here, I out,av = 156 µa V out,final V 80/81

81 Transient Simulations Transient simulations can be used to determine the energy transferred to chip in some time interval. 81/81

Long Range Passive RF-ID Tag With UWB Transmitter

Long Range Passive RF-ID Tag With UWB Transmitter Seunghyun Lee Seunghyun Oh Yonghyun Shim seansl@umich.edu austeban@umich.edu yhshim@umich.edu About RF-ID Tag What is a RF-ID Tag? An object for the identification