A HIGH EFFICIENCY RECTIFIER FOR UHF RFID PASSIVE TAGS WITH VTH CANCELLATION TECHNIQUE

Transcription

1 QUID 2017, pp , Special Issue N 1- ISSN: X, Medellín-Colombia A HIGH EFFICIENCY RECTIFIER FOR UHF RFID PASSIVE TAGS WITH VTH CANCELLATION TECHNIQUE (Recibido el Aprobado el ) Rezvan Dastanian Imam Hussein Faculty of Engineering, Behbahan Khatam Alanbia University of Technology, Behbahan, Iran dastanian@bkatu.ac.ir Shabnam Roozitalab Imam Hussein Faculty of Engineering, Behbahan Khatam Alanbia University of Technology, Behbahan, Iran Samsam Izadpanah Imam Hussein Faculty of Engineering, Behbahan Khatam Alanbia University of Technology, Behbahan, Iran Resumen: En este trabajo se propone un rectificador de onda completa de alta sensibilidad y alta potencia para aplicaciones RFID UHF a una frecuencia de 953 MHz. La estructura de acoplamiento cruzado se utiliza en el diseño; También se emplea el circuito de arranque para eliminar el efecto de la tensión umbral de transistores de paso. Con el fin de mejorar la eficiencia de potencia y el área de chip, los tamaños de los transistores se ajustan en frecuencia UHF. En este rectificador la eficiencia energética cambia de 62.7% a 76.1% y la relación de conversión de voltaje cambia de 62.8% a 77.3% para la variación de tensión de entrada de 0.7V a 1.8V. La simulación del rectificador propuesto se hace en tecnología CMOS de 0.18μm con la ayuda del software Cadence, mientras que el área de la viruta es mm2.) Palabras clave: RFID, Ultra-high frequency (UHF), rectificador, Vth cancelación Abstract: In this paper a high sensitivity and high power efficiency full wave rectifier is proposed for UHF RFID applications at 953MHz frequency. The cross-coupled structure is used in the design; also the bootstrap circuit is employed to eliminate the effect of threshold voltage of pass transistors. For the purpose of improving the power efficiency and the chip area, the sizes of transistors are adjusted in UHF frequency. In this rectifier the power efficiency changes from 62.7% to 76.1% and the voltage conversion ratio changes from 62.8% to 77.3% for the variation of input voltage from 0.7V to 1.8V. The simulation of the proposed rectifier is done in 0.18µm CMOS technology with the help of Cadence software, while the chip area is mm 2.) Keywords: RFID, Ultra-high frequency (UHF), rectifier, V th cancellation Citar, estilo APA: Dastanian, R., Roozitalab, S., & Izadpanah, S. (2017). A high efficiency rectifier for uhf rfid passive tags with vth cancellation technique. Revista QUID (Special Issue),

2 1. INTRODUCTION RFID technology, which has different applications in industry and science, has been improved recently [1]-[4]. Using passive tag causes the reduction of cost and the increment of lifetime. The required power for passive tag is supplied from the sent wave from the reader. This received power follows friis (1) at free space [5]. λ 2 P rec(d) = P t. G t. G r. η.. L. 4π 2 d 2 (1) where P t is the sent power from the reader, G t is the gain of the reader antenna, G r is the gain of the tag antenna, η is the rectifier efficiency of RFID tag, λ is the wavelength, d is the communication range, and L is the emission loss. For increasing the received power of antenna at free space and increasing the reading range, electromagnetic wave is used at UHF frequency range. Based on the effective isotropic radiated power (EIRP), the reader has to send only 4W power at UHF frequency [6]. As the received power has limitation, the design of high efficiency rectifier at low received power is the important challenge. Figure 1 shows the diagram block of the passive RFID tag. The received wave from tag antenna enters the rectifier after passing through the matching network. The rectifier block converts the received AC voltage to the DC one and provides the required voltage of the tag. Most of the time CMOS Rectifier Bridge or Dickson circuit is used for the design of rectifier. One of the common disadvantages of such rectifiers is the drop voltage of the output because of MOS transistors threshold voltage. The threshold voltage, not only decreases the output voltage, but also reduces the power efficiency. One of the techniques that is used to eliminate the threshold voltage of transistors is the Schottky transistors [7]-[9]. Employing Schottky transistors need more masking processes and also it is not compatible with CMOS standard that culminates in increasing the cost of fabrication. The semi-passive rectifier is proposed in [10] for distributing the battery voltage to the rectifier stages in order to neutralize the effect of threshold voltage of each transistor. In [6] the internal circuit is employed for the purpose of eliminating the threshold voltage to improve the power conversion efficiency. Some of the designs use cross-coupled circuit instead of diode-connected transistor in the rectifier circuit [11]- [13]. In addition the bootstrap circuit for decreasing the effect of threshold voltage of transistors has been presented in [12], while the full wave rectifier, which uses the combination of cross-coupled and bootstrap techniques, has been designed in [13]. The design of the rectifier with MOS transistors in triode region has been shown in [14]. In [15] the dynamic bulk biasing circuit has been presented for the rectifier in order to reducing the leakage current. Multi-stage CMOS Rectifier Demodulator DC Limiter + Voltage Regulator Voltage Reference VDD Modulator Fig. 1. The diagram block of the RFID tag clk data Control Logic Charge pump EEPROM In this paper, the full wave rectifier is proposed for RFID passive tags at UHF frequency with the aim of eliminating the effect of threshold voltage of the pass transistors. The cross-coupled structure is considered for NMOS pass transistors and the capacitor and the transistor is used as the bootstrap circuit for neutralizing the effect of the PMOS pass transistors threshold voltage, which leads to reducing the chip area. This paper is organized as follows: in section 2, the topology and the characteristics of the passive rectifier is evaluated with different techniques for eliminating the threshold voltage. The new structure of the full wave rectifier is presented in section 3 with the complete detail of its circuit. The simulations of the rectifier and the conclusion are presented in section 4 and 5, respectively. 2. THE RECTIFIER TOPOLOGY AND THE EMPLOYED TECHNIQUES FOR ELIMINATING THE THRETHOLD VPLTAGE 2.1. CMOS Bridge Rectifier Figure 2(a) shows the common bridge rectifier with the diode-connected transistor. In each cycle of the input source voltage, the output voltage is about 2V th lower than the amplitude of the input voltage. Therefore the rectifier can t operate properly in low input voltage and it doesn t have the suitable power efficiency. The crosscoupled structure [11] shown in Figure 2(b) can be replaced the NMOS transistors in conventional bridge rectifier. Due to this circuit, in each cycle of the input voltage only one drop threshold voltage is seen at the output voltage which results in the improvement of the efficiency and the increment of the output voltage. Figure 2(c) shows the full cross-coupled structure [16] which is used for PMOS diode-connected transistor. One of the disadvantages of the full cross-coupled structure is the

3 reverse current which flows from the capacitor load to the antenna. the bootstrap circuit and the cross-coupled technique which contributes to ameliorating the power efficiency and the output voltage. Since the PMOS transistors work in dynamic region and their body not always connects to the highest voltage, the dynamic bulk biasing circuit is used to fixes the maximum bulk voltage and decreases the bulk leakage current [17]. Bootstrapping Circuit M5 (a) (b) B5 M7 VCAP CB1 CL RL CB2 B5/6 (c) Fig. 2. Schematics of full-wave rectifiers: (a) Common bridge rectifier, (b) Gate cross-coupled and (c) Fully cross-coupled [16] Bootstrap Circuit In order to increase the output voltage and the power efficiency of the rectifier, the effect of the threshold voltage should be decreased. This aim can be gained by the bootstrap capacitor. Figure 3(a) shows the simple half wave rectifier and Figure 3(b) shows the half wave rectifier which uses the bootstrap circuit for neutralizing the effect of the threshold voltage [12]. D1 C R D1 VCAP CB ( a) (b) D2 CLOAD Fig. 3. (a) Passive half-wave rectifier and (b) Half-wave rectifier which uses the bootstrap circuit [12] The Full Wave Rectifier with the Bootstrap Circuit and Cross-Coupled Structure The full wave rectifier, which is used for the purpose of eliminating the effect of the threshold voltage, is shown in Figure 4(a) [13]. This structure uses the combination of RLOAD B6 M6 Bootstrapping Circuit (a) /- Fig. 4. (a) Schematic of full-wave rectifier uses the combination of the bootstrap circuit and the crosscoupled technique [13] (b) Schematic of its dynamic bulk biasing circuit for diode- connected transistors of M5-6 [17]. 3. THE PROPOSED RECTIFIER This paper proposes the full wave rectifier, which uses the combination of the cross-coupled structure with the bootstrap circuit at 953MHz frequency, to ameliorate the power efficiency. Figure 5 shows the proposed rectifier. In this circuit, M 1-4 transistors are replaced the diodeconnected transistors of the conventional bridge rectifier and conduct the current path from the input source to the output load. M 1 and M 2 transistors have the cross-coupled structure to have the lower channel resistivity at their activation time [11]. For improving the efficiency and the output voltage, the bootstrap circuit is employed to cancellation the threshold voltage of PMOS pass transistors. M 7 transistor with C B capacitor creates the bootstrap circuit. In this topology, the gates of M 3 and M 4 transistors are connected to each other and M 7, the diodeconnected transistor, which is inserted between the gate of these transistors and the output, can diminish the effect of the threshold voltage of M 3 and M 4, PMOS pass transistors. First, the current of the input source charges the output capacitor and C B capacitor by M 5 and M 6, the diode- connected transistors. The voltage of C B can be suitable for the complete conductivity of the PMOS pass transistors. For reducing the leakage current, the sizes of M8 (b)

4 M 5 and M 6 transistors are selected lower than those of pass transistors. M5 M8 Bootstraped Circuit M9 CB VB M7 0 M 2 1 CL RL M6 Fig. 5. Schematic of the proposed full-wave rectifier In the positive half cycle, when the input voltage (V IN+) is larger than the output voltage, the current charges the output capacitor by M 5, the diode connected transistor. The voltage of output capacitor and C B capacitor is calculated as (2) and (3). V OUT = V IN V th5 (2) V B = V OUT V th7 = V IN V th5 V th7 (3) The voltage of V B can activate the transistor M 3 to simultaneously charge the output capacitor with M 5 transistor. The voltage of V SG() is achieved from (4). V SG, = V IN V B (4) In (5), the transistor M 3 is deactivated when V SG() equals to its threshold voltage. V IN V B = V th3 (5) By using (3) in (5), the output voltage can be calculated from (6). V OUT = V IN ( V th3 V th7 ) (6) Therefore, if V th3 = V th7, the output capacitor charges to the equal value to the input voltage. The PMOS diode-connected transistors, M 5 and M 6, which work in dynamic region, have the bulk terminal that doesn t have connected to the highest voltage during one complete cycle. This problem causes the increasing of the bulk leakage current and the threshold voltage of the diode-connected transistors. To eliminate the body effect of M 5 and M 6, the bulk biasing circuit (M 8-M 11) is used. Since the effect of M 3 and M 4 threshold voltage is neutralized by the bootstrap circuit, the bulk biasing circuit doesn t use for M 3 and M 4, in order to have the maximum output voltage. Thus the body of such transistors is connected to V OUT. To reduce the parasitic capacitors of pass transistors at the operation frequency, 953MHz, and providing the required current for the output load, the sizes of pass transistors M 1-4 should be optimized. The widths of auxiliary transistors M 5 and M 6, which charge the output capacitors and C B capacitor at the first moment, should be selected minimum to decrease the leakage current of this path. In addition the sizes of biasing circuit transistors should have the minimum value. 4. SIMULATION RESULTS The proposed rectifier is simulated at 953MHz frequency with the input voltage varying from 0.7V to 1.8V, 10KΩ output load and 1pF capacitor load. The simulation is done in 0.18µm CMOS technology with Cadence software. By increasing the widths of pass transistors, the load current is increased, but the leakage currents and the loss are increased too which culminates in the reduction of power efficiency. Therefore for improving the power efficiency and decreasing the chip area, the sizes of transistors are set at UHF frequency. The sizes of transistors of the proposed rectifier are presented in Table 1 and the value of CB is considered 3pF.

5 PCE (%) PCE (%) Output Voltage (V) \ Table 1. Summary of transistor sizes Transistor W/L (µm/µm) Multiply Factor Transistor W/L (µm/µm) Multiply Factor 12/ M7 0.22/ / M8 0.22/ / M9 0.22/ / / M5 0.6/ / M6 0.6/ The power conversion efficiency and the voltage conversion ratio can be calculated by (7) and (9). PCE = P OUT(DC) = V2 OUT P IN(RF) R L P IN(RF) (7) where, T P IN(RF) = 1 T V IN(t) I IN (t)dt 0 (8) VCE = V OUT(average) V IN (9) The power efficiency versus the input voltage is shown in Figure 6. The power efficiency is 71.1% at 1.2V input voltage. As it is clear, by increasing the input voltage, the power efficiency is increased Input Voltage (V) Fig. 6. Simulated power conversion efficiency versus input peak amplitude. Figure 7 shows the DC output voltage versus the input voltage. The variation of output voltage is almost linear related to the input voltage. The value of VCE is 73.7% at 953MHz frequency and 1.2V input voltage Input Voltage (V) Fig. 7. Simulated output DC voltage versus input peak amplitude. The power efficiency versus the frequency of the input source is shown in Figure 8. By increasing the source frequency, the parasitic resistor of the transistors is increased which leads to the energy loss and reduction of the power efficiency Frequency (GHz) Fig. 8. Simulated power conversion efficiency versus variation in input frequency. The output voltage related to the time is shown in Figure 9. By considering 1.2V for the input voltage, the DC output voltage and the output voltage ripple are 0.885V and ±18mV, respectively.

6 75µm 1.0 (V) (mv) -/Vout Time (us) µm Time (us) Fig. 9. The output voltage of the proposed Full-wave Rectifier. Figure 10 shows the chip area of the proposed rectifier which equals to 75 70μm 2 in 0.18µm CMOS technology. Table 2 compares the proposed rectifier with the other rectifiers. At UHF frequency, the proposed rectifier has the maximum power efficiency and maximum sensitivity, while its chip area is very low C B Fig. 10. The layout of the proposed full-wave rectifier drawn in cadence software.. Table 2. Performance comparison between proposed rectifier and previous work This Work [6] [19] [18] Process [μm] Freq[MHz] Pin [dbm] -15 to Vout [V] 0.44 to R L [Ω], C L[pF] 10, , 1 ɳ[%] 62.7 to Area [μm 2 ] CONCLUTION In this paper the full wave rectifier is proposed with the aim of eliminating the effect of threshold voltage of the pass transistors for the RFID passive tag. In the designed rectifier the cross coupled structure is considered for NMOS pass transistors and the bootstrap circuit is used for cancellation the effect of threshold voltage of PMOS pass transistors. Also the dynamic bulk biasing is employed for the auxiliary transistors. The rectifier is simulated in 0.18µm CMOS technology and its chip area is mm 2. At 953MHz operation frequency for 1.2V input voltage and 10KΩ load, the power efficiency and voltage conversion efficiency of the proposed rectifier are 71.1% and 73.7%, respectively. REFERENCES [1] S. Han, H. S. Lim, and J. M. Lee (2007). An efficient localization scheme for a differential-driving mobile robot based on RFID system. IEEE Trans. Ind. Electron., vol. 54, no. 6, pp

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