A Low Start up Voltage Charge Pump for Thermoelectric Energy Scavenging

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1 A Low Start up Voltage harge Pump for Thermoelectric Energy Scavenging S. Abdelaziz, A. Emira, A. G. Radwan, A. N. Mohieldin, A. M. Soliman Faculty of Engineering, airo University Abstract In this paper, an ultra-low-voltage charge pump is presented. Two techniques are used to reduce required number of stages and improve power efficiency, namely clock boosting and V t cancellation. lock boosting is employed to increase the output voltage per stage resulting in lower number of stages, and hence smaller output resistance. V t cancellation is achieved by using an auxiliary circuit that enables the charge pump to operate at input voltages as low as 3mV. ompared to conventional charge pump techniques, the proposed technique is shown to offer higher power efficiency and voltage gain. The charge pump is designed using TSM.25µm MOS technology. I. INTRODUTION Thermoelectric generator (TEG) is a device that converts the temperature difference across it into electrical energy [1]. Due to its small size and working autonomous ability, the TEG device can be used in many portable applications such attachable medical devices, electronic wrist watches, self powered heat sensors and Blue tooth headsets. In certain applications, such as body area network, the temperature difference across the TEG is only a few degrees so the TEG s open-circuit voltage is in the range of millivolts [2]. To obtain a higher output voltage, a large number of TEG elements must be connected thermally in parallel, but electrically in series, resulting in larger and more expensive solution. Another practical alternative is use a low-start up voltage charge pump to boost the output voltage. harge pumps are widely used in this purpose to increase the TEG s output voltage to a suitable voltage that can supply the standard integrated circuit. In this paper, a low-start up voltage charge pump which can operate with input voltages as low as 3mV. This is achieved using special techniques such as clock boosting and V t cancellation. Section II describes old architectures used to design low voltage charge pumps.the proposed charge pump is presented in section III. Simulation results are presented in section IV. MD1 MD2 MD3 MD4 MD5 Figure 1. Dickson harge Pump f II. ONVENTIONAL ARHITETURES One of most commonly used voltage multipliers is Dickson harge pump [3] in which diode-connected NMOS is used as charge transfer device as shown in Fig. 1. The voltage gain of each stage in Dickson charge pump, which is defined as the difference between the output and input voltages of this stage, is given by: G v = V V tn (1) where V tn is the threshold voltage of the diode-connected NMOS modified by the body effect due to source voltage increasing at each stage. V is the voltage fluctuation at each pumping node and is given by I o V = V φ + s f ( + s ) where is the pumping capacitance, s is the parasitic capacitance, I o is the output current, V φ is the clock amplitude and f is the clock frequency. As noticed from (2), at no D load current and if s is small enough then V V φ =. According to (1), V, and hence the minimum is set by the condition: (2) > V tn (3) to obtain a positive voltage step in each stage. Therefore, Dickson charge pump is not suitable for low-voltage applications. Many modifications to the Dickson charge pump have been proposed to enable it to operate at low input voltage levels [4, 5]. In [4] for example, the diode voltage drop is eliminated by using charge transfer switch (TS) in parallel with the diode connected device in order to improve the performance in low voltage applications. Static and dynamic TS techniques have been proposed in [4]. TS is used instead of the diodes to transfer the charge between nodes. While the diodes are used only for setting up the initial voltage at each pumping node. The steady state voltage pumping gain per stage can be now expressed as G v = V (4) As shown in Fig. 2, static TS technique uses the next stage higher voltage as a static control for the TS s. The operation is as follows, when φ 1 is high and φ 2 is low, MD2 will be /11/$ IEEE 71

2 V1+ΔV V2+ΔV V2 V3+ΔV V3 V1 MD1 (1) (2) (3) MD2 MD3 MD4 MDO f 1 2 M M 2 V 1 MS1 MS2 MS3 MS4 MD5 V out M 1 2 M 3 V Figure 2. Static TS harge Pump turned ON to set the initial voltage at node 2. The gate-tosource voltage of MS2 is 2 V, if 2 V > V tn then MS2 is ON where V tn is the threshold voltage of NMOS. In the next half cycle, φ 1 is low and φ 2 is high, MD2 will be turned OFF and the gate-to-source voltage of MS2 is 2 V. MS2 will be turned OFF only if 2 V < V tn which is not valid. Although stat is TS achieves higher gain than Dickson as indicated in equation (4), it suffers from reverse charge sharing problem due to incompletely turning OFF of MS2 and this will reduce the efficiency. MN1 V1 V1+ΔV MD1 MS1 MP1 V2+ΔV (1) (2) (3) MN2 MD2 MS2 MP2 V2 MN3 V3+ΔV MD3 MS3 MP3 V3 MN4 MD4 MS4 MP4 MDO f MD5 Figure 4. Pelliconi harge Pump and MS2 will be completely turned OFF. From (5), TS s are difficult to turn ON in low voltage environment. So dynamic TS technique is not effective at low voltage applications. The charge pump proposed by Pelliconi [5] is shown in Fig. 4. The clock amplitude is equal to. After the initial transient, when φ 1 is high and φ 2 is low, V is set to through M 1 and V 1 is charged to 2 and connected to V out through M 2. When φ 1 is low and φ 2 is high, V 1 is set to through M 1 and V is charged to 2 and connected to V out through M 3. So the output be always 2 after first stage. Pelliconi charge pump has many advantages such as eliminating body effect by connecting each device substrate to its source. It also uses very simple clocking scheme and it has no diode-connected MOS so higher gain is achieved (i.e. G v = V = ). The output voltage for N stages can be expressed as: V out = +N /( + s ) I out R out (7) Figure 3. Dynamic TS harge Pump where the output resistance R out can be expressed as: This problem is solved by using dynamic control of the TS s. As shown in Fig. 3, each TS is accompanied by an auxiliary circuit that contains NMOS and PMOS transistors so TS s can be turned off completely in the required period and can be turned on by next stage high voltage as in static TS technique. The operation of dynamic TS technique is explained as follows. When φ 1 is high and φ 2 is low, the source-to-gate voltage of MP2 is 2 V, the gate-to-source voltage of MN2 is zero, and MS2 will be turned ON if: 2 V > V tp &2 V > V tn (5) where V tp is the threshold voltage of PMOS and V tn is the threshold voltage of NMOS. when φ 2 is high and φ 1 is low, MP2 will be turned OFF and MN2 will turned ON If 2 V > V tn (6) R out = Nf/( + s ) (8) omparing with (1), it is clear that Pelliconi is more suitable for low voltage applications. But at very low voltage levels, cascading a large number of stages is necessary to obtain the desired output voltage. For example, to obtain an output voltage of 3.3V from a.3v input, at least nine stages are needed at ideal conditions as indicated in (7). From (8), larger number of stages results in higher output resistance and lower efficiency. III. PROPOSED HARGE PUMP The proposed charge pump is composed of three blocks, the charge pump core, the auxiliary circuit, and the clock booster. The charge pump is based on Pelliconi architecture but the PMOS transistors are replaced with diode-connected NMOS transistors due to their low V t compared to that of the 72

3 V11 MS11 MD11 Mn11 Mp11 22 V21 MS21 MD21 Mn21 Mp21 V31 1 Vin 1 2 V n1 M M 2 Mn12 Mp12 Mn22 Mp22 V V12 MS12 MD12 MD21 21 V22 MS22 MD22 V out M 1 V n2 M 3 Figure 5. Proposed harge Pump PMOS ones. The threshold of the low-v t NMOS transistor in the TSM.25µm MOS technology is slightly less than 2mV, while regular PMOS transistor threshold voltage is around.7v. The threshold voltage drop will limit the performance of Pelliconi especially at low input voltages. To eliminate this drop, an auxiliary circuit is added to each diodeconnected to make it more efficient in transferring charge. Fig. 5 shows two stages of the proposed charge pump with the auxiliary circuit added to each diode-connected and with a clock of 2 amplitude. The auxiliary circuit is composed of 2 NMOS transistors (Ms s and Mn s) and one PMOS (Mp s). The gate of Mp11 is connected to V 12 while its source is connected to V 21 and the gate of Mn11 is connected to V 22 and its source is connected to V 11. The operation of the auxiliary circuit is explained as follows. When φ 1 is low and φ 2 is high (2 ), the voltage at the nodesv 11,V 12,V 21,V 22 andv out1 are3,,5, 3 and 3, respectively. The source-to-gate voltage of Mp11 is 4 and the gate-to -source voltage of Ms11 is 2 so if: 4 > V tp &2 > V tn (9) Then MP11 is turned ON causing MS11 to turn ON also. Mn11 is turned OFF since its gate-to source voltage is zero. When φ 1 is high and φ 2 is low, the voltage at the nodes V 11, V 12, V 21, V 22 and V out1 are, 3, 3, 5 and 3, respectively. The source-to-gate voltage of Mp11 is zero so it will be turned OFF. The gate-to -source voltage of Mn11 is 4. So if: 4 > V tn (1) then Mn11 is turned ON causing MS11 to turned OFF. omparing (9) with (3), (5), the proposed charge pump is more suitable for low voltage applications. The last stage for the proposed charge pump is shown in Fig. 6. The controlling signal for the previous stage already exist at the nodes V n1 Figure 6. 2 Output stage of the proposed charge pump and V n2, so no special output stage is required as in static and dynamic TS techniques. The clock booster circuit shown in Fig. 7 is used to have a clock amplitude of 2. lock boosting main role is to have a swing of 2 at each node. Boosting the clock is a must for the auxiliary circuit to work and it also helps in improving the harge pump performance since using higher clock amplitude will decrease the stage loss due to the diode threshold voltage as mention in [6]. Also by clock boosting higher output voltage can be obtained with fewer stages and this will lead to smaller output equivalent resistance. As a result the efficiency will be improved,the operation of the booster is explained in [6]. IV. SIMULATION RESULTS Simulation is performed using TSM.25µm MOS technology in Spectre R to compare between Pelliconi (in which PMOS transistors are replaced by diode-connected NMOS as indicated in Fig. 8) and our proposed charge pump. To have a fair comparison, the same clock boosting scheme has been used for both circuits with the same value (25pF ) of pumping capacitors. All simulations are performed at a clock frequency of 1MHz. Fig. 9 shows comparison results of output voltage versus number of stages at of.3v and I o = 2.8µA. It is clear from the figure that the proposed charge pump offers about 1% higher output voltage at the same number of stages (e.g. for six stages, the output voltage of the proposed charge pump is 3.4V while it is 2.72V in boosted Pelliconi). The efficiency versus load resistance comparison is shown in Fig. 1. Simulation are done at =.3V and N = 6. The proposed pump maximum efficiency reaches 66% while it is 73

4 N 2b N 2 P 2 1 1b P 1 Figure 9. V out versus N, =.3V, and I o = 2.8µA N 1b N 1 K K b Figure 7. lock booster circuit M1 Vn11 M12 M2 Vn21 M22 M11 Vn12 M13 M21 Vn22 M Figure 1. Efficiency versus R load at =.3V and N = 6 Figure 8. Two-stages of Pelliconi charge pump with all NMOS about 57% in Pelliconi with clock boosting. The comparison results of the output voltage versus input voltage are given in Fig. 11. The proposed charge pump has higher gain than Pelliconi charge pump with clock boosting as shown in the figure. It is clear that the proposed charge pump has the best performance. V. ONLUSIONS A new charge pump is proposed which is suitable for operating at low voltage levels. Two techniques are utilized to improve the performance, namely clock boosting and V t cancellation. The proposed solution is analyzed and simulated against Pelliconi s charge pump. The power efficiency is shown to be 9% higher than Pelliconi s charge pump with the same clock boosting circuit and the output voltage is about 1% higher. The proposed charge pump can operate from input voltage as low as 3mV which makes it suitable for energy harvesting applications. Figure 11. V outversus V in at I o = 5µA and N = 6 REFERENES [1] L. Mateu,. odrea, N. Lucas, M. Pollak, and P. Spies, Energy harvesting for wireless communication systems using thermogenerators, in Proc. of the XXI onference 74

5 on Design of ircuits and Integrated Systems (DIS), Barcelona, Spain, 26. [2] V. Leonov, T. Torfs, P. Fiorini, and. Van Hoof, Thermoelectric converters of human warmth for self-powered wireless sensor nodes, Sensors Journal, IEEE, vol. 7, no. 5, pp , 27. [3] J. Dickson, On-chip high-voltage generation in mnos integrated circuits using an improved voltage multiplier technique, Solid-State ircuits, IEEE Journal of, vol. 11, no. 3, pp , Jun [4] J. Wu and K. hang, MOS charge pumps for low-voltage operation, Solid-State ircuits, IEEE Journal of, vol. 33, no. 4, pp , 22. [5] R. Pelliconi, D. Iezzi, A. Baroni, M. Pasotti, and P. Rolandi, Power efficient charge pump in deep submicron standard MOS technology, Solid-State ircuits, IEEE Journal of, vol. 38, no. 6, pp , 23. [6] F. Pan and T. Samaddar, harge pump circuit design. McGraw-Hill Professional,