SYNCHROPHASOR MEASUREMENT USING SUBSTATION INTELLIGENT ELECTRONIC DEVICES: ALGORITHMS AND TEST METHODOLOGY. A Dissertation JINFENG REN

Transcription

1 SYNCHROPHASOR MEASUREMENT USING SUBSTATION INTELLIGENT ELECTRONIC DEVICES: ALGORITHMS AND TEST METHODOLOGY A Disserttion by JINFENG REN Subitted to the Office of Grdute Studies of Texs A&M University in prtil fulfillent of the requireents for the degree of DOCTOR OF PHILOSOPHY Deceber 0 Mjor Subject: Electricl Engineering

2 Synchrophsor Mesureent Using Substtion Intelligent Electronic Devices: Algoriths nd Test Methodology Copyright 0 Jinfeng Ren

3 SYNCHROPHASOR MEASUREMENT USING SUBSTATION INTELLIGENT ELECTRONIC DEVICES: ALGORITHMS AND TEST METHODOLOGY A Disserttion by JINFENG REN Subitted to the Office of Grdute Studies of Texs A&M University in prtil fulfillent of the requireents for the degree of DOCTOR OF PHILOSOPHY Approved by: Chir of Coittee, Coittee Mebers, Hed of Deprtent, Mlden Kezunovic Grng M. Hung Shnr P. Bhttchryy Willi McCin Lively Costs Georghides Deceber 0 Mjor Subject: Electricl Engineering

4 iii ABSTRACT Synchrophsor Mesureent Using Substtion Intelligent Electronic Devices: Algoriths nd Test Methodology. Deceber 0 Jinfeng Ren, B.S., Xi n Jiotong University, Chin Chir of Advisory Coittee: Dr. Mlden Kezunovic This disserttion studies the perfornce of synchrophsor esureent obtined using substtion Intelligent Electronic Devices IEDs nd proposes new lgoriths nd test ethodology to iprove nd verify their perfornce when used in power syste pplictions. To iprove the dynic perfornce when exposed to sinusoidl wvefor distortions, such s odultion, frequency drift, brupt chnge in gnitude, etc, n dptive pproch for ccurtely estiting phsors while eliinting the effect of vrious trnsient disturbnces on voltges nd currents is proposed. The lgorith pre-nlyzes the wvefor spnning the window of observtion to identify nd loclize the discontinuities which ffect the ccurcy of phsor coputtion. A qudrtic polynoil signl odel is used to iprove the ccurcy of phsor estites during power oscilltions. Extensive experientl results deonstrte the dvntges. This

5 iv lgorith cn lso be used s reference lgorith for testing the perfornce of the devices extrcting synchronized phsor esureents. A novel pproch for estiting the phsor preters, nely frequency, gnitude nd ngle in rel tie bsed on newly constructed recursive wvelet trnsfor is developed. This lgorith is cpble of estiting the phsor preters in qurter cycle of n input signl. It fetures fst response nd chieves high ccurcy over wide rnge of frequency devitions. The signl spling rte nd dt window size cn be selected to eet desirble ppliction requireents, such s fst response, high ccurcy nd low coputtionl burden. In ddition, n pproch for eliinting decying DC coponent, which hs significnt ipct on estiting phsors, is proposed using recursive wvelet trnsfor. This disserttion develops test ethodology nd tools for evluting the confornce to stndrd-define perfornce for synchrophsor esureents. An interleving technique pplied on output phsors cn equivlently increse the reporting rte nd cn precisely depict the trnsient behvior of synchrophsor unit under the step input. A reference phsor estitor is developed nd ipleented. Vrious types of Phsor Mesureent Units PMUs nd PMU-enbled IEDs Intelligent Electronic Devices nd tie synchroniztion options hve been tested ginst the stndrds using the proposed lgorith. Test results deonstrte the effectiveness nd dvntges.

6 v DEDICATION To My Derly Beloved Wife Yping Wng, nd My Prents for Their Love, Ptience nd Support.

7 vi ACKNOWLEDGEMENTS I would lie to express y sincere grtitude to y dvisor, Dr. Mlden Kezunovic, for his support nd guidnce throughout y studies t Texs A&M University. His nowledge nd experience contributed ny of the inspiring ides to this disserttion. I grtefully thn y coittee ebers, Dr. Grng M. Hung, Dr. Shnr P. Bhttchryy nd Dr. Willi McCin Lively, for their tie, coents nd support. Specil thns to Mr. Gerrd N. Stenben, forerly with the Ntionl Institute of Stndrds nd Technology NIST, for his gret help in y reserch, prticulrly during y internship t NIST. Sincere cnowledgeents re extended to y collegues, Mr. Chengzong Png nd other group ebers, for their collbortion nd ssistnce. It ws ost enjoyble experience in y life woring with the. My reserch ws inly funded by two projects. One is fro US DOC, Ntionl Institute of Stndrds nd Technology NIST: Stndrdized Perfornce Test Protocols nd Cpbilities for Phsor Mesureent Units PMUs ; nother is fro NSF I/UCRC Power Syste Engineering Reserch Center PSERC: Verifying Interoperbility nd Appliction Perfornce of PMUs nd PMU-enbled IEDs t the Device nd Syste Level. I would lie to cnowledge the finncil support fro ll the sponsors.

8 vii NOMENCLATURE DC DDR DFR DFT DPR GPS IED IRIG-B NIST PDC PMU PPS PTP TVE UTC Direct Current Digitl Disturbnce Recorder Digitl Fult Recorder Digitl Fourier Trnsfor Digitl Protective Relying Globl Positioning Syste Intelligent Electronic Device Inter Rnge Instruenttion Group Tie Code Fort B Ntionl Institute of Stndrds nd Technology Phsor Dt Concentrtor Phsor Mesureent Unit Pulse per Second Precision Tie Protocol Totl Vector Error Coordinted Universl Tie

9 viii TABLE OF CONTENTS Pge ABSTRACT... iii DEDICATION... v ACKNOWLEDGEMENTS... vi NOMENCLATURE... vii TABLE OF CONTENTS... viii LIST OF FIGURES... xii LIST OF TABLES... xvi. INTRODUCTION.... Proble Stteent..... Synchrophsor Mesureent under Power Syste Trnsients..... Confornce to Stndrd-defined Perfornce Existing Solutions Algoriths nd Techniques Reserch Proble Associted Stndrds nd Guides....3 Reserch Approch....4 Orgniztion of the Disserttion SYNCHROPHASOR TECHNOLOGY FUNDAMENTALS Introduction Synchrophsor Mesureent Concept Devices nd Networ Phsor Mesureent Units Tie Synchroniztion Options Phsor Dt Concentrtors PDCs Synchrophsor Dt Networ Applictions to Power Syste... 3

10 ix Pge.4. Rel-tie Opertions Off-line Applictions Wide-re Controls Sury ADAPTIVE SYNCHROPHASOR ESTIMATOR Introduction Power Syste Trnsients Disturbnce Identifiction nd Locliztion Lipschitz Exponent Wvelet Function nd Trnsfor Coefficient Mesuring Signl Regulrity with Wvelet Trnsfor Modulus Mxi Detection nd Locliztion Step Identifiction with LE Ipleenttion nd Threshold Adptive Phsor Estition Schee Adptive Dt Window Phsor Estition Algorith Study of Model Accurcy Ipleenttion of Adptive Estitor Appliction Studies Power Swing Followed by Three-phse Fult Out of Step Cused by Loss of Lod Sury NEW PHASOR ESTIMATION ALGORITHM Introduction Recursive Wvelet Trnsfor Wvelet Trnsfor Bcground Newly Constructed Recursive Wvelet Frequency nd Phsor Estition Algorith RWT Bsed Frequency nd Phsor Estition Study of Convergence Chrcteristics Anlysis of Coputtionl Burden Eliinting Decying DC Coponent Perfornce Evlution Sttic Test... 94

11 x Pge 4.5. Noise Test Dynic Test Trnsient Test Sury CHARACTERIZING DYNAMIC BEHAVIOR USING STEP SIGNALS Introduction Coputing Reference Phsors Phsor Estition Method Incresing Phsor Output Rte Ipleenttion of Step Test Test Pln Test Procedure Test Results Sury EVALUATING CONFORMANCE PERFORMANCE Introduction Confornce Test References Synchrophsor Test Syste Lbortory Setup Reference PMU Test Results Sury CONCLUSIONS Sury of Achieveents Reserch Contribution Conclusions Suggestions for Future Wor REFERENCES... 4 APPENDIX A APPENDIX B... 60

12 xi Pge APPENDIX C... 6 APPENDIX D VITA... 69

13 xii LIST OF FIGURES Pge Figure Synchrophsor esureents cross North Aeric... Figure Phsor representtion for sinusoidl wvefor [7]... 7 Figure 3 Tie synchroniztion for phsor esureent... 8 Figure 4 Phsor esureent t reote loctions [7]... 9 Figure 5 Errors in phse difference cused by tie sews in esureents [7]... 0 Figure 6 Hrdwre odules of n IED [9]... Figure 7 A typicl PMU instlltion [6]... 3 Figure 8 Tie synchroniztion options... 4 Figure 9 Three levels of PDCs [54]... 8 Figure 0 A bsic synchrophsor networ... 3 Figure Synchrophsor pplictions for difference users... 3 Figure A screen shot of RTDMS for estern interconnection Figure 3 Frequency devitions during lrge genertion outge Figure 4 Moving windows for wvefor with steps in gnitude Figure 5 Evolution of phsor esureents over trnsient period Figure 6 An oscilltion exple nd estited phsors by DFT-bsed lgorith Figure 7 An exple of sinusoidl wvefor contining vrious coponents... 50

14 xiii Pge Figure 8 Singulrities nd their coefficients of wvelet trnsfor cross scles Figure 9 Occurrence of step chnge in dt window Figure 0 Ipleenttion flow chrt for the dptive pproch Figure Voltge wvefor under fult nd power swing condition Figure Preter estites nd errors of three lgoriths t t nd t Figure 3 Current wvefor under out of step condition Figure 4 Estited plitude, phse, frequency nd TVE for three lgoriths... 7 Figure 5 Tie doin wvefors of ψt Figure 6 Frequency doin wvefors of Ψω Figure 7 Flow chrt of the frequency, gnitude nd phse estition Figure 8 Convergence nlysis results Figure 9 Estited frequency error for f =65 Hz Figure 30 Estited TVE for f =65 Hz Figure 3 Sttic test results using qurter cycle dt window Figure 3 Frequency rp test results Figure 33 Dynic response for plitude step Figure 34 Dynic response for phse ngle step Figure 35 Dynic response for frequency step... 98

15 xiv Pge Figure 36 Dynic response for plitude step with pre-filtering Figure 37 Phse-A current wvefor... 0 Figure 38 Exple of the step point t tie stp Figure 39 Exple of the step point between tiestps Figure 40 N sets of output phsors obtined by repeted esureents Figure 4 Interleving of phsors... 0 Figure 4 Output phsors of PMU before interleving... Figure 43 Output phsors of PMU fter interleving... Figure 44 Illustrtion of perfornce indices... 4 Figure 45 Frewor of step test progrs... 6 Figure 46 Illustrtion of perfornce indices... 7 Figure 47 Synchrophsor test nd clibrtion syste... 4 Figure 48 Synchrophsor test syste rchitecture... 5 Figure 49 A screenshot of front pnel for test initiliztion... 7 Figure 50 A screenshot of front pnel for dt trnsfer... 7 Figure 5 A screenshot of front pnel for phsor lignent... 8 Figure 5 A screenshot of front pnel for error nlysis... 9 Figure 53 Phse copenstion for phsor esureents... 30

16 xv Pge Figure 54 Digr for perforing confornce tests... 3 Figure 55 Results of gnitude test... 6 Figure 56 Results of phse test Figure 57 Results of recovery gnitude test Figure 58 Results of recovery phse test... 65

17 xvi LIST OF TABLES Pge Tble Specific functions nd their Lipschitz exponents... 5 Tble Rtios of wvelet trnsfor odulus xi nd LEs Tble 3 Results for ccurcy studies Tble 4 Test results for noise tests Tble 5 Test results for odultion tests Tble 6 Test results for decying DC offset... 0 Tble 7 Feture sury of PMUs being tested... Tble 8 Description of test types nd conditions... 3 Tble 9 Test signl odels for confornce test... Tble 0 Test scenrios for stedy stte condition... Tble Test scenrios for bndwidth condition... Tble Test scenrios for step chnge condition... Tble 3 Test scenrios for frequency rp condition... 3 Tble 4 Test signl odels for ccurcy study... 3 Tble 5 Results of reference lgorith ccurcy study... 3 Tble 6 Perfornce indices of gnitude tests Tble 7 Perfornce indices of phse tests... 64

18 xvii Pge Tble 8 Perfornce indices of recovery gnitude tests Tble 9 Perfornce indices of recovery phse tests Tble 0 Configurtions for PMUs nd PMU-enbled IEDs Tble Confornce test result: stedy stte test Tble Confornce test result: dynic stte test... 68

19 . INTRODUCTION. Proble Stteent.. Synchrophsor Mesureent under Power Syste Trnsients The synchrophsor esureent technology hs exhibited gret superiority in enhncing syste situtionl wreness since it ws developed nd introduced into power syste in the erly eighties []-[3]. Its vlue ws reinforced fter the August 4, 003 blcout [4] where vilbility of such esureents could hve prevented the blcout. In the lst few yers the effort of deploying nd deonstrting vriety of pplictions tht cn benefit fro synchronized esureents, prticulrly in wide re onitoring, protection nd control, hs been ccelerted through the North Aericn Synchrophsor Inititive NASPI nd other relted industry efforts. Figure shows n exple of the synchrohsor esureents vilble cross the North Aeric due to recently instlled PMU or PMU-enbled units. Electric power syste is one the ost coplex systes which suffers vrious disturbnces ll the tie. Relying on different types of control nd protective functions the syste cn rein stble conditions during such dynic chnges. Soe This disserttion follows the style of IEEE Trnsctions on Power Delivery.

20 disturbnces, for exple fults nd switching opertions, produce discontinuous points such s steps nd rps in voltge nd current wvefors due to electrognetic trnsients. The effect of these trnsients lso introduces high frequency coponents in voltge nd current signls. Typiclly PMU genertes phsor esureents t certin rte, i.e. reporting rte [5], nd perfors phsor estition over one cycle of Figure Synchrophsor esureents cross North Aeric noinl power frequency. The discontinuities in wvefors cused by the trnsient steps y occur within n observed dt window. In this cse ccurcy of the phsor

21 3 output estited over such dt window is ffected by discontinuities, nd it cn represent ccurtely neither the pre-stte before the discontinuous point nor the post-stte fter tht point. A power swing y occur in power syste when blnce between the power genertion nd consuption is lost becuse of fult, line switching, genertion tripping, loss of lod or other syste disturbnces. This phenoenon in power syste cn be ctegorized s n electroechnicl trnsient becuse it typiclly involves the rotor oveent of lrge electric chines. During power swing the plitude nd phse ngle of the voltge nd current re odulted with low frequency which corresponds to the devition of rotting speed ong genertors. Vrious exples of power swings observed in prctice cn be found in technicl report [6]. Fourier filter bsed phsor estition lgoriths, which hve been predointely used in PMUs, hve difficulties in processing dynic sinusoidl wvefor distortions, such s odultion, frequency drift, brupt chnge in gnitude, nd decying DCs. Thus, the pproches for chieving better perfornce under trnsients, ccurtely estiting phsors while eliinting the effect of vrious trnsient disturbnces on voltges nd currents re highly desired. Such lgoriths y help to iprove the perfornce of synchrophsor bsed pplictions.

22 4.. Confornce to Stndrd-defined Perfornce As the deployent of the Srt Grid progrs is underwy, new pplictions using synchronized phsor esureents for enhncing the power grid relibility nd security becoe n iportnt prt of the overll power syste opertion [7]. The Aericn Recovery nd Reinvestent Act ARRA funding nd other unrelted infrstructure investent plns in the utility business ccelerte the deployent of PMUs dedicted high precision recording instruents nd PMU-cpble IEDs such s DFRs, DPRs, nd DDRs, etc. tht hve phsor esureent function cpbility cross the North Aericn power grids. While the nuber of PMUs cross the USA utility networs is estited t 50, the nuber of PMU-enbled IEDs y rnge in thousnds. With the recent investents through the ARRA nd other funding sources, the totl nuber of PMUs nd PMU-enbled IEDs y increse by n order of gnitude with tens of thousnds of such units being instlled or enbled in the next 5-0 yers. This sset will require costly solutions for substtion instlltion, counictions, dt integrtion, nd visuliztion. The totl cost of the overll solution y exceed the cost of individul recording devices by severl orders of gnitude. With instlltion of such costly infrstructure the riss of the sset becoing strnded re rel nd itigting esures need to be put in plce to void such n undesirble disstrous outcoe.

23 5 The existing issue of coplince with stndrds es the riss of the strnded ssets outcoe rel in the synchrophsor technology ipleenttions tht include:. Multi-vendor PMUs nd PMU-enbled IEDs with proprietry fetures; b. Vrious Tie synchroniztion options; c. Mixed PDCs nd couniction networs. While ny efforts hve been de to evlute the sttic nd dynic perfornce of PMUs, the responses to step chnge in gnitude, which is typicl electrognetic phenoenon in electric power syste cused by fults or switching opertions, hve not been discussed erlier. A new stndrd for synchrophsor esureent being blloted by the Power Syste Relying Coittee PSRC specifies the perfornce requireents under dynic conditions. Soe dynic conditions, such s the siultneous odultions in both plitude nd phse, nd frequency rp, hve not been studies s well. A coprehensive test ethodology for evluting the confornce perfornce of the PMUs nd PMU-enbled IEDs ginst the new stndrd is in dend. This type of test requires n ccurte synchrophsor esureent lgorith to be used s reference point in evlutions of such esureents found in different products.. Existing Solutions.. Algoriths nd Techniques As defined by Steinetz [8], sttic sinusoidl wvefor with nown frequency

24 6 cn be represented by its plitude nd ngulr position with respect to n rbitrry tie reference. The Fourier filter, which is widely used in PMUs, cn ccurtely copute phsors for the signls with constnt preters within n observtion intervl [9]. In generl, power syste voltge nd current wvefors re not sttic sinusoids. Insted they contin sustined hronics nd noise. During syste disturbnces, oscilltions, step chnges nd high frequency interferences in the gnitude nd phse ngle y occur becuse of the fults, switching opertions nd electroechnicl trnsients of chine rotors. The Fourier bsed phsor estition lgoriths re derived bsed on the sttic sinusoidl signl odel. As result, significnt lgorith errors re expected when dynic wvefors contining odultion, brupt chnge in gnitude nd/or phse ngle, nd frequency drifts re used s inputs. The PSRC is updting the synchrophsor stndrds with specifiction of dynic requireents for PMUs. This will ccelerte the pplictions in power syste nd enhnce the interoperbility for products fro different vendors. In this context, the interoperbility ens confornce with the stndrd s requireents. Menwhile ny efforts hve been de to iprove the ccurcy of phsors coputtion under trnsient conditions [0]-[4]. A rised cosine filter is proposed in [0]. This filter is ble to obtin ccurte results during plitude odultion. An intuitive wy to iprove the estites for signl oscilltion is to use the polynoil odels in gnitude nd phse ngle,

25 7 insted of constnt vlues, nd then to pproxite the envelope of the chnging wvefor preters within n observtion spn. Bsed on this ide, pper [] proposes second-order Tylor polynoil odel to iprove the esureents under power syste oscilltions. If the preters reflecting the chnging chrcteristics of signls cn be estited, this provides ore infortion to the pplictions trcing the dynic progress copred to the trditionl sttic phsor esureent. Ppers [] nd [3] define the dynic phsor coputtion using ulti-preter odels nd provide copenstion ethod for cnceling the error in the clssicl Fourier lgorith tht rises under dynic conditions. Soe issues regrding ipleenttion of the lgorith in different IEDs re discussed s well. In [4] the phsor esureents under trnsient syste conditions re reviewed looing t the bsic definition, estition rchitecture nd power syste dynic chrcteristics. As discussed in [4], step chnges in the gnitude nd phse ngle becuse of electrognetic trnsients y occur within the coputtion dt window, in which cse, the phsor estite obtined fro tht window y be invlid. This y postpone the response tie of the tie criticl pplictions, nd in worse cse it y cuse wrong protective or control decisions. How to properly solve this issue is not ddressed in the bove efforts. A vriety of techniques for the rel tie estition of power syste frequency hve

26 8 been developed nd evluted in pst two decdes. As n exple, DFT hs been extensively pplied to extrct frequency due to its low coputtion requireent. However, the iplicit dt window in DFT pproch cuses errors when frequency devites fro the noinl vlue [5]. To iprove the perfornce of DFT bsed pproches, soe dptive ethods bsed on feedbc loop by tuning the spling intervl [6], djusting dt window length [7], chnging the noinl frequency used in DFT itertively [5], correcting the gins of orthogonl filters [8] nd tuning the weighted fctor [9] recursively re proposed. Becuse of the inherent liittion in DFT, t lest one cycle of nlyzed signl is required, which hrdly eets the dend of high-speed response for protection schees. A ethod using three consecutive sples of the instntneous input signl is discussed in [0]. The noise nd zero crossing issue y bring lrge errors to this ethod. On the bsis of sttionry signl odel, soe non-liner curve fitting techniques, including extended Kln filter [] nd recursive Lest Squres lgorith [], re dopted to estite fundentl frequency. The ccurcy is only reched in nrrow rnge round noinl frequency due to the trunction of Tylor series expnsions of nonliner ters. Soe rtificil intelligence techniques, such s genetic lgorith [3] nd neurl networs [4] hve been used to chieve precise frequency estition over wide rnge with fst response. Although better perfornce cn be chieved by these optiiztion techniques, the

27 9 ipleenttion lgorith is ore coplex nd intensive in coputtion. Mny techniques hve been proposed to eliinte the ipct of decying DC coponent in phsor estition. A digitl iic filter bsed ethod ws proposed in [5]. This filter fetures high-pss frequency response which results in bringing high frequency noise to the outcoe. It perfors well when its tie constnt tches the tie constnt of the exponentilly decying coponent. Theoreticlly, the decying coponent cn be copletely reoved fro the originl wvefor once its preters cn be obtined. Bsed on this ide, [6], [7] utilize dditionl sples to clculte the preters of the decying coponent. Reference [8] uses the siultneous equtions derived fro the hronics. The effect of dc coponents by DFT is eliinted by using the outputs of even-sple-set nd odd-sple-set [9]. Reference [30] hybridizes the prtil su bsed ethod nd lest squres bsed ethod to estite the dc offsets preters. A new Fourier lgorith nd three siplified lgoriths bsed on Tylor expnsion were proposed to eliinte the decying coponent in [3]. In [3], uthor estites the preters of the decying coponent by using the phse ngle difference between voltge nd current. This ethod requires both voltge nd current inputs. As result, it is not pplicble to the current-bsed protection schees... Reserch Proble With the incresing nuber of the deployent of PMUs ny vendors with their

28 0 PMU cpble devices re copeting in this ret. The perfornce requireents of synchrophsor esureents y differ s per the pplictions requireents [4]. For exple, the power grid onitoring requires phsor esureents with high ccurcy while the protection pplictions require such esureents with fst response. In this cse the perfornce of ech individul device potentilly becoes n essentil spect tht could directly ffect the perfornce of the entire syste. The ris of using such elborte high precision esureent infrstructure requires the substntil support of stndrds nd pproprite testing to ensure coplince nd consistency cross ultiple IED types, s well s future sclbility nd upgrdebility, hence voiding the costly infrstructure becoing strnded sset. Mny efforts hve been de for evluting the perfornce of PMUs. The NIST hs estblished SynchroMetrology Lbortory [33]. Two systes for PMU testing under stedy-stte nd dynic conditions respectively hve been developed in this lbortory [34]-[36]. The NIST stedy-stte clibrtion service tests PMUs for coplince with the preter requireents in IEEE C In the dynic test, odulted signls with vrying gnitude nd frequency re used to investigte PMU s dynic perfornce. These test signls siulte the conditions of vrious power syste dynic oscilltions. While the test environent nd ethodology for PMU testing under both

29 stedy-stte nd dynic conditions hve lredy been studied [33]-[5], the PMU responses to step signl, which is typicl signl in dynic conditions, hve not been discussed erlier. Besides, how to verify the perfornce of PMUs under the siultneous odultions in both plitude nd phse ngle, nd frequency rps hve not been ddressed either...3 Associted Stndrds nd Guides IEEE C stndrd defines synchrophsor esureents used in the power syste pplictions [5]. This stndrd specifies the coplince requireents for PMUs with respect to the phsor gnitude, frequency, phse ngle, hronics distortion, nd out-of-bnd interference. It specifies the ccurcy requireent of PMUs in ters of single error preter, defined s the Totl Vector Error TVE. This error cobines the phse tiing error with the gnitude error. It should be pointed out tht the perfornce requireents described in IEEE C re for stedy-stte tests, in which the test signls re held constnt in gnitude, ngle nd frequency during ech test t vlues found in possible operting stte of power syste. In generl, power syste voltge nd current wvefors re not sttic sinusoids. Insted they contin sustined hronics nd noise. Prticulrly during syste disturbnces, oscilltions nd step chnges in the gnitude nd phse ngles of the wvefors y occur becuse of fults, switching opertions nd electroechnicl

30 trnsients of chine rotors. The woring groups of the PSRC re updting the old stndrd with dding the dynic perfornce requireents. Their tss include two new stndrds: the PC37.8. which specifies the perfornce requireents for the synchrophsor esureent [5]; the PC37.8. which specifies the couniction protocols nd requireents for the synchrophsor esureent [53]. The Perfornce nd Stndrds Ts Te PSTT of the NASPI issued PMU syste testing nd clibrtion guide [54]. This guide describes test environents nd procedures for PMU in coplince with perfornce requireents specified in IEEE C In ddition to the stedy-stte tests, the perfornce requireents of PMUs under dynic conditions re included s well..3 Reserch Approch A bredown of reserch pproch in this disserttion is s follows: Study the chrcteristics of voltge nd current wvefors during power syste trnsients. Anlyze the effect of power syste trnsients on phsor behvior. Bsed on better understnding the fundentl properties of the signls tht need to be onitored, nd corresponding signl processing techniques, define the specific requireents for reference phsor estitor under power syste trnsient. Develop n dptive lgorith to iprove the ccurcy of synchrophsor

31 3 esureents for better trcing dynic trnsients during power syste disturbnces [55]. Utilize wvelet ethod to pre-nlyze the wvefor spnning the window of observtion to identify nd loclize the discontinuities which ffect the ccurcy of phsor coputtion. Detect nd further chrcterize the singulrity of signls using Lipschitz Exponent LE, nd e e iproveent for better resolving the specific ipcts on the esureent rised in power syste. Propose new phsor estition lgorith for rel-tie pplictions feturing better dynic perfornce, cpble of eliinting decying DC coponents, flexible window size nd low coputtion burden [56]-[59]. Conduct reserch bsed on recursive wvelet pproch, which ws introduced in protective relying for long tie. Construct new wvelet function, which is coplex function whose wvelet trnsfor coefficients rel prt nd iginry prt contin both phse nd gnitude infortion of the input signl. Bsed on such pproch, derive the lgorith for estiting the power syste frequency nd synchrophsor. Develop test ethodology for evluting the dynic perfornce of PMUs when exposed to step chnge of input signls [60], [6]. Use the dptive window schee to chieve high ccurcy of reference phsors. Apply n

32 4 interleving technique on output phsors to equivlently increse the reporting rte nd precisely depict the trnsient behvior of PMU under the step input. Perfor four types of tests with blnced nd unblnced three-phse step signls s reference signls to chrcterize the step responses. Develop test pln bsed the dynic test syste to utote step test procedures. Design lbortory setup using NI-PXI syste for perforing the confornce tests on synchrophsor devices. Propose the test ethodology for how to ipleent the tests. Develop reference PMU esureent pproch using proposed phsor estition lgoriths nd test techniques. Conduct the ccurcy study to exhibit the superiority. Test results will be given t the end..4 Orgniztion of the Disserttion The disserttion is orgnized s follows. A bcground of the synchrophsor technology is introduced in Section. Section 3 describes the dptive phsor estition for power syste trnsients using wvelet trnsfor techniques. A new lgorith for estiting power syste frequency, gnitude nd phse while eliinting the ipct of decying DC coponent in rel tie is proposed in Section 4. Section 5 describes test ethod for chrcterizing PMU dynic behvior using step chnge signl. Section 6 describes coprehensive lbortory setup bsed on NI-PXI pltfor for ipleenting reference lgoriths nd evluting the perfornce of synchrophsor

33 5 devices. The conclusions of the disserttion re given in Section 7. References nd Appendices re ttched t the end.

34 6. SYNCHROPHASOR TECHNOLOGY FUNDAMENTALS. Introduction The probles to be resolved in this disserttion re discussed in the previous section, in which ny new concepts nd terinology re involved. This chpter introduces the fundentls of the synchrophsor esureent nd ssocited technology. The techniques for trnsferring synchrophsor dt in the wide re solution nd the pplictions using synchrophsor dt in power syste re described s well. This y help to explin the existing issues presented in the previous section fro nother point of view. In Section., the concept of synchrophsor esureent is introduced [6]. The in coponents, such s PMUs, tie clocs nd PDCs nd their functionlities re described in detil in Section.3. Section.4 presents the pplictions using phsor dt for power syste onitoring, protection nd control to enhnce syste relibility [7].. Synchrophsor Mesureent Concept A phsor is coplex nuber with gnitude nd phse ngle tht is used to represent sinusoidl signl under specific frequency 50 Hz or 60 Hz t specific point of tie. As shown in Figure, the phse ngle is the distnce between the sinusoidl pe of the signl nd specified reference point of tie for exple tie = 0 nd is expressed using n ngulr esure. The phsor gnitude is relted to the

35 7 plitude of the sinusoidl signl. Figure Phsor representtion for sinusoidl wvefor [7] When phsor esureent is tie stped ginst the UTC tie by GPS, it is clled synchrophsor. This llows esureents in different loctions to be synchronized nd tie-ligned, then cobined to provide precise, coprehensive view of n entire region or interconnection. Usully GPS receiver is used to provide UTC tie to synchronize the phsor esureent. GPS receiver provides both PPS nd tie code IRIG-B outputs, s shown in Figure 3. PPS is used to synchronized sples nd djust the locl tie ginst the pulse every second. The deodulted IRIG-B signl which is DC shift pulse chin is siilr to PPS but contins tie code, which cn be

36 8 used to tiestp the esureents directly. Figure 3 Tie synchroniztion for phsor esureent Figure 4 gives n exple of phsors esureent ten t different loctions. With the tie reference the phsor esureents re synchronized, then de coprble. The phse ngle difference between two sets of phsor esureents is independent of the ngle reference. How tie sews in the sple synchroniztion nd subsequently in the synchrophsor esureents nd nlysis process cn induce errors in the phse ngle difference coputtions is shown by Figure 5. Bsiclly the phse ngle difference between two sets of esureents is pproxitely ten degrees. However, when one of these two phse ngle signls is sewed by one second, the coputed phse ngle difference is pproxitely five degrees. This y introduce lrge errors to ppliction results bsed on such esureents.

37 9 Figure 4 Phsor esureent t reote loctions [7] Copred to the trditionl Supervisory Control nd Dt Acquisition Syste SCADA, the synchrophsor technology hs the following dvntges: Phsor technology provides high resolution sub-second tie synchronized dt which is pplicble for wide re onitoring; rel tie dynics nd stbility onitoring; dynic syste rtings to operting power syste closer to the rgin to reduce congestion costs nd incresing sset utiliztion; nd iproveents in stte estition, protection, nd controls. Trditionl SCADA/EMS systes re bsed on stedy stte power flow nlysis, nd therefore cnnot observe the dynic chrcteristics of the power syste

38 0 phsor technology is the MRI qulity of the power systeindustry providing the high sub-second visibility required for observing dynic behvior nd, therefore, overcoing the liittions of the old x-ry qulity visibility tht trditionl SCADA-bsed systes offer. Phsor esureents directly provide the phse ngles t the high sub-second rte. These phse ngles hve trditionlly been obtined fro stte estitors which re inherently slow typiclly every 5-0 seconds nd susceptible to errors due to outdted or inccurte odels required by the stte estition process. Figure 5 Errors in phse difference cused by tie sews in esureents [7]

39 .3 Devices nd Networ.3. Phsor Mesureent Units A PMU is stndlone device tht esures 50/60 Hz AC voltge nd/or current signls to provide phsor nd frequency esureents. The nlog AC wvefors re digitized by n nlog to digitl converter for ech phse nd phse-loc oscilltor nd GPS reference tie source, often clled pulse per second PPS provides high-speed tie synchronized spling. A PMU clcultes line frequency, s well s voltge nd current phsors t high spling rte nd stres those dt, long with the ssocited GPS tie stp, over networed couniction lines. The synchrophsors cn be single phse or syetricl coponent vlues. The synchrophsor esureent functionlity need not be the sole function or purpose of device; for instnce, ny digitl relys hve PMU functionlity but their priry purpose is to serve s rely rther thn s PMU. Any device tht incorportes this functionlity such s digitl fult recorders DFRs nd digitl relys is considered PMU device, i.e. PMU-enbled IED. Other unrelted functions of the device ust be shown not to ffect the perfornce of the PMU coponent, nd eqully iportntly the PMU functions ust not ffect the other functions of the device. The in coponents of PMU or PMU-enbled IED include nlog input signl interfce, dt cquisition syste, phsor estition odule nd post-processing odule for

40 output dt. Figure 6 shows the hrdwre structure of n IED. Ech odule, prticulrly the phsor estition lgorith hs ipct on the ccurcy perfornce. For their use in vrious pplictions, the synchrophsor nd frequency vlues ust eet the generl definition s well s the iniu ccurcy requireents given in stndrds [5], [5] nd [53]. Figure 6 Hrdwre odules of n IED [9] PMUs nd PMU-enbled IEDs re typiclly instlled in substtion or t power plnt. Ech phsor requires three seprte electricl connections one for ech phse, to either esure current fro line or power trnsforer bn or voltge fro either line or bus PTs. A typicl PMU instlltion is shown in Figure 7.

41 3 A PMU lso perfors pre- nd post-processing of the dt collected, including proprietry phsor coputtion lgoriths, nti-lising filtering, nd other signl processing esures. As of tody there re thousnds of DPRs nd DFRs deployed on the US grid tht cn be upgrded to PMU functionlity. These upgrded PMU-enbled IEDs cn be used for high-speed grid onitoring, utoted opertions, forensic nlysis, nd odel clibrtion. A list of IEEE 37.8 coptible, PMU-cpble, upgrdble DFRs nd DFRs ccording to nufcturers clis cn be found t [63]. Figure 7 A typicl PMU instlltion [6].3. Tie Synchroniztion Options A PMU requires source of UTC tie nd high ccurcy tiing signl to provide

42 4 synchronized esureents. According to the IEEE C37.8 stndrd, the ccurcy of synchrophsor esureent shll not exceed % of TVE, which corresponds to phse ngle error of 0.57 degrees. If we only consider the phse ngle error, the error of 0.57 degree corresponds to pproxitely 6 μs t 60 Hz nd 3 μs t 50 Hz. The existing ethods include the direct GPS signl [64], IRIG-B/PPS [65] nd IEEE 588 [66]-[68]. For using direct GPS signl, n IED ust be equipped with GPS receiver for decoding the tie signl. For using IRIG-B nd PPS, the receiver ust be locl to the IEDs. Using IEEE PC37.38 [68], the receiver cn be either locl or reote to the IEDs becuse the tie code defined in IEEE PC37.38 cn be distributed over couniction networ. Figure 8 Tie synchroniztion options GPS signl A direct wy for PMU to refer UTC tie is using GPS signl. Such PMU should be equipped with internl or externl GPS receiver, which is

43 5 specilly designed to receive nd synchronize locl tiing reference to UTC using the GPS signl. The GPS syste is referenced to toic clocs intined by the U.S. ilitry. These clocs re very ccurte tie nd frequency references, nd re intined within nown offset to UTC. A good GPS tie receiver will incorporte verging nd holdover to ccoodte short devitions nd signl dropouts due to tospheric disturbnces nd other cuses. It will lso provide notifiction if it loses loc with the GPS signl, so the synchroniztion sttus is lwys nown to PMUs. IRIG-B/PPS IRIG-B is coonly used by PMUs for synchronizing to UTC tie. It y be provided in level shift, Hz plitude odulted signl, or in the bi-phse Mnchester odulted fort odultion type, Bxx. If the plitude odultion is used, it y need to be suppleented with PPS pulse trin to chieve the required ccurcy. The IRIG-B plitude odulted fort is coonly vilble nd hence is the ost redily ipleented. The newer Mnchester fort is ore coptible with fiber optic nd digitl systes nd provides coplete synchroniztion without dditionl signls. The cloc reference is provided once per second in seconds through dy of yer in binry coded decil BCD fort nd n optionl binry second-of-dy count. A PPS in tiing systes is pulse trin of positive pulses t rte of Hz. The rising

44 6 edge of the pulses coincides with the seconds chnge in the cloc nd provides very precise tie reference. The pulse widths vry fro 5 μs to 0.5 s, nd the signl is usully 5 V plitude driving 50 oh lod. IEEE 588 PTP is protocol used to synchronize distributed clocs with n ccurcy of less thn icrosecond vi Ethernet networs. GPS is highly ccurte solution but does not scle well due to cost nd coplictions of ttching ntenns to every device. Using n Ethernet networ to propgte tiing signls eliintes the extr cbling requireent of GPS nd IRIG-B. The first version of IEEE 588 ws found tht the originl design does not scle well for lrge switched networs. The processing nd trffic congestion cn occur t the tiing ster nd cscded networ switches could cuse inccurcies due to jitter tht occurs s the pcets trverse through the switches. The second genertion solves the probles by. using echniss tht increse ccurcy by ccounting for switching tie nd peer to peer propgtion delys tht occur s the tiing signls trverse the networ; b. using trnsprent clocs in Ethernet switches tht eliinte the need for end-to-end dely esureent, reducing trffic congestion nd eliinting switch jitter. With IEEE 588, the cbling infrstructure requireent is reduced. The convergence of tiing nd dt infortion networs cn be crried out right to the networ edge nd converted

45 7 to IRIG-B for synchroniztion of existing devices tht re not cpble of IEEE 588, llowing the to be ept in service even while updting the tiing nd dt networ infrstructure..3.3 Phsor Dt Concentrtors PDCs A PDC collects phsor dt fro ultiple PMUs or other PDCs, ligns the dt by tie-tg to crete tie-synchronized dtset, nd psses this dtset to other infortion systes. A PDC lso perfors dt qulity checs nd issing flgs or probletic dt witing for set period of tie, if needed, for ll the dt to coe in before sending the ggregted dtset on. Soe PDCs lso store phsor dt nd cn down-sple it so tht phsor dt cn be fed directly to pplictions tht use dt t slower sple rtes, such s SCADA syste. The Perfornce Stndrds Ts Te of NASPI is drfting docuent tht defines the functionl nd perfornce requireents for PDC [69], [70]. The in functions include: Correlte phsor dt by tie tg nd then brodcst the cobined dt to other systes; Confor to streing protocol stndrds e.g., IEEE C37.8 for both the phsor dt inputs nd the cobined dt output stre; Verify the integrity nd copleteness of dt stres fro PMUs nd properly

46 8 hndle dt nolies Buffer input dt stres to ccoodte the differing ties of dt delivery fro ech PMU. The functions of PDC cn vry depending on its role or its loction between the source PMUs nd the higher-level pplictions. There re three levels of PDCs, s shown in Figure 9: Figure 9 Three levels of PDCs [54] Locl PDC nges the collection nd couniction of tie-synchronized dt fro locl PMUs, sends it to higher level concentrtors, nd stores the dt for use within the substtion. A locl PDC y be locted physiclly close to

47 9 PMUs typiclly t substtion nd store sll cche of locl esureents to prevent ginst networ filure, nd should be the source of dt for locl utoted control functions. A locl PDC is generlly hrdwre-bsed device tht should require liited intennce nd cn operte independently if it loses counictions with the rest of the synchrophsor networ. Corporte PDC opertes within control roo where it ggregtes dt fro ultiple PMUs nd PDCs. It ust conduct rel-tie dt qulity checs nd clcultions t very high speed with rel-tie sple rtes currently t sples per second nd heding higher.rel-tie clcultion ust be copleted very quicly, before the next set of vlues rrive. PDCs typiclly utilize threding nd other prllel coputing techniques vilble within odern operting systes to nge ultiple connections t high speeds. PDCs ust be dptble to new protocols nd output forts s well s interfces with dt-using pplictions. PDCs should incorporte inter-utility stndrds to llow for efficient chine-to-chine, progr-to progr-coptibility. It is expected tht the grid opertors tht host PDCs will dend these cpbilities fro PDC vendors, nd tht these cpbilities will be written into specifictions nd tested for effective interoperbility perfornce before cceptnce. Super PDC opertes on regionl scle, hndling phsor esureents fro

48 30 severl hundred PMUs nd ultiple PDCs. It collects nd correltes phsor dt fro reote PDCs nd PMUs nd es the vilble s coherent, tie-synchronized dtset to pplictions such s wide-re onitoring nd visuliztion softwre, energy ngeent systes nd SCADA pplictions. A super-pdc lso feeds the dt into centrl dtbse for long-ter dt rchiving dt historin function. Super-PDCs re softwre ipleenttions, running on instre server hrdwre, s these lrger devices need to scle rpidly to serve growing utility nd regionl deployent of PMUs nd diverse phsor dt pplictions. PDCs re coercilly vilble fro severl vendors. Bsed on their perfornce history, these PDCs re generlly considered to be production-grde systes. Even so, PDCs hve not yet been perfornce-benchred. While it is liely tht the SGIG projects will ccelerte the developent of PDC perfornce nd test stndrds, there re currently no forl stndrds for evluting nd rting PDCs..3.4 Synchrophsor Dt Networ A bsic synchrophsor esureent networ consists of PMUs nd PMU-enbled IEDs, PDCs, gtewys, dt storge nd pplictions, s given in Figure 0. A stndrd for synchrophsor dt trnsfer for power systes hs been initilized by PSRC[53]. It defines the fort of synchrophsor dt nd specifies the requireents of networ for

49 3 dt trnsfer. The functions of PMU nd PDC hve been described in previous sections. Figure 0 A bsic synchrophsor networ.4 Applictions to Power Syste According to the function of power syste pplictions, the synchrophsor bsed pplictions cn be clssified into three ctegories [7]: Applictions to support rel-tie grid opertions by providing wide-re visuliztion nd incresed stte wreness, Applictions to iprove syste plnning nd nlysis, including power syste perfornce bselining, event nlysis nd odel vlidtion, nd Response-bsed control pplictions tht use rel-tie wide re infortion to te utoted control ctions on the power syste. Rel-tie pplictions require rel-tie dt collection nd processing with

50 3 iedite nlysis nd visuliztion or re used s control signls for rel-tie controls pplictions. Plnning nd post-event nlysis pplictions use rchived dt nd the nlysis y be conducted off-line dys or onths fter the dt were collected. Figure surizes the pplictions using synchrophsors for different roles in power syste including the roles of plnners, opertors, reserchers nd relibility coordintors. The rest of this section will briefly introduce principl pplictions groups in ech of three ctegories. Figure Synchrophsor pplictions for difference users

51 33.4. Rel-tie Opertions All rel-tie opertions using phsor dt offer high spling speed, new grnulrity into phse ngles nd other grid conditions, nd tie synchroniztion. These esureent chrcteristics lso enble exceptionl visuliztion, nlytics nd lring ll of which iprove opertors bility to see nd understnd wht is hppening on the bul power syste, nticipte or identify potentil probles, nd identify, evlute, ipleent nd ssess reedil esures. However, phsor pplictions ust synthesize nd surize lrge ounts of phsor dt for opertors, preventing infortion overlod nd presenting ctionble infortion in n esily understndble nner so tht quic nd relible decisions cn be de. Most power syste opertors tody hve very little visibility into power syste dynics such s power oscilltions, voltge stbility indictions, nd syste ngulr stress. Lrge-scle integrtion of renewble resources will present n dditionl chllenge to the syste opertors, s lrge nd fst power chnges by interittent genertors cn drticlly shift genertion ptterns nd operting conditions. Visibility of power syste dynics is becoing even ore criticl s the power syste grows with inclusion of ore vrible resources with less offsetting chine inerti to stbilize the syste. There re severl pplictions for enhncing the wide-re situtionl wreness of

52 34 power grids, such s the synchronized esureent nd nlysis in rel tie SMART tool by Southern Cliforni Edison SCE, rel tie dynic onitoring syste RTDMS nd PowerWorld Retriever. Let us te RTDMS for exple. This softwre is phsor dt-bsed pltfor used by grid opertors, relibility coordintors, nd plnning nd opertions engineers for rel-tie wide-re visuliztion, onitoring nd nlysis of the power syste. RTDMS offers rel-tie dshbord with indictors of ey grid etrics for situtionl wreness. Figure A screen shot of RTDMS for estern interconnection

53 35 Figure shows screen shot of RTDMS for Estern Interconnection fter strt of Florid grid disturbnce [7]. It is ble to identify nd visulize the developent of grid disturbnce, showing the difference in grid conditions. Other rel-tie pplictions such s stte estition, frequency stbility onitoring, power oscilltion detection, voltge onitoring nd opertion plnning re briefly describes s follows: Stte Estition Snpshots of dt fro PMUs cn integrted into n orthogonl stte estitor by feeding PMU esureents e.g., voltge nd current directly into the stte estitor esureent vector nd the Jcobin trix it uses to solve the networ. Alterntively, stte estitor cn use derived PMU esureents of voltge ngle differences nd brnch fctor ngle esureents, thus eliinting the requireent for synchronizing stte estitor nd PMU ngle references. This pproch enbles the stte estitor to clculte the networ solution bsed on both PMU nd conventionl esureents siultneously, with the dvntge tht the phsor dt offer redundnt syste condition esureents nd enble better solution ccurcy.

54 36 Figure 3 Frequency devitions during lrge genertion outge Frequency Stbility Syste frequency is the ey indictor of the lod-resource blnce. The size of the frequency devition is well correlted with the size of genertion loss. Figure 3 shows n exple of frequency response to genertion outge. Syste frequency is lso good indictor of integrity of n interconnection during syste events involving seprtion or islnding. If bus frequency in one prt of the syste stys t 60.5 Hz while frequency in nother prt of the syste holds t 59.5 Hz for severl inutes, it is sure indiction of the syste seprtion. PMU frequency plots provide good indiction of the lost genertion, for n exple, frequency drop of 0. Hz is typicl in the WECC for 800 MW genertion losses. Also, the propgtion of the frequency drop cn

55 37 be used to identify where the genertion drop occurred. Power Oscilltion Detection of power syste oscilltions nd bient grid dping re ong the preier pplictions tht require the high-speed dt tht PMUs provide nd conventionl SCADA does not. Low-frequency oscilltions occur when n individul genertor or group of genertors swing ginst other genertors operting synchronously on the se syste, cused by power trnsfers nd high-speed, utotic turbine controls ttepting to intin n exct frequency. Synchrophsor dt bus frequency, ngles, line loding nd voltge re criticl to detect potentil nd ctul oscilltions within the bul power syste. Inter-re oscilltions cn be seen by exining bus voltges nd frequencies, so ost ethods of oscilltion detection re pplied to the pth or flow gte. Oscilltion detection ethods clculte the dping of ring down during syste disturbnce. The energy of power oscilltions indictes whether n oscilltion is growing or dissipting. A build-up in energy signls growing oscilltory ctivity, nd cn lert n opertor to chec other indictors. Voltge Monitoring Phsor systes cn be used to onitor, predict nd nge frequency nd voltge on the bul power syste. One of the ost proising ner-ter synchrophsor pplictions is for trending syste voltges t ey lod center nd bul trnsission busses. Voltge trending nd voltge

56 38 instbility prediction re highly desirble uses for synchrophsor systes nd high priority for phsor dt pplictions. Mny trnsission systes re voltge stbility-liited, nd voltge collpse cn hppen very quicly if stbility liits re reched. Voltge instbility occurs when either the syste hs indequte rective reserves, or the trnsission syste cnnot deliver rective power fro the source to where it is needed. Monitoring syste voltge using phsor esureents of voltge profile, voltge sensitivities, nd MVr rgins llow opertors to wtch voltge levels in rel-tie, while trending ppliction would provide n erly indiction of voltge instbility vulnerbility. Opertion Plnning Phsor dt offer gret vlue for hour-hed nd dy-hed opertions plnning. These dt cn be used to iprove odels both to refine odels of individul ssets nd groups of ssets e.g., cobustion turbines or wind power plnts to iprove understnding nd representtion of interconnection-wide behvior. Phsor dt snpshots of pst syste conditions cn be used to iprove developent nd nlysis of syste operting conditions under vriety of norl nd potentil contingency operting scenrios. Phsor dt cn lso be used to identify nd dignose odd syste conditions or behviors. For instnce, BPA plnners used phsor dt to identify the fct tht severl of its genertors were operting with their governors utotic controls

57 39 turned off..4. Off-line Applictions The off-line pplictions using synchronized phsor esureents including syste odel vlidtion, event nlysis, specil protection nd islnding, nd bselining syste perfornce. Syste Model Vlidtion Plnners re using phsor dt to iprove sttic syste odels. The high-speed observtions of grid conditions llow odelers to clibrte odels to better understnd syste opertions, identify errors in syste odeling dt or in odel lgoriths, nd fine-tune the odels for online nd off-line pplictions, such s power flow, stbility, short circuit, OPF, security ssessent, odl frequency response, nd ore. Event Anlysis Synchronized wide-re dt is essentil for disturbnce nlysis, s evidenced by the August 4, 003 blcout investigtion [4]. Dt synchroniztion is criticl for the sequence of event reconstruction, prticulrly for coplex events where ny switching opertions occur in short tie fre. Specil Protection nd Islnding Phsor dt cn be used to design nd test specil protection schees SPS nd islnding. Ultitely it y be possible to use rel-tie phsor dt tht revels the loction nd cuses of syste stress to drive utoted control nd execution of specil protection schees, including

58 40 even the rel-tie design nd opertion of syste islnding in the fce of potentil cscde. Bselining Syste Perfornce it identifies nd understnds phse ngles under vriety of syste conditions. To be ost useful nd infortive, these nlyses require extensive records of phsor esureents cross lrge region, covering wide vriety of lods, equipent sttus, nd other syste conditions. Bselining entils using historic grid condition dt to correlte syste perfornce reltive to the esured ngulr seprtion. PMU dt re then used to structure power syste siultions to predict how syste perfornce reltes to the phse ngles under lrge disturbnce events. Idelly, this is done using syste odels tht hve lredy been clibrted nd vlidted with phsor dt to iprove their predictive cpbility..4.3 Wide-re Controls Wide-re synchronized esureents enble unprecedented opportunities for wide-re stbility control pplictions. Wide-re esureents provide uch greter observbility of the syste stte, thereby leding to better nd fster decisions. Since PMU esureents re instntneous nd hve high resolution, phsor dt cn be used to ctivte locl or centrlized control of corrective esures for ngulr stbility, voltge stbility, low-frequency oscilltions nd therl constrints.

59 4 The following prcticl control pplictions, ll requiring high-speed phsor dt, re now under study: Fst Rective Switching Synchronous genertors in voltge control ode nd Sttic Vr Copenstors SVC provide rective power reserves tht cn be deployed during the disturbnces. Studies show strong correltion between the rective rgins on voltge stbility-liited pths nd rective power response nd rective power reserves. Switching shunt in cpcitors cn be done to increse the rective reserves of genertors nd SVCs. Coordinted Secondry Voltge Control It is not uncoon to hve severl rective power resources in electricl proxiity to ech other. Coordintion of voltge set-points is often required to ensure tht pproprite rective power reserves re intined with equitble rective shring through secondry voltge controls. Synchrophsors or SCADA cn be used for slow loop control, but with lrge-scle wind integrtion, there is greter need for fst coordintion of voltge schedules ong clustered wind power plnts nd switched cpcitors to intin dynic rective reserves. Inter-Are Oscilltion Dping Controls Wide-re oscilltions cn be dpened using utoted controls, but this requires high-speed dt nd observbility such s tht offered by synchrophsor syste. After excessive

60 4 oscilltory ctivity ws observed during the 006 suer het wve, western grid opertors re revisiting the fesibility of oscilltion dping controls fcilitted by phsor dt [7]. Equilibriu Stte Control The power syste ust hve stble equilibriu trget stte to return to following disturbnce event. The ore secure the trget stte, the ore liely the syste trnsient oscilltion will be dped nd the less strong oscilltion control will be needed. In effect, the networ nd trnsfer dends re brought into blnce to ssure tht there is stble equilibriu power flow condition. Phsor-driven wide-re controls hs been populr reserch topic in the lst decde, including response-bsed Syste Integrity Protection Schee SIPS nd inter-re oscilltion dping for dptive islnding. Yet very few control pplictions re now in use. This is the lest ture set of pplictions, lthough it offers gret benefit for grid relibility..5 Sury Phsor is n equivlent representtion of sinusoidl wvefor. With ngle reference nd globl tie synchroniztion the synchronized phsor esureents re widely used to reflect the operting sttus of power grid; Vrious PMUs nd PMU-enbled IEDs provide synchrophsor esureent

61 43 with different ccurcy perfornce. IEDs cn be synchronized using different options, such s GPS, IRIG-B/PPS nd IEEE PC37.38, which provide vrint levels of ccurcy. In synchrophsor solution, PMUs y be fro different vendors using different tie synchroniztion options nd connected through different PDCs. This y cuse interoperbility issues. Power syste pplictions using synchrophsor esureent hve different requireents in ccurcy nd response. The qulity of synchrophsor esureent hs direct ipct on the ppliction perfornce.

62 44 3. ADAPTIVE SYNCHROPHASOR ESTIMATOR * 3. Introduction New pplictions using synchronized phsor esureents for enhncing the power grid relibility nd security becoe n iportnt prt of the overll srt grid deployent [85]. The exples entioned in the previous section such s rel tie dynic stte onitoring, stte estition, odel vlidtion, nd instbility detection/islnding re iproving wide re visuliztion, protection nd control [7]-[84]. The ccurcy of phsor esureents becoes n essentil spect tht y directly ffect the ppliction perfornce, nd hence y hve profound ipct on the entire syste. As ddressed in Section.., the conventionl Fourier filter bsed phsor estition lgoriths hve difficulties in processing dynic sinusoidl wvefor distortions, such s odultion, frequency drift nd prticulrly brupt chnge in gnitude. Section.. discusses the existing solutions for iproving the ccurcy of phsors coputtion under trnsient conditions. However, they hrdly solve the issue of * Prt of the teril in this section is reprinted fro An dptive phsor estitor for power syste wvefors contining trnsients by Jinfeng Ren nd Mlden Kezunovic, IEEE Trns. Power Delivery Under review, pper no. TPWRD IEEE, with perission fro IEEE.

63 45 deling with step chnge signls cused by electrognetic trnsients. For the rest of this section the effect of power syste trnsients on phsor behvior is nlyzed firstly. A wvelet ethod is used to pre-nlyze the wvefor within n observtion window in Section 3.3. It cn detect nd loclize vrious disturbnces while discriinting the vlid signl step chnges fro noise. In Section 3.4, once vlid discontinuity is loclized, n dptive window contining vlid dt is used to fit qudrtic polynoil odel in the sense of lest squre error. The signl odel hs perfect ccurcy when representing the gnitude nd phse ngle odulted signls. The lgorith ipleenttion nd ppliction studies re presented in Section 3.5 nd 3.6 respectively, nd sury is outlined t the end. 3. Power Syste Trnsients Fults nd switching opertions produce discontinuous points such s steps nd rps in voltge wvefors respectively due to electrognetic trnsients. Typiclly the phsor estition is deterined over one cycle of noinl power frequency. The discontinuities in wvefors cused by the trnsients y occur within n observed dt window. In this cse the ccurcy of the phsor output estited over such dt window is ffected by the discontinuities, nd it cn neither represent the pre-stte nor the post-stte ccurtely. An exple for coputing the phsors representtion of wvefor with n brupt

64 46 step in the plitude nd phse ngle is given in Figure 4. The step fors boundry which seprtes the pre-disturbnce fro the post-disturbnce segent. Assuing the observing window spns N sples, s the coputtion window oves forwrd when new sples re obtined, the dt window nd +N re the windows closest to the boundry contining only the sples belonging to the pre-disturbnce nd post-disturbnce respectively. Dt Window, +, +, Dt Window +N-, +N Figure 4 Moving windows for wvefor with steps in gnitude trnsition phsors X+, X+N- phsor X+N phsor X Figure 5 Evolution of phsor esureents over trnsient period

65 47 The phsors clculted through the windows +to +N- represent neither the prenor post- segents. Figure 5 shows the phsors during the trnsition period. Use of such phsor estites for ny type of protection or control pplictions y be inpproprite. A technique for identifying the discontinuities while eliinting their ipct on the ccurcy of outputs will be described. The technique cn be lso used to flg such invlid phsor esureents. Power swing y occur followed by disturbnces such s fult, line switching, genertion tripping, loss of lod or other syste disturbnces. During power swing the plitude nd phse ngle of the voltge nd current re odulted with low frequency signl which corresponds to the devition of rotting speed ong genertors. Let consider n exple of oscilltions cused by three-phse fult. The wvefor of phse-a voltge nd its plitude envelop re given Figure 6. The rely opertion ws delyed nd the oscilltion strted fter the fult ws clered. A DFT-bsed lgorith is used to copute the phsors. This lgorith is the widely used technique in presently vilble PMUs though it hs difficulty in deling with sinusoids with chnging preters. Figure 6 shows the dynic behvior when the lgorith is exposed to the steps nd odultions. The phse estites nd totl vector error TVE, which is defined in [5] is given in Figure 6 b nd c respectively. In this exple the TVE reches.6% during oscilltion, which y hrdly eet soe pplictions

66 48 requireents. The ccurcy during power swing needs to be iproved. Voltge wvefor nd plitude estite b Phse ngle estite c TVE Figure 6 An oscilltion exple nd estited phsors by DFT-bsed lgorith 3.3 Disturbnce Identifiction nd Locliztion The step in wvefor discussed bove is one clss of edges,... singulr points s clled in thetics, which exist ong different segents of the wvefor. In the re of ige processing the edges contin lot of criticl infortion nd the detection

67 49 of the plys significnt role in the discipline. Mny techniques hve been proposed to detect nd further chrcterize the singulrity of signls [86], [87]. This study utilizes such principles nd es iproveent for better resolving the specific probles identified in power syste Lipschitz Exponent The locl regulrity of function cn be theticlly esured with Lipschitz Exponent α, i.e. LE α, which is defined s follows [86]. Definition : A function ft t c, d is described to be Lipschitz α t point t 0, if there exists constnt K nd polynoil P n t, such tht t c, d, the following is held: α f t Pn t K t t0 3. Bsed on bove definition one cn esily prove tht for positive integer n, if ft is LE α > n, then ft is n ties differentible t point t 0 while the polynoil P n t is the first n+ ters of the Tylor series of ft t t 0. LE indictes the differentibility of function. Furtherore, if the LE α of ft stisfies n < α < n+, then we lern tht ft is n ties differentible t t 0 but its nth derivtive is singulr t this point nd the LE chrcterizes its regulrity.

68 50 t t t t 3 t 4 t 5 t 6 Figure 7 An exple of sinusoidl wvefor contining vrious coponents Figure 7 shows sinusoidl wvefor contining soe coponents, including noise, step edge nd rp edge t different loctions t, t,, t 5, which cn be esily found in voltge nd current esureents of the rel power syste. Mtheticl functions which represent these signl coponents nd heir corresponding locl Lipschitz regulrities re given in Tble. Idelly the voltge nd current wvefors re pure sinusoidl. They re usully continted by vriety of noise, ong which the ipulse noise nd white noise re the ost two coon inds. Soeties step nd rp edges y occur in voltge wvefor due to the electrognetic trnsients during fults nd switch opertions. Fro Tble we now tht the different functions cn be discriinted with their LEs. The following sections will present the ethod for estiting the exponents pproxitely.

69 5 Tble Specific functions nd their Lipschitz exponents Loction Function L. E. t Dirc Ipulse α = - t White Noise -<α < -0.5 t 3 Step α = 0 t 4, t 5 Rp α = t 6 Sinusoidl α >> 3.3. Wvelet Function nd Trnsfor Coefficient The wvelet trnsfor hs been proven to be n effective theticl tool to nlyze the regulrity of signl becuse of its rerble cpbility of the locliztion in both tie nd frequency doin. A wvelet is defined s function ψ t L R whose Fourier trnsfor Ψω stisfies the dissibility condition: + Ψ ω ω In tie doin this condition iplies: dω = C Ψ < 3. + Ψ ω ω = ψ t dt = = 0 Denote s nd u s the scling fctor nd tie shifting fctor respectively. A set of wvelet functions cn be derived by dilting nd trnslting the other wvelet ψt, t u ψ, = u s t s ψ, s > s Definition : The wvelet trnsfor of function ft with regrd to tie shift u nd scle s is defined s,

70 5 t u Wf u, s = f t u, s t = s + ψ f t ψ dt 3.5 s Where Wfu, s is denoted s the trnsfor coefficient. Let scle fctor s chnge long the dydic sequence of j j=,, we hve the dydic wvelet function ψ u,j t nd its dydic wvelet trnsfor coefficient Wfu, j. For siplicity we designte s Wfu, j for the rest of this study. It hs been proven tht input signl cn be perfectly reconstructed with the dydic trnsfor coefficient. Besides, it leds to efficient nuericl ipleenttions. The coponent of interest in the input signl, clled the edge in this study, cn be exposed over the trnsfor coefficient by selecting proper wvelet nd trnsfor scles Mesuring Signl Regulrity with Wvelet Trnsfor Assue the wvelet holds n vnishing oents, i.e. n ties differentible. Tht is for ll positive integer < n, ψt stisfies + t ψ t dt = Theore : Let n be positive integer nd α n. If ft is Lipschitz α t t 0, then there exists constnt A such tht for ll point t in neighborhood of t 0 nd ny scle s, the wvelet trnsfor of ft with regrd to ψt with n vnishing oents holds Wf α 0 α u, s A s + u t 3.7 Theore : ft nd it wvelet trnsfor is well defined over c, d, nd let t 0 ϵ c, d. Suppose tht there exists scle s 0 nd constnt C, such tht for t ϵ c, d nd s< s 0, ll

71 53 the odulus xi of Wfu, s, denoted s Wf x u, s, belong to cone defined by t t 0 C s 3.8 Then t ll points t c, d, t t 0, ft is uniforly Lipschitz n in neighborhood of t. Let α n be non-integer. The function ft is Lipschitz α t t 0, if nd only if there exists constnt A such tht t ech odulus xi is in the cone defined by 3.8 Wf u, s A s α x 3.9 The proof of the bove theores hs been given by Mllt [86]. He pointed out tht the xi of the wvelet trnsfor odulus cn reflect the loctions of the irregulr structures. If we rewrite eqution 3.9, then: log Wf x u, s log A + α log s 3.0 Fro 3.0 one cn see tht the Lipschitz regulrity t point t 0 is the xi slope of stright lines tht rein bove log Wf x u,s on logrithic scle s. The dydic wvelet trnsfor s = j for scle j nd j+ cn be obtined fro 3.0 log Wf x u, j log A + α j 3. log Wf x u, j + log A + α j + 3. Subtrct 3. fro 3. the LE α cn be pproxitely estited by the following eqution Wf x u, j + α log 3.3 Wf u, j x Eqution 3.3 shows tht the Lipschitz α of signl t ny point cn be

72 54 pproxitely estited by its odulus xi of dydic wvelet trnsfor over djcent scles. Bsed on LE one cn identify the types of singulrities. For exple, if Wf x u, j+ = Wf x u, j, i.e. α=0 it iplies the signl is discontinuous t this point, such s step chnge; if Wf x u, j+ < Wf x u, j, i.e. α<0, it iplies tht the signl is ore singulr thn discontinuity t this point, such s Dirc nd white noise; if Wf x u, j+ > Wf x u, j, i.e. α>0, it ens the signl is t lest continuous such s rp, or sooth such s sinusoid Modulus Mxi Detection nd Locliztion In thetics the inflection points of function correspond to the locl extre of the first derivtive of the function or to the zero crossings of the second derivtive of the function. Bsed on this, Cnny developed coputtionl pproch for edge detection using sooth functions [88]. Let f be the originl signl nd F be the soothed one by function θ, for exple the Gussin function whose integrl is equl to one nd it converges to 0 t infinity. In the sense of filtering F = f *θ, where * stnds for the convolution opertor. Suppose tht θ is twice differentible nd define ψ nd ψ' s the first- nd second-order derivtive of θ, respectively. In this cse the detection of edges is equivlent to locting the inflection points of the soothed F. Tht is to find the locl extre of f*ψ or zero crossings of f *ψ'. Both locl extreu nd zero crossing give loction infortion of the inflection

73 55 point nd detecting the is siilr procedure. However the locl extreu pproch hs soe iportnt dvntges. An inflection point of F cn be either xiu or iniu of the bsolute vlue of f *ψ. The xiu is shrp vrition point of F, which is the point of interest, wheres the iniu corresponds to slow vrition. With second derivtive opertor ψ' it is difficult to distinguish these two types of zero crossings. On the contrry, with the first derivtive ψ one cn esily detect the shrp vrition points by only locting the locl xi of f *ψ, which is the odulus of f *ψ. Besides, finding xiu point is uch esier thn locting zero crossing point. In the frequency doin, the sooth function θ fetures low-pss filter while its first derivtive ψ is bnd-pss filter. The function ψ cn be considered to be wvelet becuse its integrl is equl to zero by definition. Let ψ s be the function dilted by scle fctor s. The wvelet trnsfor of f under scle s is given by Wf s = f ψ 3.4 s Fro bove discussion we now tht the inflection points with shrp vritions cn be detected nd loclized by the odulus xi of wvelet trnsfor Step Identifiction with LE After detecting the disturbnce points one needs to further identify their types becuse the shrp vritions y either be step or noise. As we discussed the types, or regulrities in thetic ters cn be chrcterized by LE which cn be estited by

74 56 the evolution cross scles of wvelet trnsfor odulus xi Wf x u, j. To chieve this gol we construct cubic order B-Spline function s the sooth function nd its first-order derivtive s the wvelet function, i.e. qudrtic B-Spline wvelet. This wvelet possesses desirble properties, such s the copct support, syetry nd biorthogonlity [89]. It hs siple nlyticl for in frequency doin. The filter length for scling function nd wvelet function re 4 nd respectively. This feture results in n efficient nuericl ipleenttion for the ulti-scle decopositions. For exple, if one perfors wvelet trnsfor in two scles, N ultiplictions nd sutions will be required, where N is the length of input dt. In Figure 8 four types of singulrities, Dirc, white noise, step, nd rp re shown in designted s p-p4 respectively. Their trnsfor coefficients of qudrtic B-Spline wvelet fro scle to 3 re given in b c. Fro Figure 8 we cn observe tht for the Dirc nd white noise the xi of wvelet trnsfor coefficient decrese long the evolution of scles while for the step nd rp they increse long the evolution of scles.

75 57 Figure 8 Singulrities nd their coefficients of wvelet trnsfor cross scles This cn be clerly seen by the rtios of wvelet trnsfor odulus xi for djcent scles given in Tble, where Wf x j stnds for the odulus xiu under scle j. The LE estites by 3.3 re given s well. It hs to been pointed out tht gnitude steps in voltge wvefors re usully soothed to pper s rp due to their trvelling long the trnsission lines. As result the LE will fll into the rnge between 0 nd. For siplicity let designte such singulrities s steps for the rest of the study.

76 58 Tble Rtios of wvelet trnsfor odulus xi nd LEs Type Wf x / Wf x Wf x 3 / Wf x LE α p /-. P /-.58 P /0.5 P / Ipleenttion nd Threshold Let f be the sples of the input signl nd N be the length of the observed dt window. Suppose f is properly processed using low-pss filter to coply with the Spling Theore. The process of disturbnce detection will be perfored to ech observed dt window denoted s f N before directly estiting the phsor over it. The ipleenttion procedure for disturbnce detection is: Detect the singulrity of the input signl to see if ny disturbnce occurs within this window spn. Perfor wvelet trnsfor using the qudrtic B-Spline wvelet in scle to obtin the hve coefficient Wf, =, N. Under norl conditions, the signl is sinusoidl, thus the coefficient Wf, hs no locl odulus xi. If there is no odulus xiu the process is terinted nd dt will be hnded over to the next process, such s phsor estition; If the odulus xi Wf x, exist then there re singulrities within the window nd loctions cn be found by Wf x, s well.

77 59 Identify the type of singulrities. The singulrities cn be either the rel trnsient disturbnces brupt steps or the noise cused by vriety of interferences brought into the esureents. To further distinguish the the wvelet trnsfor coefficients in scle is coputed nd the odulus xi Wf x, re found. If Wf x, / Wf x, α=0 =, the singulrity is step, the dt will be turned over to the process of the step hndler; If Wf x, / Wf x, < α=-0.5 = 0.707, the singulrity is noise, then the process is terinted nd dt is turned over to the process for phsor estition. 3.4 Adptive Phsor Estition Schee Typiclly PMUs generte synchrophsors t subultiples of the noinl power syste frequency. One cycle period of the input signl is coonly used s the length of the dt window for phsor coputtions. The sples of voltges nd currents in window spn re obtined t the se rte s the output phsors. And the position of window is either centered, or sided t the beginning or the end t fixed points corresponding to tiestps. The brupt steps in input signls y ffect the ccurcy of phsor outputs, prticulrly when the dt window crosses the step point. The ethod for detecting the trnsient disturbnces hs been discussed. This section will introduce n dptive dt window for voiding or iniizing the ipct of disturbnces nd present signl odel for ccurtely estiting phsors during trnsients.

78 Adptive Dt Window Suppose tht the occurrence of step chnge within spn of dt window hs been identified nd loclized. Let N be the length of the window. As shown in Figure 9 the window for tie stp t denoted s window t contins step chnge in wvefor. The phsor coputed over this window will represent neither the pst norl stte nor the present fulty stte becuse it contins prtil sples of both sttes. Since the position of the step chnge within this window hs estited, we cn use the dt either before or fter the step point. b t t l N-l N-l l t Figure 9 Occurrence of step chnge in dt window To use the dt before the singulr point the prtil dt with the length of l in window t cobining the dt with the length of N-l, which is usully stored in buffer with continuous spling, fors the window t b. It should be pointed out tht the plitude of the phsor estited over the window b t represents the pst stte while the phse ngle strts showing the trnsition due to the selection of ngle reference.

79 6 To use the dt fter the singulr point, the windowt is fored by using the prtil dt with the length of N-l in window t, nd cobining the dt fro the next spling window with the length of l. In this cse both the plitude nd phse ngle will represent the present stte. The phsor output will be delyed becuse of the wit due to cquiring dt l in the next spling window. Which dt window will be used in the lgorith cn be deterined by the specific requireents of the pplictions. For exple, soe pplictions tht require the lest output ltency y use the windowt b ; soe pplictions tht require rpid detection of the disturbnce stte, but cn tolerte the dely to certin level, y use the window t. How to select the dt window for specific ppliction will not be discussed here. Nevertheless, siple rule will be followed nd it will be used in the lgorith for the rest of the considertions: if the singulr point occurs in the first hlf of the window, s shown in Figure 9, windowt will be used for coputing the phsor; if the singulr point occurs in the second hlf of the window, windowt b will be used. Bsed on this rule the xiu dely for using window t will be hlf cycle, i.e. N/ ties spling intervl Phsor Estition Algorith The conventionl DFT-bsed lgoriths usully ssue sinusoidl signl odel with constnt plitude nd phse ngle over the observtion window. This ssuption

80 6 is not very rigorous for the signls during power syste trnsients. For better describing the signl in trnsient stte odel with chnging plitude nd phse ngle is eployed: y t = t cos[π f 0t + ϕ t] 3.5 where f 0 is the noinl frequency, the plitude t nd phse ngle φt re functions of tie. Rewrite 3.5 s y t = t cos[ ϕ t]cosπf t t sin[ ϕ t]sinπf t For n observtion intervl, the tcos[φt] nd -tsin[φt] re the envelopes of the noinl frequency coponents cosπf 0 t nd cosπf 0 t respectively. Using the qudrtic for to pproch the envelopes spnning the observtion intervl we hve, y t = q + q t + q t cosπf t r + r t + r t sinπf t where q 0, q, q, r 0, r, r re the coefficients of qudrtic for. According to the synchrophsor stndrd C37.8 the plitude A nd phse ngle φ re coputed over the observtion window t the tiestp t, which is the point t = 0 in the window. This is lso the reference point for coputing phse ngle. Fro 3.5 we hve A = t t=0, φ = φt t=0. Let θt = πf 0 t + φt, then the frequency t the reference point cn be represented with f = dθ t πdt t= 0 = f 0 ϕ t + π t= 0 3.8

81 63 Estiting the qudrtic coefficients in 3.7 cn be chieved by resolving the liner regression proble. Suppose tht the solution depends linerly on the dt M γ ij x j = yi i =, N, tht is N liner equtions in M unnown coefficients x, j x x M, with N>M. Rewrite this in trix for s H X=Y. The fitting vribles X re deterined in the lest squre error sense by solving the qudrtic iniiztion proble rgin Y-H X. For 3.7 the H trix is H = [cosπf 0 t i -sinπf 0 t i t i cosπf 0 t i -t i sinπf 0 t i ti cosπf 0 t i -ti sinπf 0 t i ], i =, N. The corresponding fitting vrible X vector is X = [q 0 r 0 q r q r ] T, where T stnds for the trnspose. For N-sple window the H trix is N 6 trix while the fit dt Y is N vector. The position of the phse reference in given observtion window cn be deterined by ssigning tie vectort. If the tiestp is locted in the iddle of the window let t = t N,,0, t ]; if [ / N / the tiestp is locted t the beginning or the end of the window, ssign t 0, t, t ] or t = t,,,0] N, respectively. = [ N [ t After obtining the fit coefficients, the plitude nd phse ngle over the observtion window cn be coputed by the following equtions: A = / q0 r0 ϕ = rctn r0 / q0 3.0 f = f 0 q0r r0 q + π q + r

82 64 And the rte of chnge of frequency R f = df /dt. The derivtion of the bove equtions is given in the Appendix A Study of Model Accurcy Eqution 3.7 uses the qudrtic for to pproch the envelope of the slow chnging in n observtion intervl. The dequcy of such pproxition is investigted to ensure the odel is cpble of representing the voltge nd current signls esured fro the rel syste. The new synchrophsor stndrd C37.8. being blloted defines dynic signl odels nd corresponding specifiction requireents. The disserttion uses the signl odels nd test conditions defined in the stndrd drft to study the ccurcy of phsor estition lgorith. Two types of signls representing the power oscilltion nd frequency rp re given s follows:. Power Oscilltion y t = A [ + x cosπf t] cos[πf 0t + cosπf t π ] 3. where A is the constnt plitude, f is the odultion frequency, nd x nd re odultion fctors for plitude nd phse ngle respectively. b. Frequency Rp y t = A cosπ f 0t + πf t + ϕ d 3.3 where f d is the rte of frequency chnge nd φ is the initil phse.

83 65 0.% white noise SNR 60 db is dded to the test signls. We use one cycle s the observtion intervl for the phsor esureent. The TVE nd the frequency error Δf re used to esure the estition ccurcy. Abundnt scenrios tht y be observed in rel syste re studied s surized in Tble 3. The test conditions re ore severe thn these required by the stndrd. The xiu vlues of TVE nd frequency error, which correspond the ost rigorous conditions, re given in Tble 3. For exple, s relted to type, the ost rigorous condition is f = Hz, x = =0.. The typicl TVE nd frequency error re t the level of 0.0 % nd Hz respectively. The results deonstrte tht the odel pproch is dequte for representing the power signl under trnsient conditions. Tble 3 Results for ccurcy studies Type b Conditions 00% rted gnitude nd f 0 t strt f : 0. Hz to Hz x : 0 to 0., : 0 to 0.. f d : ±0. Hz to ± Hz Rp rnge: ±5 Hz Mx TVE % Mx Δf Hz Ipleenttion of Adptive Estitor The dptive phsor estition pproch hs been ipleented for rel-tie use in the synchrophsor esureent test syste, which ws developed on PC-bsed PXI

84 66 pltfor by Ntionl Instruents nd used for PMU clibrtion nd testing [60]. The syste consists of controller, tie synchroniztion cloc nd dt cquisition odules. It is cpble of perforing synchronous spling for eight chnnels t up to 500 Hz. The ipleenttion flow chrt of the dptive schee is shown in Figure 0, where the vlid ens tht the input sples within the observtion window hve discontinuity cused by electrognetic disturbnce insted of noise. Figure 0 Ipleenttion flow chrt for the dptive pproch Solving the qudrtic iniiztion proble rgin Y-H X is equivlent to solving Y HX / X = 0, Tht is H T Y HX = Let designte H T Y s Z, nd H T H s G. If we rewrite 3.4, we hve G X = Z 3.5 where G is 6 6 trix, nd Z is 6 vector. Then the fitting vribles X cn be estited by solving eqution 3.5. For efficient ipleenttion, the coefficient trix G cn be

85 67 clculted in dvnce nd decoposed into LU trices for fst coputtion. It hs been proven tht the trix G is nonsingulr. For given size of dt window N, the disturbnce chec requires bout N ultiplictions nd sutions while phsor estition requires 6N+30 ultiplictions nd 6N+0 sutions. The coputtion burden is very low. We hve deonstrted tht the dptive pproch cn be relized in rel-tie. 3.6 Appliction Studies We use voltges nd currents generted fro the tie doin progr ATP/EMTP to evlute the perfornce of the dptive phsor estitor under trnsient conditions. The power syste odel is 30 V power networ creted by IEEE Power & Engineering Society s PSRC [90]. The files recording voltge nd current wvefors re red by progr nd fed to lgoriths. Two scenrios re considered: one is trnsission line fult followed by tripping of fulted line tht cused power swing; nother is n out of step due to loss of lod. We use.9 Hz spling frequency nd one cycle dt window. The estites fro three lgoriths re copred; the dptive phsor estitor denoted s APE, the DFT-bsed lgorith nd the four-preter lgorith denoted s FPA in [] Power Swing Followed by Three-phse Fult We use one phse voltge fro secondry side of instruent trnsforer s the

86 68 input fed to the phsor estition lgoriths. As shown in Figure two disturbnces occurred t t nd t which stnd for the three phse fult nd the clernce of fult respectively, nd oscilltions followed. The estited plitude, phse ngle, frequency nd TVE in the vicinity of t nd t for the three lgoriths re given respectively in Figure -d t n pproprite zoo. One cn see tht the DFT nd FPA suffer step effects when exposed to the disturbnces, prticulrly for the frequency estition. In Figure d the TVEs exceed 0% during trnsitions. Figure Voltge wvefor under fult nd power swing condition The proposed ethod is cpble of detecting the disturbnces nd coputing phsors with dptive windows. In this cse the phsor estites cn follow the input chnges very well. The xiu TVEs for DFT, FPA nd APE during oscilltion re.4, 0.89 nd 0. respectively.

87 69 Aplitude estites b Phse estites c Frequency estites d TVE Figure Preter estites nd errors of three lgoriths t t nd t

88 Out of Step Cused by Loss of Lod One phse current fro secondry side of instruent trnsforer is fed to the phsor estition lgoriths. Figure 3 shows the current wvefor esured during disturbnces. The estited plitude, phse ngle, frequency nd TVE by the three lgoriths re given in Figure 4 -d. Copred to the DFT-bsed lgorith, both four-preter lgorith nd the proposed phsor estition ethod cn follow the input during oscilltions. The xiu TVEs for DFT, FPA nd APE fter t re 4.%,.3% nd 0.086% respectively. This proves tht the proposed dynic phsor odel chieves better ccurcy thn tht of the four-preter odel. Fro the TVE results in Figure 4 d we cn observe tht the dptive ethod successfully detected nd loclized the discontinuous point t nd t so tht their effects on outputs were eliinted. Figure 3 Current wvefor under out of step condition

89 7 b c d Figure 4 Estited plitude, phse, frequency nd TVE for three lgoriths 3.7 Sury An dptive pproch for estiting phsor under power syste trnsient conditions in rel-tie is proposed in the disserttion. The sury is given s follows: The wvelet ethod is ble to identify nd loclize the disturbnce while discriinting fro vrious types of noise within given dt window. The effect of electrognetic trnsients cn be eliinted by using dptive dt window.

90 7 The qudrtic polynoil odel chieves better ccurcy during power oscilltions. The proposed pproch cn be ipleented for rel-tie synchrophsor estition. It cn lso be used s the reference lgorith for testing devices perforing synchrophsor esureents. The proposed lgorith for disturbnce detection cn be used to indicte the phsor qulity so tht the power syste pplictions re ble to be wre of whether the phsors they use or the results bsed on the phsors re vlid or not.

91 73 4. NEW PHASOR ESTIMATION ALGORITHM * 4. Introduction The phsor frequency, plitude nd phse ngle re criticl vribles used by ny lgoriths. How to rpidly nd ccurtely estite frequency nd other phsor preters is still conteporry topic of reserch interest. Discrete Fourier Trnsfor DFT is widely used s filtering lgorith for estiting fundentl frequency phsors [9], [9]. Conventionl DFT lgorith chieves excellent perfornce when the signls contin only fundentl frequency nd integer hronic frequency coponents. Since in ost cses the currents contin decying DC coponents this y introduce firly lrge errors in the phsor estition [93], [94]. As ddressed in Section.., ny techniques for the rel tie estition of power syste frequency hve been developed nd evluted in pst two decdes [5]-[4]. Soe ethods were developed to iprove the perfornce of DFT bsed pproches. Such iproveents include dptive ethods bsed on feedbc loop by tuning the spling intervl, djusting dt window length, chnging the noinl * Prt of the teril in this section is reprinted fro Rel tie power syste frequency nd phsor estition using recursive wvelet trnsfor by Jinfeng Ren nd Mlden Kezunovic, IEEE Trns. Power Delivery, vol. 6, no. 3, pp , July 0 0 IEEE, with perission fro IEEE.

92 74 frequency itertively, correcting the gins of orthogonl filters nd tuning the weighted fctors. Becuse of the inherent liittion in DFT, t lest one cycle of nlyzed signl is required, which hrdly eets the dend of high-speed response for protection schees. The ethods using consecutive sples of the instntneous input signl suffer the noise nd zero crossing issues. Kln filter nd recursive Lest Squres lgorith re well nown techniques. Soe rtificil intelligence techniques, such s genetic lgorith nd neurl networs hve been used to chieve precise frequency estition over wide rnge with fst response. Although better perfornce cn be chieved by these optiiztion techniques, the ipleenttion lgorith is ore coplex nd intensive in coputtion. The techniques developed for eliinting the ipct of decying DC coponent in phsor estition include digitl iic filter bsed ethods [5] nd preter estition bsed lgoriths [6]-[3]. The iic filter perfors well when its tie constnt tches the tie constnt of the exponentilly decying coponent. For preter estition bsed ethods, soe technique such s the siultneous eqution, prtil sution, Tylor expnsion nd lest squre ethod re utilized. Those ethods either require dditionl sples or both voltges nd currents, which y cuse ppliction probles. Recursive wvelet pproch ws introduced in protective relying for long tie

93 75 [95]-[99]. The iproved odel with single-direction recursive equtions is ore suitble for the ppliction to rel-tie signl processing [98]. The bnd energy of ny center frequency cn be extrcted through recursive wvelet trnsfor RWT with odertely low coputtion burden. A new other wvelet with recursive forul is constructed in this study. RWT bsed rel tie frequency nd phsor estition nd decying DC coponent eliintion schee is proposed. Section 4. introduces the bsic concept of wvelet trnsfor, presents the newly constructed recursive wvelet nd its chrcteristics both in tie nd frequency doin nd describes the process of deriving recursive forul for clculting wvelet trnsfor coefficients. The frequency nd phsor estition lgorith is described in Section 4.3. The nlysis of convergence nd coputtion burden is presented in Section The ethod for eliinting the effect of decying DC offset is given in Section 4.4. Section 4.5 nd 4.6 present the detils of perfornce evlution nd sury respectively. 4. Recursive Wvelet Trnsfor 4.. Wvelet Trnsfor Bcground Mother wvelet function is defined s function ψt which stisfies the dissibility condition:

94 76 = + Ψ ω ω C Ψ d ω < 4. + i.e. Ψ ω ω = 0 = ψ t dt = 0 where Ψω is the Fourier trnsfor of ψt. A set of wvelet functions cn be derived fro ψt by dilting nd shifting the other wvelet, s given below: t b ψ /, = b t ψ, > 0 4. where nd b re scling diltion fctor nd tie shifting trnsltion fctor, respectively. A good wvelet is such function tht eets the dissibility condition nd hs sll tie-frequency window re [89]. We construct other wvelet function s expressed s follows: 3 3 σt σ t σ t σ + jω0 t ψ t = + + e u t And we designte function ψ t = ψ * t, 3 3 σt σ t σ t σ + jω0 t ψ t = + e u t Its frequency doin expression obtined by Fourier trnsfor is given in following expression: σ ω0 ω Ψ ω = [ σ + j ω ω ] σ 4.5

95 77 Setting σ = π / 3, ω = π es the wvelet function ψt dissible, i.e. Ψ ω= ω = Figure 5 Tie doin wvefors of ψt Figure 6 Frequency doin wvefors of Ψω One cn see tht the newly constructed wvelet is coplex function whose tie nd frequency doin expressions contin rel nd iginry prts. Figure 5 nd Figure 6 give tie nd frequency doin wvefors of ψt nd Ψω, respectively. Soe perfornce preters cn be clculted to specify wvelet function [89]. Tie-doin center t * nd window rdius Δt of wvelet function ψt re s nd

96 s respectively. As one cn see in Figure 6, it fetures bnd-pss filter with the frequency-doin center ω * nd bnd rdius Δω of π rd nd.38 rd. One of dvntges of the wvelet trnsfor is tht the qulity fctor Q, defined s the rtio of frequency center ω * nd bndwidth Δω, stys constnt s the observtion scle vries. For Ψω, Q =ω * /Δω =.7. The coplex wvelet exhibits good tie-frequency locliztion chrcteristics. Its tie-frequency window re S defined s product of tie window width Δt nd frequency bnd width Δω is.3 rd s. To obtin the center frequency f c of the bnd-pss filter, which is defined s the frequency in which the function reches the xiu gnitude, we hve the Fourier trnsfor for the dilted wvelet function ψt/: σ ω ω 3 0 Ψ ω = 4.6 [ σ + j ω ω ] 4 0 3σ Ψω reches the xiu vlue when ω = ω 0, i.e. π f c = π. Thus, we hve f c = /. Tht is the scle fctor is reciprocl to the center frequency f c of the bnd-pss filter. 4.. Newly Constructed Recursive Wvelet Since the wvelet function ψt is nti cusl which hs zeros for ll positive tie, the wvelet trnsfor coefficient in scle for given cusl signl xt cn be expressed s below:

97 79 b / t b Wx t, b = x t ψ dt, t > Let ΔT be the spling period, n nd re integers. Then t =nδt, b =ΔT. With the observing frequency f = /, forul 4.7 cn be expressed discretely: Wx n T f, T = T f x n T ψ f n T T = n = T f = n Above forul cn be expressed using convolution: W x n T ψ f T n 4.8 T T f, T = T f [ x n T ψ fn ] 4.9 x n T Ting z-trnsfor on both sides, we hve, W z x f, Z = T f [ X Z Ψ Z ] 4.0 where W z x f, Z, X Z nd Ψ Z re z-trnsfors of discrete sequences W T f,, x n T nd ψ fn T, respectively. x n T Bsed on the expression of wvelet function ψ t, we derive its discrete for in ters of observing frequency f, 3 3 σfn T σ fn T σ fn T σ + jω0 fn T ψ fn T = + e u fn T 4. 3 Its z-trnsfor is expressed s follows, n Z = ψ fn T Z 4. n= 0 Ψ f T σ jω0 Denoteα = e, we obtin the expression for Ψ Z,

98 = Ψ z z z z z z z Z β β β β λ λ λ 4.3 where, 3] / / / [ 3 T f T f T f + = σ σ σ α λ, ] 3 / 4 [ 3 T f T f = σ σ α λ 3] / / / [ T f T f T f = σ σ σ α λ, α β 4 =, 6α β =, 3 3 4α β =, 4 4 α β = Fro 4.0 nd 4.3, we obtin, = z z z Z X f T Z W z x λ λ λ z z z z Z W z x β β β β 4.4 According to the properties of inversion of z-trnsfor, we obtin the recursive expression for discretely coputing wvelet trnsfor coefficients, 4, 3,,, ] 3 [, T f W T f W T f W T f W T x T x T x f T T f W T n x T n x T n x T n x T n x + + = β β β β λ λ λ 4.5 In forul 4.5, f represents the observing center frequency which is reciprocl to the scle fctor. To extrct the frequency bnd energy centered in 60 Hz, for instnce, siply pply f = 60 to 4.5. One cn notice tht wvelet trnsfor coefficients cn be clculted recursively with the historicl dt. This type of wvelet trnsfor is so-clled the recursive wvelet trnsfor RWT. Copring with the RWT in [96] nd [98], the proposed RWT requires the historicl dt nd less coputtion, thus it cn be used in rel tie pplictions.

99 8 4.3 Frequency nd Phsor Estition Algorith As discussed in previous section the recursive wvelet RW fetures coplex wvelet whose wvelet trnsfor coefficients rel prt nd iginry prt contin both phse nd gnitude infortion of the input signl, bsed on which the lgorith for estiting the power syste frequency nd phsor is derived s following RWT Bsed Frequency nd Phsor Estition Let us consider discrete input signl tht contins Mth order hronics with spling period ΔT: M x n = A = cosπ f n T + ϕ, n = 0,,, 4.6 where f, A nd φ represent the frequency, plitude nd phse ngle of th order hronic, respectively. Denoting the bsolute phse ngle of the th order hronic t sple n sθ n = π f n T + ϕ, one cn see tht frequency f represents the rte of chnge of θ. For siplicity, the spling period ΔT is neglected when expressing vribles for the rest of the pper. To represent the input signl xn in tie-frequency doin pply RWT in scle using 4.5. As derived in Appendix B we hve following expression: W M c c x n, = u, f, x = M s s + u, f, x, = 0,,, 4.7 =

100 8 Fro eqution 4.7 one cn see tht the wvelet trnsfor coefficient W xn contins infortion of input signl in both cosine for nd sine for, denoted s c x nd s x in eqution B.4 nd B.5 respectively, ultiplied by weighting fctors, denoted s c u nd s u in eqution B.6 nd B.7 respectively. Let f represent the initil estite of frequency vrible, nd rewrite eqution B.6 using the first order Tylor series expnsion. Tht is f c c c f df du f u f u +,,,, c c f f u f u + =,,,, 4.8 Q T l f l T f u l c = = 0 / sin,, π π 4.9 where T l j e T l T l T l Q + + = ] 3 [ ω σ σ σ σ. For siplicity, denote,, f u c nd,, f u c s c u nd c u respectively. Then we rewrite the eqution s follows: c c c f u u f u +,, 4.0 Following the se procedures we cn rewrite eqution B.7S s follows: s s s f u u f u +,, 4. Q T l f l T u l s = = 0 / cos π π 4. Then forul 4.7 cn be expressed s follows:

101 83 = + M c c c c n x x u x u W ] [, ] [ = + + M s s s s x u x u 4.3 where c c f x x = nd s s f x x =. Applying RWT to xn in series of scles,,, 4M we obtin series of coefficients w, w,, w 4M tht cn be expressed in 4.3. Rewrite those equtions in trix for:,,,,,,,,,,,,,,,,,,,,,,,,, s M s s c c s M s s c c s M s s c c s M s s c c s M s s c c s M s s c c x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u w w w w w M M M M M M 4.4 For siplicity, we represent bove trix in vector for. At sple we hve the following eqution: X U W 4.5 In 4.5 the wvelet coefficient W cn be clculted using recursive eqution 4.5. For weighting fctor U, it cn be clculted with estited frequency f using equtions B.6, B.7, 4.9 nd 4.. Solving eqution 4.5 we obtin vector vrible X. Then we cn derive the following forul for Δf : x x x x x x f s c s s c c + + = 4.6

102 84 After we estite the frequency djustent, updte frequency with f + f nd iterte bove pproxition procedures until either the frequency chnge reches the cutoff vlue, for exple ε = 0.00 Hz, or xiu nuber of itertions denoted s L is perfored. As result, the rel frequency cn be estited t the lst itertion. Then the plitude A nd phse ngle φ cn be estited by the following equtions: A c s x x = + ϕ = θ π f T where cos c θ = x or sin s θ = x The flow chrt s given in Figure 7 illustrtes the ipleenttion of procedures for the proposed frequency, gnitude nd phse estition lgorith. In prctice, low-pss filter with pproprite cutoff frequency is pplied for eliinting high frequency coponents in voltge nd current esureents. As result, the order of hronic coponents cn be liited within the rnge of cutoff frequency. For exple, if third order Butterworth low-pss filter with cutoff frequency 30 Hz is used to pre-filter input signls, in this cse the xiu order of hronics will be liited to five, i.e. M = 5. Generlly we select ultiples of noinl frequency i.e. f 0 = 60 Hz, represents the order of hronics s initil estite to strt itertions. To chieve high ccurcy, scle fctors [, 4M ] re required to cover ll the frequency coponents of the signl being nlyzed. Therefore, we select = / f 0 +-/4. Extensive

103 85 siultions show tht proposed lgorith cn converge to the rel vlue within three itertions. Pre-filter input signl xn Clculte wvelet trnsfor coefficients of xn using 4: W = [w,w,, w 4M ] T Initilize frequency estites f = f0 Strt itertion for p = Clculte weighting fctor trix using 8-b-9-b: p cp c p sp s [,,, p U = U U U U ] f p p = p+ p = f + f Clculte X p by solving 0b: p cp c p sp s [,,, p X = X X X X ] Then, estite f using No Δf ε? or p L? Yes p f = f Estite A nd φ using b nd c End Figure 7 Flow chrt of the frequency, gnitude nd phse estition It should be noted tht if only the fundentl frequency coponent is of interest, i.e. only f is ten into itertion loop, the diension of scle fctors nd weighting

104 86 trix will be reduced to M+.Obviously, if input signl only contins the fundentl c frequency coponent the solved vribles x nd s x M will be soe nubers close to zero, nd then the preters of those hronics re eningless Study of Convergence Chrcteristics The spling rte nd window length y ffect the convergence chrcteristics becuse of two fctors. One is tht these forule re derived bsed on the ssuption tht the error resulting fro the discrete coputtion is negligible. Another is the error introduced by n inherent settling process in recursive equtions. Besides, inppropritely selecting window size nd spling rte y cuse the weighting fctor trix U to becoe singulr. To nlyze the convergence chrcteristics, we define the window length l s s the cycle of the noinl frequency, which is independent of the signl spling frequency f s defined s N ties noinl frequency f 0 in Hz. The vrible l s nd f s deterine the nuber of sples N s within dt window, i.e. N s = l s f s / f 0 = l s N. Totl vector error TVE is used to esure the phsor ccurcy. Once the plitude error ΔA in percent of rel vlue nd the phse error Δφ in degrees re vilble, the expression for TVE is given bytve = A + ϕ / 0.573, where is the rcsine of % in degree. The signl odel in 4.6 is used for the lgorith convergence nlysis. In 4.6

105 87 we let f = 60 Hz nd M = 5, tht is the fundentl frequency coponent contined in the signl is 60 Hz nd the frequency of hronic noise is up to 300 Hz. Anlysis results re given in Figure 8, in which dot represents the convergence while x stnds for divergence. Results indicte tht the window length cn be shortened to 0. cycle if the spling rte is 70 sples per cycle i.e. 4. Hz or higher. Figure 8 Convergence nlysis results Let us consider cse when the fundentl frequency devites to 65 Hz nd perfor the lgorith to estite frequency, gnitude nd phse. Reltionships between frequency error, TVE nd two vribles l s nd f s re shown in Figure 9 nd Figure 30 respectively, in which the signl spling rte is siulted fro 50 to 50 sples per cycle while the window length chnges fro 0.5 to cycle. One cn see tht the proposed lgorith chieves high ccurcy nd fst convergence. Siultions perfored in Section 4.5 lso show tht for brod rnge of frequency devition, such s

106 88 55 Hz 65 Hz, the lgorith cn converge to the rel vlue within three itertions. Besides, the spling rte hs brely ny effect on the ccurcy once it reches to 50 sples per cycle i.e. 3 Hz for 60 Hz power syste or higher. Copring to the conventionl DFT bsed ethods this lgorith cn shorten the window length to qurter- cycle. Figure 9 Estited frequency error for f =65 Hz Figure 30 Estited TVE for f =65 Hz

107 Anlysis of Coputtionl Burden Let us now consider the coputtion burden of the proposed lgorith. If we use 3 Hz spling frequency nd 0.5 cycle dt window s the cse perfored in convergence nlysis nd perfornce tests it pproxitely requires 6000 ultiplictions nd 5796 sutions. Only 68*M+ = 86 ultiplictions nd 5*M+ = 6 sutions re used for coputing RWT coefficients W M+ where M=5, nd 3*M+ 3 =584 ultiplictions nd sutions for trix inverse coputtion when three itertions re perfored. Weighting trix U with vrious scles nd frequencies cn be clculted nd stored in dvnce nd cn be ccessed very fst using tble loo-up ethod. Soe theticl techniques such s Chelosy nd LU fctoriztion ethods cn be dopted to siplify the trix coputtion [00], [0]. The coputtion burden cn then be noticebly reduced to 68*M+ + 3*M+ = 48 ultiplictions nd 5*M+ +3*M+ = 044 sutions. Besides, incresing the window length hs very sll effect on the totl coputtion burden becuse it only increses the coputtion burden of RWT coefficients while the trix diension stys the se. Bsed on the nlysis one cn see the totl coputtion burden is firly low. It cn stisfy the tie response requireent of tie-criticl pplictions.

108 Eliinting Decying DC Coponent Siilr derivtion procedures cn be used to develop the lgorith for eliinting the effect of decying DC Offset. Let us consider the following signl odel tht contins the exponentilly decying coponent: n T τ y n = x n + Aτ e, n = 0,,, 4.9 where xn is the signl odel defined in 4.6, A τ nd τ represent the plitude nd tie constnt of DC offset respectively. Applying RWT in scle to represent signl yn in tie-frequency doin s derived in the Appendix B we hve: W, = Wx n, + uτ, τ, xτ, 0,, 4.30 y n = Fro eqution 4.30 one cn see tht the wvelet coefficient W yn contins the coefficient for signl xn nd the weighted decying DC coponent. Since the tie constnt is unnown to u τ, itertions re required to pproxite it. Let τ represent the initil estite nd rewrite eqution B. using the first order Tylor series expnsion, we hve u, τ, = u τ τ duτ, τ, + dτ τ τ = τ, u, + u, τ, τ 4.3 τ τ where u, τ, = τ T 0 l= / l e l T τ Q

109 9 For siplicity, denote,, u τ τ nd,, u τ τ s τ u nd τ u respectively, nd rewrite bove forul s follows: τ τ τ τ τ + =,, u u u Then the eqution 4.3 cn be expressed s follows: = + = M c c c c n y x u x u W ] [, ] [ = + + M s s s s x u x u x u x u τ τ τ τ where τ τ τ = x x. Applying RWT to yn in series of scles,,, 4M+ we obtin series of coefficients w, w,, w 4M+ tht cn be expressed s the following trix: = ,,,,,,,,,,,,,,,,,,,,,,,,, τ τ τ τ τ τ τ τ τ τ τ τ x x x x x u u u u u u u u u u u u u u u u u u u u u u u u u w w w w w s M c c s M c c s M c c s M c c s M c c s M c c M M M M M M M M M M M M M M M M M M 4.33 For siplicity, we represent bove trix in vector for. At sple we hve the following eqution: X U W = 4.34 In 4.34 the wvelet coefficient W' cn be clculted using recursive eqution 4.5. For weight fctor U, it cn be clculted with pproxite frequency f nd

110 9 tie constnt τ using equtions B.6, B.7, 4.9, 4., B. nd 4.3 respectively. Solving trix 4.34 we obtin vector vrible X. Then we cn derive the forul to estite Δτ: τ = xτ / x τ 4.35 And forul 4.6 cn be used to estite Δf. After we obtin the tie constnt nd frequency djustents, updte those two vribles with f + f nd τ + τ, nd iterte bove pproxition procedures until either the chnges of vribles rech the cutoff vlue or xiu nuber of itertions is perfored. As result, the rel frequency nd tie constnt cn be estited t the lst itertion. Then the plitude A nd phse ngle φ cn be estited using eqution 4.7 nd 4.8 respectively. If we pproxite exponentil function using the second order Tylor expnsion, we obtin: x = τ A e τ T τ = Aτ [ T τ + T τ ] 4.36 The forul for estiting the gnitude of the decying DC coponent is: xτ A τ = 4.37 T τ + T τ The initil estite of the tie constnt τ cn be selected fro wide rnge: hlf cycle to five cycles [5]. Generlly we select two cycles s the initil estite. The expression for x τ is given in 3. Given the spling rte N nd window size /4 cycle the eqution B.0 cn be rewritten s x / 4d τ = A τ e τ = f 0 /d, f 0 = 60 Hz or x τ = τ A e / d the window size is cycle. Considering typicl rnge for the tie

111 93 constnt vrible of decying DC coponent d = [0.5, 5] x τ would te on the rnge 0.6A τ 0.95A τ or 0.4A τ 0.8A τ A τ is the plitude of the decying DC coponent, respectively. One cn see tht the vlue of x τ hs the se level s its plitude. Thus the issues of noise nd division by zero due to the sll vlue cn be voided. The flow chrt for perforing the lgorith is siilr to the one shown in Figure 7 except for odifying the wvelet coefficients nd weighting trix nd introducing tie constnt vribles into itertion loop. 4.5 Perfornce Evlution In this section, perfornce of the proposed estition lgorith is fully evluted with vrious test conditions covering sttic stte, dynic stte nd trnsient stte, nd the results re copred with conventionl DFT ethods, iproved DFT-bsed ethods in [5]-[7] nd the ltest published techniques in [9], [0], [30] nd [3]. In the sttic test, signl odel contining hronics nd noise is used nd the perfornce is verified in wide rnge of frequency devition. The dynic test uses the scenrios tht y occur in rel power syste. The scenrios including the frequency rp, short-circuit fult nd power swing re siulted using pproprite signl odels. In the trnsient test, three-phse current outputs fro ATP/EMTP [90] re used to verify the perfornce of eliinting the DC offset. All tests re perfored with the spling rte N = 50 sples per cycle, i.e. f s = 3 Hz, nd dt window size l s = 0.5

112 94 cycle sples Sttic Test A signl odel in 4.38 contining hronics nd 0.% signl-to-noise rtio SNR=60dB white noise is ssued, where en represents the zero-en Gussin noise. Let A =.0 p.u., φ = 5 º. The fundentl frequency f vries over wide rnge fro 55 Hz to 65 Hz in 0. Hz steps. Frequency error nd TVE totl vector error of the fundentl frequency coponent re estited. Copring to the DFT bsed ethods in [5]-[7] the lgorith cn output the frequency nd phsor preters in bout 4 illiseconds. The ethod using three consecutive sples of the instntneous signl in [9], [0], denoted s MV, chieves the uncertinty of 0 illion Hz. But they require higher spling frequency 6.4 Hz nd higher nd the dditionl tie dely pproxitely two cycles introduced by the bnd pss filtering. The results re shown in Figure 3. The output ccurcy cn be iproved by extending the dt window. Siultion results show tht the xiu frequency error nd TVE cn be reduced to 0.05 Hz nd 0.7% respectively when l s is extended to hlf cycle. 5 x n = = A cosπ f n T + ϕ + e n 4.38

113 95 Figure 3 Sttic test results using qurter cycle dt window 4.5. Noise Test The inherent noise rejection cpbility of the lgorith is investigted by the noise test. The signl odel for sttic test is used. Let the fundentl frequency te the noinl vlue 60 Hz. For ech level of the Gussin noise three dt windows qurter cycle, hlf cycle nd one cycle were pplied. The test ws conducted using the ethod MV except pplying the vrible dt windows becuse the MV hs fixed size of dt window. Ech cse ws perfored 0 ties nd the xiu vlue of the frequency estite error for both RWT nd MV, nd TVE for RWT re shown in Tble 4. As one cn expect the better noise rejection cn be obtined by slowing down the output response, i.e. prolonging the window spn. The ccurcy of RWT with one cycle window is in the se level with tht of MV. The MV requires extr dely cused by filtering.

114 96 Noise Level SNR 0.% 60dB 0.3% 50dB % 40dB 3.% 30dB Tble 4 Test results for noise tests Window l s cycle RWT f Error Hz RWT TVE % MV f Error Hz Dynic Test. Frequency Rp The following synthesized sinusoidl signl with frequency rp is used to perfor the frequency rp tests. x n = A cosπ f n T + π df n T + ϕ 4.39 df is the frequency rp rte. The signl frequency strts fro 59 Hz followed by positive rp +0 Hz / sec strting t 0. second nd ending t 0.3 second, nd then stys t 6 Hz for nother 0. second. Figure 3 shows the estited frequencies nd the true vlues. The trnsient behvior t the signl strt nd ech discontinuity re shown s

115 97 well. One cn see tht the outputs follow the inputs very closely nd fst. The lgorith is ble to output in bout four illiseconds with qurter cycle window. The xiu error during rp is 0.0 Hz. As discussed in the noise test using ore dt cn iprove the trcing ccurcy but results in the lower response s trde-off. Figure 3 Frequency rp test results b. Step Chnge To evlute the dynic response when exposed to n brupt signl chnge, positive step followed by reverse step bc to the strting vlue under vrious conditions is pplied to the plitude, phse ngle nd frequency of sinusoidl signl respectively. Studies indicte tht under ll three types of steps the lgorith shows siilr dynic behvior. The results of the plitude step 0% of norl vlue, phse step π/8 rd nd frequency step Hz re presented by Figure 33, Figure 34 nd Figure 35 respectively. The steps occur t 0.0s nd 0.06s. One cn observe tht

116 98 the outputs trc the chnges in inputs very fst. Figure 33 Dynic response for plitude step Figure 34 Dynic response for phse ngle step Figure 35 Dynic response for frequency step

117 99 To investigte the effect of pre-filtering on the lgorith dynic perfornce third order Butterworth low-pss filter with cutoff frequency 30 Hz is used to process the input signls. Figure 36 shows the result of plitude step test. Copring to Figure 33 which shows the trnsient behvior without signl pre-filtering, one cn see tht the low-pss filter enlrges the overshoot nd undershoot, nd slows the response fro 4 illiseconds to 0 illiseconds through it is still fster thn the DFT-bsed ethods nd instntneous sple bsed ethods. Figure 36 Dynic response for plitude step with pre-filtering c. Modultion A sinusoidl odultion signl odel is used to siulte the trnsient progress of voltge nd current signls during power swing. Its plitude nd phse ngle re pplied with siultneous odultion s shown in the following expression: x n = A + cosπ f n T x

118 00 cos π f n T + cosπ f n T π 4.40 where f is the odultion frequency, x is the plitude odultion fctor, nd is the phse ngle odultion fctor. Eqution B.-4 in the Appendix B provides the true vlue of frequency, plitude nd phse ngle for the odulted signl odel t output sple. f Hz Tble 5 Test results for odultion tests RWT Δf i Hz MV Δf i Hz TVE RWT i % σ i % Let x = 0., = 0. rdin nd odultion frequency vry fro 0. Hz to Hz in 0. Hz step. The results re copred to the instntneous sple bsed ethod MV. The en of frequency devition Δf i obtined by RWT nd MV, nd the en i nd stndrd devition σ i of the TVE by RWT in one second re clculted. As shown in Tble 5, the lgorith chieves good dynic perfornce when exposed to signl oscilltions.

119 Trnsient Test A 30 V power networ is odeled in EMTP to generte wvefors for testing the perfornce when eliinting decying DC offset. A three-phse fult is pplied nd the three-phse currents re used s input signls. Figure 37 shows the phse-a current wvefor. One cn see tht the signl is continted with decying DC coponent nd high frequency noise during the beginning of post-fult. The third order Butterworth low-pss filter with cutoff frequency 30 Hz is used to ttenute the high frequency coponents. Preters estition for the stedy stte twenty cycles fter the fult occurs is used s reference to esure the totl vector errors. Figure 37 Phse-A current wvefor As shown in Tble 6 the results re copred with the conventionl full cycle DFT FCDFT, hlf cycle DFT HCDFT ethods, lest error squre ethod LES, siplified lgorith SIM3 in [3] nd hybrid ethod HM in [30]. In Tble 6 t s is the

120 0 tie in cycles when the TVEs re esured. For the high ccurcy the lgorith ws djusted to three-qurter cycle window spn. Results show tht the ccurcy is coprble to those of LES, SIM3 nd HM ethods while the proposed lgorith requires shorter dt window, which results in fster response. Tble 6 Test results for decying DC offset Filter t s cycle I A TVE % I B TVE % I C TVE % FCDFT HCDFT LES SIM HM RWT Sury This section proposes new wvelet function nd its recursive wvelet trnsfor. The ethod llowing rel tie estition of power syste frequency, gnitude nd phse while eliinting the ipct of decying DC coponent bsed on RWT is proposed. The lgorith dvntges re surized s follows: The lgorith fetures rpid response nd ccurte result over wide rnge of frequency devitions. It uses only qurter cycle of input signls for outputting frequency, gnitude nd phse results for signl continted with

121 03 hronics. The spling rte nd observed window size cn be chosen to eet selected pplictions requireents. Anlysis of the lgorith convergence chrcteristics indictes tht the higher the spling rte, the shorter the coputtion dt window nd fster the rte the ethod outputs phsor, nd vice vers. The decying DC coponent cn be copletely reoved by estiting its preters using RWT. The perfornce of the proposed lgorith is evluted under vriety of conditions including sttic stte, dynic stte nd trnsient stte. Copring with other techniques results deonstrte the dvntges. Coputtion burden nlysis indictes tht the coputtion requireent is oderte. Thus this pproch cn stisfy the tie criticl dend of the rel tie pplictions in power systes.

122 04 5. CHARACTERIZING DYNAMIC BEHAVIOR USING STEP SIGNALS * 5. Introduction As the developent of Srt Grid projects, nuber of coercil PMUs hve been deployed in the estern nd western systes in North Aeric. There re ny copnies copeting in this ret. Thus the perfornce of ech individul PMU potentilly becoes n essentil spect tht could directly ffect the perfornce of the entire syste. The issues for current test ethodology nd tools hve been discussed in Section.., tht tls bout the PMU responses to step signl, which is typicl signl in dynic conditions, hve not been studied in pst efforts [33]-[5]. This section presents test ethodology nd tools for chrcterizing dynic behvior of PMUs when exposed to step signls. A lest-squre liner-fit bsed phsor estition ethod for chieving high ccurcy of reference phsors nd ethod for interleving signl steps with tiestps to equivlently increse the reporting rte of output phsors so tht they precisely depict PMU step behvior re presented. Three coercil PMUs re selected to perfor step tests using the synchrophsor test syste, * Prt of the teril in this section is reprinted fro Chrcterizing dynic behvior of PMUs using step signls by Jinfeng Ren, Mlden Kezunovic nd Gerrd Stenben, Europen Trnsctions on Electricl Power, DOI: 0.00/etep, copyright 00 by John Wiley & Wiley & Sons, Ltd.

123 05 which will be described in this section. A set of progrs re developed bsed on the dynic test syste to utote step test procedures. Four types of tests re perfored with blnced nd unblnced three-phse step signls s reference signls to chrcterize the step responses of PMUs. Four perfornce indices for step tests re defined to evlute the dynic perfornce. The rest of this section is orgnized s follows: this section presents the ethod for estiting reference phsors. The test ipleenttion frewor of the step test progrs re described in Section 5.3. The test pln nd perfornce indices for chrcterizing PMU responses re specified in this section s well. Test results nd contributions re surized in Section 5.4 nd Section 5.5 respectively. 5. Coputing Reference Phsors 5.. Phsor Estition Method PMUs provide vlues for the voltge nd current phsors t reporting ties synchronized to UTC, which provided by tie code. This is done by spling the respective signls round the UTC tie code, selecting nuber of the sples windowing, nd nlyzing the dt with odel. When testing PMUs the test systes do soething very siilr. They sple the voltge nd current signls pplied to the PMUs with spler synchronized to PPS series of pulse chin per second obtined through GPS receiver nd nlyze the esureents to deterine the reference vlues

124 06 to which the PMU output vlues re copred. This section describes the odel nd windowing ethods used in the step tests. To estite the plitude, phse ngle nd dc coponent of the reference esureent, three-preter liner fit odel is eployed. Consider sinusoidl signl odel expressed s follows: y = A cos π f 0 t + θ + B 5. where A is the plitude, f 0 is the fundentl frequency, θ is the phse ngle, nd B is the dc coponent. If we rewrite 5. we hve y = A cosθ cosπ f 0 t A sinθ sinπ f 0 t + B. 5. If we hve series of sples y, = y, y, yn t ties t t, t,, tn = fro the esureent syste, for exple, then these sples cn be fit to the trix odel X consisting of the three colun vectors s X = [cos π f0 t sinπ f0 t ]. 5.3 The vector of fit coefficients β T T = β β ], where β is the trnspose of β, re [ 0 β deterined in the lest squre error sense by y X β using the Norl eqution. Then we cn copute the plitude, phse ngle, nd dc coponent s follows: A = β +, 0 β θ = rctn β / β0, B = β. 5.4 The step chnge in signl y ffect the ccurcy of phsor estition,

125 07 prticulrly when the dt window crosses the step point. In order to void or iniize this ipct, specil routine is pplied to chieve ccurte vlues, which ct s reference esureents to evlute the errors of the PMU being tested. There re two cses tht need to be discussed: step point t n output tiestp nd step point between two output tiestps. Figure 38 gives n exple for the first cse where step occurs t the tiestp t. P - nd P + re the output phsors t corresponding tiestps t - nd t +. To estite the phsor t t, one cn use the dt window either before or fter t. They re P nd P s shown in Figure 38, nd the phse ngle should be clculted t the end nd beginning of the dt window correspondingly. Figure 38 Exple of the step point t tie stp For the second cse, to estite P nd P + pproprite dt windows should be selected to eliinte the ipct of the step position, s shown in Figure 39. The step position should be nown precisely in dvnce so tht the dt windows for the specil

126 08 tiestps contin sples on only one side of the step. In the synchrophsor test syste, which is described ore fully in section 6, the signl wvefors re typiclly generted with D/A converters opertion t 00 sps nd the dt is spled with A/D converters operting t 50 sps. At these spling rtes the step trnsitions show no sples or t ost one sple. At genertion nd spling rtes of 500 sps, the step trnsitions generlly show to 3 sples. Figure 39 Exple of the step point between tiestps 5.. Incresing Phsor Output Rte A PMU outputs synchrophsors t subultiples of the noinl power syste frequency. The IEEE C37.8 stndrd requires reporting rtes fro 0 fres per second up to xiu of 5 fres per second nd 30 fres per second for 50 Hz nd 60 Hz noinl frequencies respectively. Although ny coercil PMUs feture even higher rtes of up to 50 fres per second nd 60 fres per second for 50 Hz nd

127 09 60 Hz noinl frequencies respectively, soe detils of the response of PMU fcing step chnge of signl could be lost under low output rtes. The ethod described below, which es use of equivlent tie spling, provides solution for this proble. A higher resolution esureent of the PMU s step response is de fro sples ten on repeted esureents of tie shifted step input signls. Becuse the signl genertion is synchronized with UTC, the bsolute phse vlues re the se for ties t = t, reltive to ny UTC on second tie., t, t n Assue set of output phsors P P P t tiestps t t t is,, +,, + esured when pplying step signl, so we hve the reporting rte R / t t. = We repetedly pply the se step signl N ties, however, with tieshift of t = t t / N ong ech other reltive to the PMU reporting ties. Figure 40 N sets of output phsors obtined by repeted esureents

128 As shown in Figure 40 we obtin N sets of output phsors: P, P, P, + P N N, P, P +,, P, P, P N +. If one interleves those phsors in ccordnce with their tiestps reltive to the step tie by the wy depicted in Figure 4, then one chieves the reporting rte R = / t = N / t t, which is n N ultiple of the originl reporting rte R. The effectiveness is presented in Figure 4 nd Figure 43, which disply output phsors of PMU before nd fter interleving respectively, where N is 0. Figure 4 Interleving of phsors

129 Figure 4 Output phsors of PMU before interleving Figure 43 Output phsors of PMU fter interleving

130 5.3 Ipleenttion of Step Test The step tests were perfored on the synchrophsor test lbortory setup developed t TAMU. The syste will be described in detil in Section 6. This section will focus on wht to test nd how to perfor the test Test Pln Three coercil PMUs were selected to investigte the dynic behvior using the proposed step test ethod nd tools. These PMUs hve vrious fetures, such s filter type, output phsor type, reporting rte, couniction ediu, nd so on, which re surized in Tble 7. Three-phse voltges nd currents re represented s VA, VB, VC, IA, IB nd IC, while three-sequence voltges nd current re represented s V, V, V0, I, I nd I0. Tble 7 Feture sury of PMUs being tested Feture PMU A PMU B PMU C Filter Type Optionl Optionl Optionl Adptive Tuning Alwys on Alwys on Selectble Output Phsors Mx Reporting Rte fre /sec VA, VB, VC, V, IA, IB, IC, I 50 for 50 Hz 60 for 60 Hz VA, VB, VC, V,V,V0, IA, IB, IC, I, I, I0 50 for 50 Hz 60 for 60 Hz VA, VB, VC, V,V,V0, IA, IB, IC, I, I, I0 50 for 50 Hz 60 for 60 Hz Couniction Seril Port Ethernet Ethernet GPS Receiver IRIG-B input IRIG-B input Built-in

131 3 Tble 8 Description of test types nd conditions Test Type Reference Condition Description Mgnitude: ±0% step of noinl gnitude Phse: 0 step of inception ngle Recovery gnitude: fro zero gnitude of one phse to noinl. Recovery phse: fro norl phse ngle of one phse to 80 Blnced 3-phse voltge nd current signls, gnitude noinl, noinl frequency Blnced 3-phse voltge nd current signls, noinl gnitude, noinl frequency Unblnced, gnitude of non-stepped phses noinl, norl phse ngle, noinl frequency Blnced, gnitude of ll phses noinl, norl phse ngle on non-stepped phses, noinl frequency Fro stedy stte, pply blnced gnitude step, followed by reversed step bc to the strting stte. Fro stedy stte, pply blnced phse step, followed by reversed step bc to the strting stte. Fro stedy stte, gnitude of one phse steps fro zero to noinl, followed by the reversed step bc to the strting stte. Fro stedy stte, phse ngle of one phse steps fro norl to 80, followed by the reversed step bc to the strting stte. In ters of proposed updte of Section 5.3 of IEEE C , to ccoodte dynic phsor coplince four types of step tests: gnitude test, phse test, recovery gnitude test nd recovery phse test were perfored on three selected PMUs described bove. Descriptions of test types nd test conditions re listed in Tble 8. Four perfornce indices re esured to chrcterize the dynic response of PMUs when exposed to step signls: response tie, settling tie, overshoot nd undershoot, s illustrted in Figure 44. Response tie is defined s the tie intervl fro when the step chnge response leves the % TVE until it re-enters % TVE of the

132 4 finl vlue. Settling tie is defined s the tie intervl fro when the trnsient signl first enters % TVE of the finl vlue until it stys within % TVE of the finl vlue. Overshoot nd undershoot re defined s the differences between xiu, iniu vlues of trnsient signl fter first entering % TVE of the finl vlue nd the finl vlue respectively. Besides, TVE, errors of the gnitude, phse ngle, frequency nd rte of chnge of frequency re esured s well to evlute the ccurcy levels of PMUs. Once the gnitude error Δv in percent of the noinl vlue nd the phse error Δθ in degrees re vilble, the expression for TVE is given by TVE = v + θ / 0.573, where is the rcsine of % in degree. Figure 44 Illustrtion of perfornce indices

133 Test Procedure One chllenge for the step test is how to efficiently perfor hundreds of test cses on different PMUs. A set of progrs for the step tests re developed bsed on the dynic test syste to utote the test procedures. The lgoriths for estiting the reference phsor re used in these progrs. Figure 45 displys the ipleenttion frewor of the step test progrs. The test procedures re outlined s follows:. Initite test environent, such s genertion nd spling rtes, signl types nd etc., set up clibrtor nd PMU being tested. b. Generte test signls nd pply to the PMU under test. It should be noted tht the clibrtor nd PMU receive exctly the se test signls. c. Estite reference phsors using the ethod proposed in 5., collect nd decode phsors esured by PMU. d. Line up reference nd esureent phsors ccording to the tiestps, nd clculte perfornce indices. e. Disply nd store test results through GUI.

134 6 Figure 45 Frewor of step test progrs 5.4 Test Results Four types of step tests s described in Tble 8 were perfored on the three coercil PMUs described in Tble 7. The reporting output rte for the PMUs ws set to 30 fres per second, i.e. the reporting period F s = /30 s. To study the effect of the inception ngle on test results, ech test runs with the inception ngle of voltges nd currents fro 0º to 340º in 30º steps. The inception ngle is the positive sequence phse ngle of the pplied signls t the tie of the step. Vrious digitl filter types for ech PMU were studied s well. In su, over one thousnd step cses were perfored on ech PMU.

135 7 Figure 46 Illustrtion of perfornce indices Test results re presented in Appendix C. Figure 55 - Figure 58 disply the gnitude or phse ngle nd TVE of the positive sequence voltge for the four types of step tests. For PMU A, two steps for ech type of step tests were pplied t 0.4 s nd 0.8 s, respectively. For PMU B nd PMU C, two steps for ech type of step tests were pplied t 0. s nd 0.4 s, respectively. Ech curve consists of the result with different inception ngles fro 0º to 340º in 30º steps by overlying the. Soe of the perfornce indices describing the dynic step trnsition progresses re given in Tble 6 - Tble 9, where T resp, T set, O s nd U s re response tie, settling tie, overshoot nd undershoot, respectively s illustrted in Figure 46. Their vlues re clculted s xiu vlues ong different inceptions for the first step prt. The uncertinty in

136 8 these vlues for the test syste is bout 0.5 μs for tie nd 0.05% for gnitude. This dt ws ten with n interleve fctor N of 0. The vlues of T resp, nd T set re esured in units of reporting rte periods, rrp. For these tests the reporting rte ws 30 fres per second so rrp = 33.3 s. The overshoot nd undershoot, O s nd U s, re esured in percent of the step height. Fro the test results, we cn conclude: PMU A exhibits lrge post step ripple on ll tests. The settling tie in ll tests exceeds.0 rrp nd the overshoot is over 0% of the step. Tht y result fro the chrcteristics of the filter being used. PMU B shows very little ripple on ll tests nd PMU C shows sll syetric pre step ripple nd post step ripple. Their response tie nd settling tie re liited within.0 rrp for gnitude nd phse tests while.0 rrp for recovery gnitude nd recovery phse tests. The recovery tests present siilr trnsient responses with the norl step tests except tht they re esured reltive to the higher step vlues in perfornce indices. The inception ngle for both voltge nd current hs brely ny effect on the dynic perfornce. Thus, ny ngle fro -80 º to +80 º cn be piced s the reference condition for testing.

137 9 5.5 Sury PMUs s tool for esuring synchronized phsors hs gined wide cceptnce in enhncing the onitoring of power grids. However, the perfornce of ech individul PMU nufctured by different copnies y vry gretly. Stndrds for the perfornce requireents hve been de to proote the interoperbility of PMUs. These stndrdiztion efforts should fcilitte their rpid introduction into ny power syste pplictions. To proote the coon response of PMUs to rpid grid chnges, this section proposes n pproch to chrcterize the dynic perfornce of PMUs when exposed to step signls, which re surized s follows: The techniques used to chieve high ccurcy nd high resolution of reference phsors includes the lest squre liner fit, dptive dt window, nd interleving ethod. Four test types with blnced nd unblnced step signls re described. Step test progrs re developed to utote the test procedures. Three coercil PMUs re selected to perfor step tests using the synchrophsor test syste. Test results including output phsors nd perfornce indices indicte unique chrcteristics for soe PMUs nd good dynic behvior consistency ong ost of the tested PMUs.

138 0 6. EVALUATING CONFORMANCE PERFORMANCE 6. Introduction In the deployent of the IEDs for substtion synchronized esureent pplictions, the focus t the oent is on two pproches: use of PMUs dedicted high precision recording instruents, nd b use of PMU-enbled IEDs DFRs, DPRs, DDRs, etc. tht hve PMU esureent cpbility. Mny utilities will use ixed solutions fro ultiple vendors due to vrious equipent purchsing prctices nd/or phsed expnsions of syste solution over n extended period of tie. Using PMUs fro different vendors or ixing PMUs nd PMU-enbled IEDs y produces interoperbility issues in syste solution. To resolve such issues, reference lgoriths nd test pln need to be developed to verifying the interoperbility perfornce. As ddressed in Section.. nd Section.., the issue how to evlute the confornce perfornce of PMUs nd PMU-enbled IEDs ginst the new synchrophsor stndrd so tht the interoperbility perfornce cn be iproved hs not been studied erlier. The disserttion develops test ethodology nd tools to fulfill this objective. The rest of this section is orgnized s follows. The reference signls nd scenrios for verifying the confornce test re described in Section 6.. Section 6.3 specifies the pltfor for perforing the confornce test. This includes descriptions of

139 reference PMU nd lbortory setup. Test results nd brief sury for six coercil synchrophsor units re presented in Section 6.4 nd 6.5 respectively. 6. Confornce Test References The confornce under specific test conditions is evluted by copring the totl vector error TVE, plitude, phse ngle, frequency, nd rte of chnge of frequency ROCOF estites to the corresponding reference vlues. The test conditions including stedy-stte nd dynic stte re consistent with those defined in C [5] nd C37.8. drft [5]. The theticl odels used to crete test signls for stedy nd dynic sttes re given in Tble 9. Tble 9 Test signl odels for confornce test Test Type Signl Model Note Dynic Stedy stte Modultion Step chnge Frequency rp xt = X cos πft + φ xt = X [ + x cos πf t] cos [πf 0 + cos πf t π] xt = X [ + x u t] cos [πf 0 t + u t] xt = X cos πf 0 t + πf d t + φ X : plitude φ: initil ngle f: frequency x, : plitude, phse odultion fctor f : odultion frequency ut: unit step function x, : plitude, phse step fctor f 0 : noinl frequency f d : frequency chnging rte

140 The reference scenrios for stedy stte conditions re described in Tble 0. For dynic scenrios, including the odultions nd step chnges in plitude nd phse ngle, nd the rp chnges in frequency re described in Tble, Tble nd Tble 3, respectively. Vrying Quntity Voltge plitude Tble 0 Test scenrios for stedy stte condition Reference Condition 00 % rted, constnt phse nd noinl frequency Vrying Rnge Clss P Clss M 80 0% 0 0% Current plitude 0 00% 0 00% Phse ngle Constnt ngle ± π rd ± π rd Frequency Noinl frequency ±.0 Hz F s 0: ±.0 Hz; F s >0: lesser of ±F s /5 Hz or ±5 Hz Tble Test scenrios for bndwidth condition Vrying Quntity Aplitude nd phse ngle odultion: x = 0. p.u. = 0. rd Phse ngle odultion: = 0. rd Reference Condition 00 % rted, noinl frequency 00 % rted, noinl frequency Vrying Rnge Clss P Clss M Modultion frequency f : 0. Hz to lesser of F s /0 Hz or Hz Modultion frequency f : 0. Hz to lesser of F s /5 Hz or 5 Hz Tble Test scenrios for step chnge condition Vrying Quntity Aplitude Phse ngle Reference Condition 00 % rted, noinl frequency 00 % rted, noinl frequency Vrying Rnge Clss P Clss M ± 0% ± 0% ± π/8 rd ± π/8 rd

141 3 Tble 3 Test scenrios for frequency rp condition Vrying Quntity Liner frequency rp: +.0 Hz/s Liner frequency rp:.0 Hz/s Reference Condition 00 % rted, noinl frequency 00 % rted, noinl frequency Vrying Rnge Clss P Clss M ±.0 Hz Lesser of ± Fs/5 Hz or ± 5.0 Hz 6.3 Synchrophsor Test Syste 6.3. Lbortory Setup The confornce tests re perfored using synchrophsor test nd clibrtion syste developed t TAMU s lb, s shown in Figure 47. It consists of GPS receiver used to synchronize the syste to UTC, signl cquisition syste used to generte nd sple test signls up to 500 Hz, three voltge nd current plifiers connected to PMUs nd PMU enbled IEDs providing test signls t typicl level, three voltge ttenutors nd three current shunts. GPS signl, IRIG-B nd IEEE 588 v re vilble for vrious synchrophsor devices. A series of softwre odels is developed in LbVIEW [0] for ipleenting stedy stte nd dynic tests. The softwre is cpble of utoting test procedures nd nlyzing test results.

142 4 Figure 47 Synchrophsor test nd clibrtion syste The detiled descriptions for the hrdwre nd softwre of the test syste re presented respectively s follows.. Hrdwre Figure 48 shows the rchitecture of the synchrophsor test syste. Its odules re presented s follows: Tie synchroniztion options provides reference UTC tie sources to device under test. The options include direct GPS signl, IRIG-B nd IEEE 588 PTP. Dt cquisition syste converts digitl test signls to nlog signls s inputs to plifiers or synchrophsor units with low-voltge interfces; sples

143 5 voltge nd current signls for phsor estition odule. Figure 48 Synchrophsor test syste rchitecture Reference signl source nd conditioner provides voltge nd current signls in noinl level voltge: 00 V, current: 5A or A; scles high voltge signls down to the low level voltge 0 V for dt cquisition syste. Syncrophsor dt interfce provides connection nd dt trnsfer for PMUs. The interfces include seril port nd Ethernet connection. Reference PMU provides reference phsors copred to the phsors esured by device under test. The detiled description will be presented in the following section.

144 6 GUI Interfce provides console for controlling, onitoring nd collecting test results. b. Softwre The softwre for perforing the confornce test consists of over 80 routines, five of which operte s in interfces for user to run stedy stte nd dynic tests. The step test hs individul progrs becuse of the use of specil process. One cn refer to Section 5 for detil. The in progrs nd their functions re described s follows: Test initiliztion initilizes test conditions, such s setting the preters of test signls, signl genertion nd spling configurtions, PT nd CT rtios, output phsors nd etc. A screenshot of the front pnel is given in Figure 49. Dt trnsfer connects PMUs under test to controller nd trnsfers dt between the. This progr hs two options: one for connection using seril port; nother for connection using Ethernet. The control pnel of the progr for n Ethernet connection is given in Figure 50. The progr for seril port uses siilr interfce but different couniction odules. Dt processing includes the processes of coputing reference phsors, decoding esured phsors fro binry dt defined in synchrophsor stndrds, nd lign the reference phsors nd esured phsors ccording to UTC tie. A screenshot of front pnel for ligning dt gin tiestp is given in Figure 5.

145 7 Figure 49 A screenshot of front pnel for test initiliztion Figure 50 A screenshot of front pnel for dt trnsfer

146 8 Figure 5 A screenshot of front pnel for phsor lignent Error nlysis refors the reference esureents ccording to the output for of device under test; coputes the perfornce indices TVE, gnitude error, phse error, frequency error nd rte of chnge of frequency error nd displys the results of interest. A screenshot of front pnel for error nlysis is given in Figure 5.

147 9 Figure 5 A screenshot of front pnel for error nlysis 6.3. Reference PMU The reference lgorith for estiting phsors is described in Section It is derived bsed on dynic signl odel nd uses qudrtic for to pproch the chnging preters. For rel-tie ppliction, this lgorith cn chieve very good ccurcy ginst the requireents specified in the stndrds. For testing, becuse the frequency vrible of test signl is nown, insted of using the estited frequency, we use the true vlue of test signl s frequency to chieve higher ccurcy. We use constnt frequency f s = 50 Hz to sple the input voltge nd current signls. The size of dt window for estiting phsor is one cycle period of the noinl frequency, i.e. the nuber of sples within dt window is 50000/ Let F s be the PMU reporting rte fre per second. For soe reporting rte, the output